diff options
Diffstat (limited to 'Silicon')
38 files changed, 4639 insertions, 0 deletions
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Guid/AcpiVariable.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Guid/AcpiVariable.h new file mode 100644 index 0000000000..ac31b4f9fc --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Guid/AcpiVariable.h @@ -0,0 +1,70 @@ +/** @file
+ GUIDs used for ACPI variables.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ACPI_VARIABLE_H_
+#define _ACPI_VARIABLE_H_
+
+#define EFI_ACPI_VARIABLE_GUID \
+ { \
+ 0xaf9ffd67, 0xec10, 0x488a, 0x9d, 0xfc, 0x6c, 0xbf, 0x5e, 0xe2, 0x2c, 0x2e \
+ }
+
+#define ACPI_GLOBAL_VARIABLE L"AcpiGlobalVariable"
+
+//
+// The following structure combine all ACPI related variables into one in order
+// to boost performance
+//
+#pragma pack (1)
+typedef struct {
+ UINT16 Limit;
+ UINTN Base;
+} PSEUDO_DESCRIPTOR;
+#pragma pack()
+
+typedef struct {
+ BOOLEAN APState;
+ BOOLEAN S3BootPath;
+ EFI_PHYSICAL_ADDRESS WakeUpBuffer;
+ EFI_PHYSICAL_ADDRESS GdtrProfile;
+ EFI_PHYSICAL_ADDRESS IdtrProfile;
+ EFI_PHYSICAL_ADDRESS CpuPrivateData;
+ EFI_PHYSICAL_ADDRESS StackAddress;
+ EFI_PHYSICAL_ADDRESS MicrocodePointerBuffer;
+ EFI_PHYSICAL_ADDRESS SmramBase;
+ EFI_PHYSICAL_ADDRESS SmmStartImageBase;
+ UINT32 SmmStartImageSize;
+ UINT32 NumberOfCpus;
+ UINT32 ApInitDone;
+} ACPI_CPU_DATA;
+
+typedef struct {
+ //
+ // Acpi Related variables
+ //
+ EFI_PHYSICAL_ADDRESS AcpiReservedMemoryBase;
+ UINT32 AcpiReservedMemorySize;
+ EFI_PHYSICAL_ADDRESS S3ReservedLowMemoryBase;
+ EFI_PHYSICAL_ADDRESS AcpiBootScriptTable;
+ EFI_PHYSICAL_ADDRESS RuntimeScriptTableBase;
+ EFI_PHYSICAL_ADDRESS AcpiFacsTable;
+ UINT64 SystemMemoryLength;
+ ACPI_CPU_DATA AcpiCpuData;
+} ACPI_VARIABLE_SET;
+
+extern EFI_GUID gEfiAcpiVariableGuid;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Guid/AcpiVariableCompatibility.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Guid/AcpiVariableCompatibility.h new file mode 100644 index 0000000000..429c149435 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Guid/AcpiVariableCompatibility.h @@ -0,0 +1,68 @@ +/** @file
+ Definitions for data structures used in S3 resume.
+
+ Copyright (c) 2011 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _ACPI_VARIABLE_COMPATIBILITY_H_
+#define _ACPI_VARIABLE_COMPATIBILITY_H_
+
+#define EFI_ACPI_VARIABLE_COMPATIBILITY_GUID \
+ { \
+ 0xc020489e, 0x6db2, 0x4ef2, {0x9a, 0xa5, 0xca, 0x6, 0xfc, 0x11, 0xd3, 0x6a } \
+ }
+
+#define ACPI_GLOBAL_VARIABLE L"AcpiGlobalVariable"
+
+extern EFI_GUID gEfiAcpiVariableCompatiblityGuid;
+
+typedef struct {
+ BOOLEAN APState;
+ BOOLEAN S3BootPath;
+ EFI_PHYSICAL_ADDRESS WakeUpBuffer;
+ EFI_PHYSICAL_ADDRESS GdtrProfile;
+ EFI_PHYSICAL_ADDRESS IdtrProfile;
+ EFI_PHYSICAL_ADDRESS CpuPrivateData;
+ EFI_PHYSICAL_ADDRESS StackAddress;
+ EFI_PHYSICAL_ADDRESS MicrocodePointerBuffer;
+ EFI_PHYSICAL_ADDRESS SmramBase;
+ EFI_PHYSICAL_ADDRESS SmmStartImageBase;
+ UINT32 SmmStartImageSize;
+ UINT32 NumberOfCpus;
+} ACPI_CPU_DATA_COMPATIBILITY;
+
+typedef struct {
+ //
+ // Acpi Related variables
+ //
+ EFI_PHYSICAL_ADDRESS AcpiReservedMemoryBase;
+ UINT32 AcpiReservedMemorySize;
+ EFI_PHYSICAL_ADDRESS S3ReservedLowMemoryBase;
+ EFI_PHYSICAL_ADDRESS AcpiBootScriptTable;
+ EFI_PHYSICAL_ADDRESS RuntimeScriptTableBase;
+ EFI_PHYSICAL_ADDRESS AcpiFacsTable;
+ UINT64 SystemMemoryLength;
+ ACPI_CPU_DATA_COMPATIBILITY AcpiCpuData;
+ //
+ // VGA OPROM to support Video Re-POST for Linux S3
+ //
+ EFI_PHYSICAL_ADDRESS VideoOpromAddress;
+ UINT32 VideoOpromSize;
+ //
+ // S3 Debug extension
+ //
+ EFI_PHYSICAL_ADDRESS S3DebugBufferAddress;
+ EFI_PHYSICAL_ADDRESS S3ResumeNvsEntryPoint;
+} ACPI_VARIABLE_SET_COMPATIBILITY;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Guid/MemoryConfigData.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Guid/MemoryConfigData.h new file mode 100644 index 0000000000..1cca0d4326 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Guid/MemoryConfigData.h @@ -0,0 +1,30 @@ +/** @file
+ GUID used for Memory Configuration Data entries in the HOB list.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MEMORY_CONFIG_DATA_GUID_H_
+#define _MEMORY_CONFIG_DATA_GUID_H_
+
+#define EFI_MEMORY_CONFIG_DATA_GUID \
+ { \
+ 0x80dbd530, 0xb74c, 0x4f11, 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 \
+ }
+
+#define EFI_MEMORY_CONFIG_VARIABLE_NAME L"MemoryConfig"
+
+extern EFI_GUID gEfiMemoryConfigDataGuid;
+extern CHAR16 EfiMemoryConfigVariable[];
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Guid/SaDataHob.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Guid/SaDataHob.h new file mode 100644 index 0000000000..afc5495927 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Guid/SaDataHob.h @@ -0,0 +1,60 @@ +/** @file
+ The GUID definition for SaDataHob.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SA_DATA_HOB_H_
+#define _SA_DATA_HOB_H_
+
+#include <SaAccess.h>
+#include <Base.h>
+
+extern EFI_GUID gSaDataHobGuid;
+
+#pragma pack(1)
+
+//
+// HG GPIO Data Structure
+//
+typedef struct {
+ UINT32 CommunityOffset; ///< GPIO Community
+ UINT16 PinOffset; ///< GPIO Pin
+ BOOLEAN Active; ///< 0=Active Low; 1=Active High
+} HG_GPIO_INFO;
+
+//
+// HG Info HOB
+//
+typedef struct _HG_INFO_HOB {
+ UINT8 RootPortDev; ///< Device number used for SG
+ UINT8 RootPortFun; ///< Function number used for SG
+ UINT8 HgEnabled; ///< HgEnabled (0=Disabled, 1=Enabled)
+ UINT16 HgSubSystemId; ///< Hybrid Graphics Subsystem ID
+ UINT16 HgDelayAfterPwrEn; ///< Dgpu Delay after Power enable using Setup option
+ UINT16 HgDelayAfterHoldReset; ///< Dgpu Delay after Hold Reset using Setup option
+ HG_GPIO_INFO HgDgpuHoldRst; ///< This field contain dGPU HLD RESET GPIO value and level information
+ HG_GPIO_INFO HgDgpuPwrEnable; ///< This field contain dGPU_PWR Enable GPIO value and level information
+} HG_INFO_HOB;
+
+//
+// System Agent Data Hob
+//
+typedef struct {
+ EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID Hob type structure
+ UINT8 IpuAcpiMode; ///< IPU ACPI mode: 0=Disabled, 1=IGFX Child device, 2=ACPI device
+ HG_INFO_HOB HgInfo; ///< HG Info HOB
+} SA_DATA_HOB;
+
+#pragma pack()
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Library/DxeSaPolicyLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Library/DxeSaPolicyLib.h new file mode 100644 index 0000000000..361933c779 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Library/DxeSaPolicyLib.h @@ -0,0 +1,83 @@ +/** @file
+ GPrototype of the DxeSaPolicyLib library.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DXE_SA_POLICY_LIB_H_
+#define _DXE_SA_POLICY_LIB_H_
+
+#include <Protocol/SaPolicy.h>
+#include <Library/ConfigBlockLib.h>
+
+/**
+ Creates the default setting of SA Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[in, out] DxeSaPolicy The pointer to get SA Policy protocol instance.
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval Others Internal error when create default SA policy.
+
+**/
+EFI_STATUS
+EFIAPI
+SaCreatePolicyDefaults (
+ IN OUT SA_POLICY_PROTOCOL *DxeSaPolicy
+ );
+
+/**
+ Creates the Config Blocks for SA DXE Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[in, out] SiSaPolicyPpi The pointer to get SI/SA Policy PPI instance.
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+
+**/
+EFI_STATUS
+EFIAPI
+CreateSaDxeConfigBlocks(
+ IN OUT SA_POLICY_PROTOCOL **SaPolicy
+ );
+
+/**
+ Install protocol for SA Policy.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] DxeSaPolicy The pointer to SA Policy Protocol instance.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval Others Internal error when install protocol.
+
+**/
+EFI_STATUS
+EFIAPI
+SaInstallPolicyProtocol (
+ IN SA_POLICY_PROTOCOL *DxeSaPolicy
+ );
+
+/**
+ This function prints the SA DXE phase policy.
+
+ @param[in] DxeSaPolicy The pointer to SA Policy Protocol instance.
+
+**/
+VOID
+SaPrintPolicyProtocol (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ );
+
+#endif // _DXE_SA_POLICY_LIB_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Library/PeiSaPolicyLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Library/PeiSaPolicyLib.h new file mode 100644 index 0000000000..3a83ceab1c --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Library/PeiSaPolicyLib.h @@ -0,0 +1,92 @@ +/** @file
+ Prototype of the PeiSaPolicy library.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_SA_POLICY_LIB_H_
+#define _PEI_SA_POLICY_LIB_H_
+
+#include <Ppi/SaPolicy.h>
+#include <Library/ConfigBlockLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <SaRegs.h>
+
+
+/**
+ Creates the Pre Mem Config Blocks for SA Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[in, out] SiSaPolicyPpi The pointer to get SI/SA Policy PPI instance.
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer.
+
+**/
+EFI_STATUS
+EFIAPI
+SaCreatePreMemConfigBlocks(
+ IN OUT SI_SA_POLICY_PPI **SiSaPolicyPpi
+ );
+
+/**
+ Creates the Config Blocks for SA Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[in, out] SiSaPolicyPpi The pointer to get SI/SA Policy PPI instance.
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlocks (
+ IN OUT SI_SA_POLICY_PPI **SiSaPolicyPpi
+ );
+
+/**
+ Install PPI SiSaPolicyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] SiSaPolicyPpi Pointer of policy structure.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer.
+
+**/
+EFI_STATUS
+EFIAPI
+SiSaInstallPolicyPpi (
+ IN SI_SA_POLICY_PPI *SiSaPolicyPpi
+ );
+
+/**
+ SaInstallPreMemPolicyPpi installs SaPolicyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] SaPreMemPolicyPpi The pointer to SA PREMEM Policy PPI instance.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer.
+
+**/
+EFI_STATUS
+EFIAPI
+SaInstallPreMemPolicyPpi (
+ IN SI_SA_POLICY_PPI *SaPolicyPpi
+ );
+
+#endif // _PEI_SA_POLICY_LIBRARY_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Library/SmbiosMemoryLib.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Library/SmbiosMemoryLib.h new file mode 100644 index 0000000000..479c077c47 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Library/SmbiosMemoryLib.h @@ -0,0 +1,37 @@ +/** @file
+ Header file for SMBIOS Memory library.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SMBIOS_MEMORY_LIB_H_
+#define _SMBIOS_MEMORY_LIB_H_
+
+/**
+ This function will determine memory configuration information from the chipset
+ and memory and report the memory configuration info to the DataHub.
+
+ @param[in] ImageHandle Handle for the image of this driver.
+ @param[in] SystemTable Pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS If the data is successfully reported.
+ @retval EFI_NOT_FOUND If the HOB list could not be located.
+
+**/
+EFI_STATUS
+EFIAPI
+SmbiosMemory (
+ VOID
+ );
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/PlatformBaseAddresses.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/PlatformBaseAddresses.h new file mode 100644 index 0000000000..ebe3968d06 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/PlatformBaseAddresses.h @@ -0,0 +1,115 @@ +/** @file
+ Header file for Platform Base Address definition..
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_BASE_ADDRESSES_H
+#define _PLATFORM_BASE_ADDRESSES_H
+
+//
+// Base Addresses should be listed in this Section
+// Sizes are listed down below in next Section
+//
+#define GMADR_BASE_ADDRESS 0xA0000000
+#define GTTMM_BASE_ADDRESS 0xBF000000
+
+#define XHCI_TEMP_MEM_BASE_ADDRESS 0xC2C00000
+#define SW_BASE_ADDRESS 0xD3800000
+#define MTB_BASE_ADDRESS 0xD3600000
+#define HECI_BASE_ADDRESS 0xD3708000
+#define HECI2_BASE_ADDRESS 0xD3709000
+#define HECI3_BASE_ADDRESS 0xD370A000
+
+#define RTIT_BASE_ADDRESS 0xD3700000
+#define FW_TEMP_BASE_ADDRESS 0xD3400000
+
+#ifndef IPUMM_BASE_ADDRESS
+#define IPUMM_BASE_ADDRESS 0xCF000000
+#endif
+
+#define ACPI_MMIO_BASE_ADDRESS 0xD0000000
+#define SPI_TEMP_MEM_BASE_ADDRESS 0xD2000000
+#define PWM_TEMP_MEM_BASE_ADDRESS 0xD3000000
+#define PCIEX_BASE_ADDRESS 0xE0000000
+
+#define FW_BASE_ADDRESS 0xFE240000
+#define LPSS_I2C0_TMP_BAR0 0xFE910000
+#define MPHY_BASE_ADDRESS 0xFEA00000
+#define CRAB_ABORT 0xFEB00000
+
+#define IO_APIC_BASE_ADDRESS 0xFEC00000
+#define IO_APIC_INDEX_REGISTER IO_APIC_BASE_ADDRESS
+#define IO_APIC_DATA_REGISTER (IO_APIC_BASE_ADDRESS+0x10)
+#define IO_APIC_EOI (IO_APIC_BASE_ADDRESS+0x40)
+
+#define HPET_BASE_ADDRESS 0xFED00000
+
+#define SPI_BASE_ADDRESS 0xFED01000
+#define PBASE 0xFED03000
+#define PUNIT_BASE_ADDRESS 0xFED06000
+#define ILB_BASE_ADDRESS 0xFED08000
+#define IOBASE 0xFED0C000
+#define MCH_BASE_ADDRESS 0xFED10000
+
+#define DMI_BASE_ADDRESS 0xFED18000 // Direct Media Interface
+#define RCBA_BASE_ADDRESS 0xFED1C000 // Root Complex Base Address
+#define TPM_BASE_ADDRESS 0xFED40000 // Trusted Platform Module
+#define XHCI_DBC 0xFFD60000 // Reserved For P2P Traffic Targeting the xHCI DBC Endpoint
+#define DEF_VTD_BASE_ADDRESS 0xFED65000 // VT-d Engine
+
+#define PTT_HCI_BASE_ADDRESS 0xFED740000 // Platform Trust Technology HCI
+#define IO_BASE_ADDRESS 0xFED80000 // IO Memory
+#define LOCAL_APIC_BASE_ADDRESS 0xFEE00000 // Local APIC
+
+//
+// Sizes for Base Addresses should be put in this Section
+//
+#define GMADR_SIZE 0x20000000 //512M
+
+#define SPI_TEMP_MEM_SIZE 0x1000 //4K
+#define SW_SIZE 0x800000 //8M
+#define MTB_SIZE 0x100000 //1M
+#define HECI_SIZE 0x1000 //4K
+#define HECI2_SIZE 0x1000 //4k
+#define RTIT_SIZE 0x200 //512B
+#define FW_SIZE 0x200000 //1M
+
+#define ACPI_MMIO_SIZE 0x10000000 //256M can be reduced to actual needs.
+#define GTTMM_SIZE 0x1000000 //16M
+#define PCIEX_SIZE 0x10000000 //256M
+#define ISPMM_SIZE 0x1000000 //16M
+
+#define GCR_BASE_ADDRESS_SIZE 0x1000 //4K
+#define PMC_BASE_ADDRESS_SIZE 0x1000 //4K
+#define PMC_IPC1_BAR1_SIZE 0x2000 //8K
+#define PMC_IPC1_BAR2_SIZE 0x1000 //4K
+#define FW_SIZE 0x200000 //1M
+#define CRAB_ABORT_size 0x100000 //1M
+
+#define IO_APIC_SIZE 0x40 //64B
+#define HPET_SIZE 0x400 //1K
+
+#define SPI_SIZE 0x1000 //4K
+#define MCH_SIZE 0x8000 //32K
+#define XHCI_DBC_SIZE 0x1000 //4K
+#define LOCAL_APIC_SIZE 0x100000 //1M
+
+//
+// PCIe defines
+//
+#define PCIE_MMIO_BASE_ADDRESS 0xE0000000
+#define PCIE_MMIO_SIZE 0x04000000
+
+#endif
+
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/GraphicsConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/GraphicsConfig.h new file mode 100644 index 0000000000..92b49f51f9 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/GraphicsConfig.h @@ -0,0 +1,57 @@ +/** @file
+ Policy definition for Internal Graphics Config Block.
+
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GRAPHICS_CONFIG_H_
+#define _GRAPHICS_CONFIG_H_
+
+#pragma pack(1)
+
+#define GRAPHICS_CONFIG_REVISION 1
+
+extern EFI_GUID gGraphicsConfigGuid;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Block Header
+ UINT32 CdClock : 3;
+ UINT32 PeiGraphicsPeimInit: 1; ///< 0- Disable 1- Enable
+ UINT32 RsvdBits0 : 4; ///< Reserved for future use
+ UINT8 Rsvd1[2]; ///< Offset 14
+ UINT32 GttMmAdr; ///< Offset 16 Address of System Agent GTTMMADR: Default is <b>0xDF000000</b>
+ VOID* LogoPtr; ///< Offset 20 Address of Logo to be displayed in PEI
+ UINT32 LogoSize; ///< Offset 24 Logo Size
+ VOID* GraphicsConfigPtr; ///< Offset 28 Address of the Graphics Configuration Table
+ UINT32 GmAdr; ///< Offset 32 Address of System Agent GMADR: Default is <b>0xC0000000</b>
+ UINT8 PmSupport;
+ UINT8 PavpEnable;
+ UINT8 EnableRenderStandby;
+ UINT8 PavpPr3;
+ UINT8 ForceWake;
+ UINT8 PavpLock;
+ UINT8 GraphicsFreqModify;
+ UINT8 GraphicsFreqReq;
+ UINT8 GraphicsVideoFreq;
+ UINT8 PmLock;
+ UINT8 DopClockGating;
+ UINT8 UnsolicitedAttackOverride;
+ UINT8 WOPCMSupport;
+ UINT8 WOPCMSize;
+ UINT8 PowerGating;
+ UINT8 UnitLevelClockGating;
+} GRAPHICS_CONFIG;
+
+#pragma pack()
+
+#endif // _GRAPHICS_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/HybridGraphicsConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/HybridGraphicsConfig.h new file mode 100644 index 0000000000..69951ff36e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/HybridGraphicsConfig.h @@ -0,0 +1,52 @@ +/** @file
+ Hybrid Graphics policy definitions.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _HYBRID_GRAPHICS_CONFIG_H_
+#define _HYBRID_GRAPHICS_CONFIG_H_
+
+#pragma pack(1)
+
+#define HYBRID_GRAPHICS_CONFIG_REVISION 1
+
+extern EFI_GUID gHybridGraphicsConfigGuid;
+
+//
+// HG GPIO Data Structure
+//
+typedef struct {
+ UINT32 CommunityOffset; ///< GPIO Community
+ UINT16 PinOffset; ///< GPIO Pin
+ BOOLEAN Active; ///< 0=Active Low; 1=Active High
+} HG_GPIO;
+
+//
+// Defines the Switchable Graphics configuration parameters for System Agent.
+//
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Block Header
+ UINT8 RootPortDev; ///< Device number used for SG
+ UINT8 RootPortFun; ///< Function number used for SG
+ UINT8 HgEnabled; ///< HgEnabled (0=Disabled, 1=Enabled)
+ UINT16 HgSubSystemId; ///< Hybrid Graphics Subsystem ID
+ UINT16 HgDelayAfterPwrEn; ///< Dgpu Delay after Power enable using Setup option
+ UINT16 HgDelayAfterHoldReset; ///< Dgpu Delay after Hold Reset using Setup option
+ HG_GPIO HgDgpuHoldRst; ///< This field contain dGPU HLD RESET GPIO value and level information
+ HG_GPIO HgDgpuPwrEnable; ///< This field contain dGPU_PWR Enable GPIO value and level information
+} HYBRID_GRAPHICS_CONFIG;
+
+#pragma pack()
+
+#endif // _HYBRID_GRAPHICS_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/IpuConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/IpuConfig.h new file mode 100644 index 0000000000..2662880eb5 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/IpuConfig.h @@ -0,0 +1,35 @@ +/** @file
+ IPU policy definitions.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _IPU_CONFIG_H_
+#define _IPU_CONFIG_H_
+
+#pragma pack(1)
+
+#define IPU_CONFIG_REVISION 1
+
+extern EFI_GUID gIpuConfigGuid;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Block Header
+ UINT8 SaIpuEnable; ///< Enable SA IPU device: 0=Disable, <b>1=Enable</b>
+ UINT8 IpuAcpiMode; ///< Set IPU ACPI mode: <b>0=AUTO</b>, 1=IGFX Child device, 2=ACPI device
+ UINT32 IpuMmAdr; ///< Address of IPU MMIO Bar IpuMmAdr: Default is <b>0x90000000</b>
+} IPU_CONFIG;
+
+#pragma pack()
+
+#endif // _IPU_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/MemoryConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/MemoryConfig.h new file mode 100644 index 0000000000..68bdd74341 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/MemoryConfig.h @@ -0,0 +1,35 @@ +/** @file
+ Policy definition of Memory Config Block.
+
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MEMORY_CONFIG_H_
+#define _MEMORY_CONFIG_H_
+
+#pragma pack(1)
+
+#define MEMORY_CONFIG_REVISION 1
+
+extern EFI_GUID gMemoryConfigGuid;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Block Header
+ UINT8 EccSupport;
+ UINT16 DdrFreqLimit;
+ UINT8 MaxTolud;
+} MEMORY_CONFIGURATION;
+
+#pragma pack()
+
+#endif // _MEMORY_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/SaMiscConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/SaMiscConfig.h new file mode 100644 index 0000000000..f00ed53f1f --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/SaMiscConfig.h @@ -0,0 +1,41 @@ +/** @file
+ Policy details for miscellaneous configuration in System Agent.
+
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SA_MISC_CONFIG_H_
+#define _SA_MISC_CONFIG_H_
+
+#pragma pack(1)
+
+#define SA_MISC_CONFIG_REVISION 1
+
+extern EFI_GUID gSaMiscConfigGuid;
+
+#ifndef MAX_SOCKETS
+#define MAX_SOCKETS 4
+#endif
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Block Header
+ UINT8 SpdAddressTable[MAX_SOCKETS];
+ UINT8 UserBd;
+ UINT8 PlatformType;
+ UINT8 FastBoot;
+ UINT8 DynSR;
+} SA_MISC_CONFIG;
+
+#pragma pack()
+
+#endif // _SA_MISC_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/SaPolicy.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/SaPolicy.h new file mode 100644 index 0000000000..96107dcc95 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/SaPolicy.h @@ -0,0 +1,80 @@ +/** @file
+ Interface definition details between MRC and platform drivers during PEI phase.
+
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+
+#ifndef _SA_POLICY_PPI_H_
+#define _SA_POLICY_PPI_H_
+
+#include <Uefi.h>
+#include <ConfigBlock.h>
+#include <Ppi/GraphicsConfig.h>
+#include <Ppi/MemoryConfig.h>
+#include <Ppi/IpuConfig.h>
+#include <Ppi/SaMiscConfig.h>
+#include <Ppi/HybridGraphicsConfig.h>
+#include <Ppi/SaPreMemConfig.h>
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gSiSaPolicyPpiGuid;
+extern EFI_GUID gSiSaPreMemPolicyPpiGuid;
+
+/**
+ PPI revision number
+ Any backwards compatible changes to this PPI will result in an update in the revision number
+ Major changes will require publication of a new PPI
+
+**/
+#define SA_POLICY_PPI_REVISION 1
+
+//
+// Generic definitions for device enabling/disabling used by NC code.
+//
+#define DEVICE_ENABLE 1
+#define DEVICE_DISABLE 0
+
+#ifndef MAX_SOCKETS
+#define MAX_SOCKETS 4
+#endif
+
+#define S3_TIMING_DATA_LEN 9
+#define S3_READ_TRAINING_DATA_LEN 16
+#define S3_WRITE_TRAINING_DATA_LEN 12
+
+#ifndef S3_RESTORE_DATA_LEN
+#define S3_RESTORE_DATA_LEN (S3_TIMING_DATA_LEN + S3_READ_TRAINING_DATA_LEN + S3_WRITE_TRAINING_DATA_LEN)
+#endif // S3_RESTORE_DATA_LEN
+
+#pragma pack(1)
+
+
+/**
+ SI SA Policy PPI\n
+ Each config block change history should be listed here\n\n
+
+**/
+typedef struct {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Offset 0-31
+/**
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+
+**/
+} SI_SA_POLICY_PPI;
+
+#pragma pack()
+
+#endif // _SA_POLICY_PPI_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/SaPreMemConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/SaPreMemConfig.h new file mode 100644 index 0000000000..04c9951700 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Ppi/SaPreMemConfig.h @@ -0,0 +1,37 @@ +/** @file
+ Policy definition for SA Pre-Mem Config Block.
+
+ Copyright (c) 2010 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SA_PRE_MEM_CONFIG_H_
+#define _SA_PRE_MEM_CONFIG_H_
+
+#pragma pack(1)
+
+#define SA_PRE_MEM_CONFIG_REVISION 1
+
+extern EFI_GUID gSaPreMemConfigGuid;
+
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Block Header
+ UINT8 IgdDvmt50PreAlloc;
+ UINT8 PrimaryDisplay;
+ UINT8 ApertureSize;
+ UINT8 InternalGraphics;
+ UINT16 GttSize; ///< Selection of iGFX GTT Memory size: 1=2MB, 2=4MB, <b>3=8MB</b>
+} SA_PRE_MEM_CONFIG;
+
+#pragma pack()
+
+#endif // _SA_PRE_MEM_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/GlobalNvsArea.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/GlobalNvsArea.h new file mode 100644 index 0000000000..b32f334f01 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/GlobalNvsArea.h @@ -0,0 +1,520 @@ +/** @file
+ Header file for Global NVS Area definition.
+
+ Copyright (c) 2012 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _GLOBAL_NVS_AREA_H_
+#define _GLOBAL_NVS_AREA_H_
+
+//
+// Includes
+//
+#define GLOBAL_NVS_DEVICE_ENABLE 1
+#define GLOBAL_NVS_DEVICE_DISABLE 0
+
+//
+// Global NVS Area Protocol GUID
+//
+#define EFI_GLOBAL_NVS_AREA_PROTOCOL_GUID \
+{ 0x74e1e48, 0x8132, 0x47a1, 0x8c, 0x2c, 0x3f, 0x14, 0xad, 0x9a, 0x66, 0xdc }
+//
+// Revision id - Added TPM related fields
+//
+#define GLOBAL_NVS_AREA_RIVISION_1 1
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gEfiGlobalNvsAreaProtocolGuid;
+
+//
+// Global NVS Area definition
+//
+#pragma pack (1)
+typedef struct {
+/**
+ Miscellaneous Dynamic Values, the definitions below need to be matched
+ GNVS definitions in Platform.ASL
+
+**/
+ UINT16 OperatingSystem; ///< (00) Operating System
+ UINT8 LidState; ///< (02) Lid State (Lid Open = 1)
+ UINT8 PowerState; ///< (03) Power State (AC Mode = 1)
+ //
+ // Thermal Policy Values
+ //
+ UINT8 ActiveTripPoint; ///< (04) Active Trip Point
+ UINT8 CriticalThermalTripPoint; ///< (05) Critical Trip Point
+ UINT8 BspDigitalThermalSensorTemperature; ///< (06) Digital Thermal Sensor 1 Reading
+ UINT8 ApDigitalThermalSensorTemperature; ///< (07) Digital Thermal Sensor 2 Reading
+ //
+ // Processor Configuration Values
+ //
+ UINT8 ApicEnable; ///< (08) APIC Enabled by SBIOS (APIC Enabled = 1)
+ UINT8 LogicalProcessorCount; ///< (09) Number of Logical Processors if MP Enabled != 0
+ UINT8 CurrentDeviceList; ///< (10) Current Attached Device List
+ UINT16 CurrentDisplayState; ///< (11) Current Display State
+ UINT16 NextDisplayState; ///< (13) Next Display State
+ UINT8 NumberOfValidDeviceId; ///< (15) Number of Valid Device IDs
+ UINT32 DeviceId1; ///< (16) Device ID 1
+ UINT32 DeviceId2; ///< (20) Device ID 2
+ UINT32 DeviceId3; ///< (24) Device ID 3
+ UINT32 DeviceId4; ///< (28) Device ID 4
+ UINT32 DeviceId5; ///< (32) Device ID 5
+ //
+ // Backlight Control Values
+ //
+ UINT8 BacklightControlSupport; ///< (36) Backlight Control Support
+ UINT8 BrightnessPercentage; ///< (37) Brightness Level Percentage
+ UINT8 AlsEnable; ///< (38) ALS Enable
+ UINT8 MorData; ///< (39) Memory Overwrite Request Data
+ UINT32 PPResponse; ///< (40) Physical Presence request operation response
+ UINT8 PPRequest; ///< (44) Physical Presence request operation
+ UINT8 LastPPRequest; ///< (45) Last Physical Presence request operation
+ UINT8 BoardId; ///< (46) Platform board id
+ UINT32 IgdOpRegionAddress; ///< (47) IGD OpRegion base address
+ UINT8 IgdBootType; ///< (51) IGD Boot Display Device
+ UINT8 IgdPanelType; ///< (52) IGD Panel Type CMOs option
+ UINT8 IgdTvFormat; ///< (53) IGD TV Format CMOS option
+ UINT8 IgdTvMinor; ///< (54) IGD TV Minor Format CMOS option
+ UINT8 IgdPanelScaling; ///< (55) IGD Panel Scaling
+ UINT8 IgdBlcConfig; ///< (56) IGD BLC Configuration
+ UINT8 IgdBiaConfig; ///< (57) IGD BIA Configuration
+ UINT8 IgdSscConfig; ///< (58) IGD SSC Configuration
+ UINT8 Igd409; ///< (59) IGD 0409 Modified Settings Flag
+ UINT8 Igd509; ///< (60) IGD 0509 Modified Settings Flag
+ UINT8 Igd609; ///< (61) IGD 0609 Modified Settings Flag
+ UINT8 Igd709; ///< (62) IGD 0709 Modified Settings Flag
+ UINT8 IgdDvmtMemSize; ///< (63) IGD DVMT Memory Size
+ UINT8 IgdFunc1Enable; ///< (64) IGD Function 1 Enable
+ UINT8 IgdSciSmiMode; ///< (65) GMCH SMI/SCI mode (0=SCI)
+ UINT8 IgdPAVP; ///< (66) IGD PAVP data
+ UINT8 PcieOSCControl; ///< (67) PCIE OSC Control
+ UINT8 NativePCIESupport; ///< (68) Native PCIE Setup Value
+ UINT8 DisplaySupport; ///< (69) _DOS Display Support Flag.
+ UINT8 GlobalIoapicInterruptMode; ///< (70) Global IOAPIC/8259 Interrupt Mode Flag.
+ UINT8 GlobalCoolingType; ///< (71) Global Cooling Type Flag.
+ UINT8 GlobalL01Counter; ///< (72) Global L01 Counter.
+ UINT32 DeviceId6; ///< (73) Device ID 6
+ UINT32 DeviceId7; ///< (77) Device ID 7
+ UINT32 DeviceId8; ///< (81) Device ID 8
+ UINT32 DeviceId9; ///< (85) Device ID 9
+ UINT32 DeviceId10; ///< (89) Device ID 10
+ UINT32 DeviceId11; ///< (93) Device ID 11
+ UINT32 DeviceId12; ///< (97) Device ID 12
+ UINT32 DeviceId13; ///< (101) Device ID 13
+ UINT32 DeviceId14; ///< (105) Device ID 14
+ UINT32 DeviceId15; ///< (109) Device ID 15
+ UINT32 HdaNhltAcpiAddr; ///< (113) HD-Audio NHLT ACPI address
+ UINT32 HdaNhltAcpiLength; ///< (117) HD-Audio NHLT ACPI length
+ UINT32 HdaDspFeatureMask; ///< (121) HD-Audio DSP Feature Mask
+ UINT8 PlatformFlavor; ///< (125) Platform Flavor
+ UINT8 BoardRev; ///< (126) Board Rev
+ UINT8 XhciMode; ///< (127) xHCI controller mode
+ UINT8 PmicEnable; ///< (128) PMIC enable/disable
+ UINT8 IpuAcpiMode; ///< (129) IPU device Acpi type -- 0: Auto; 1: Acpi Igfx; 2: Acpi no Igfx
+ UINT32 UART21Addr; ///< (130) HSUART2 BAR1
+ UINT32 GPIO0Addr; ///< (134) GPIO0 BAR
+ UINT32 GPIO0Len; ///< (138) GPIO0 BAR Length
+ UINT32 GPIO1Addr; ///< (142) GPIO1 BAR
+ UINT32 GPIO1Len; ///< (146) GPIO1 BAR Length
+ UINT32 GPIO2Addr; ///< (150) GPIO2 BAR
+ UINT32 GPIO2Len; ///< (154) GPIO2 BAR Length
+ UINT32 GPIO3Addr; ///< (158) GPIO3 BAR
+ UINT32 GPIO3Len; ///< (162) GPIO3 BAR Length
+ UINT32 GPIO4Addr; ///< (166) GPIO4 BAR
+ UINT32 GPIO4Len; ///< (170) GPIO4 BAR Length
+ UINT32 eMMCAddr; ///< (174) eMMC BAR0
+ UINT32 eMMCLen; ///< (178) eMMC BAR0 Length
+ UINT32 eMMC1Addr; ///< (182) eMMC BAR1
+ UINT32 eMMC1Len; ///< (186) eMMC BAR1 Length
+ UINT8 DptfEnable; ///< (190) DPTF Enable
+ UINT8 EnableSen0Participant; ///< (191) EnableSen0Participant
+ UINT8 PassiveThermalTripPointSen0; ///< (192) PassiveThermalTripPointSen0
+ UINT8 CriticalThermalTripPointSen0S3; ///< (193) CriticalThermalTripPointSen0S3
+ UINT8 HotThermalTripPointSen0; ///< (194) HotThermalTripPointSen0
+ UINT8 CriticalThermalTripPointSen0; ///< (195) CriticalThermalTripPointSen0
+ UINT8 DptfChargerDevice; ///< (196) DptfChargerDevice
+ UINT8 DptfDisplayDevice; ///< (197) DptfDisplayDevice
+ UINT8 DptfFanDevice; ///< (198) DptfFanDevice
+ UINT8 DptfProcessor; ///< (199) DptfProcessor
+ UINT32 DptfProcCriticalTemperature; ///< (200) DPTF Processor participant critical temperature
+ UINT32 DptfProcPassiveTemperature; ///< (204) DPTF Processor participant passive temperature
+ UINT32 DptfGenericCriticalTemperature0; ///< (208) DPTF Generic sensor0 participant critical temperature
+ UINT32 DptfGenericPassiveTemperature0; ///< (212) DPTF Generic sensor0 participant passive temperature
+ UINT32 DptfGenericCriticalTemperature1; ///< (216) DPTF Generic sensor1 participant critical temperature
+ UINT32 DptfGenericPassiveTemperature1; ///< (220) DPTF Generic sensor1 participant passive temperature
+ UINT32 DptfGenericCriticalTemperature2; ///< (224) Reserved
+ UINT32 DptfGenericPassiveTemperature2; ///< (228) Reserved
+ UINT32 DptfGenericCriticalTemperature3; ///< (232) DPTF Generic sensor3 participant critical temperature
+ UINT32 DptfGenericPassiveTemperature3; ///< (236) DPTF Generic sensor3 participant passive temperature
+ UINT32 DptfGenericCriticalTemperature4; ///< (240) DPTF Generic sensor3 participant critical temperature
+ UINT32 DptfGenericPassiveTemperature4; ///< (244) DPTF Generic sensor3 participant passive temperature
+ UINT8 CLpmSetting; ///< (248) DPTF Current low power mode setting
+ UINT32 DptfCriticalThreshold0; ///< (249) DPTF Critical threshold0 for SCU
+ UINT32 DptfCriticalThreshold1; ///< (253) DPTF Critical threshold1 for SCU
+ UINT32 DptfCriticalThreshold2; ///< (257) DPTF Critical threshold2 for SCU
+ UINT32 DptfCriticalThreshold3; ///< (261) DPTF Critical threshold3 for SCU
+ UINT32 DptfCriticalThreshold4; ///< (265) DPTF Critical threshold4 for SCU
+ UINT8 Reserved6; ///< (269) Reserved
+ UINT32 LPOEnable; ///< (270) DPTF LPO Enable
+ UINT32 LPOStartPState; ///< (274) P-State start index
+ UINT32 LPOStepSize; ///< (278) Step size
+ UINT32 LPOPowerControlSetting; ///< (282) Power control setting
+ UINT32 LPOPerformanceControlSetting; ///< (286) Performance control setting
+ UINT8 DppmEnabled; ///< (290) DPTF DPPM enable/disable (Deprecated)
+ UINT8 BatteryChargingSolution; ///< (291) Battery charging solution 0-CLV 1-ULPMC
+ UINT32 TPMAddress; ///< (292) TPM Base Address
+ UINT32 TPMLength; ///< (296) TPM Length
+ UINT8 PssDeveice; ///< (300) PSS Device: 0 - None, 1 - Monzax 2K, 2 - Monzax 8K
+ UINT8 ModemSel; ///< (301) Modem selection: 0: Disabled, 1: 7260; 2: 7360;
+ UINT8 GpsModeSel; ///< (302) GNSS/GPS mode selection, 0: LPSS mode, 1: ISH mode
+ UINT32 HdaDspModMask; ///< (303) Hd-Audio DSP Post-Processing Module Mask
+ UINT8 Reservedo; ///< (307) OS Selection.
+ UINT8 WifiSel; ///< (308) Wi-Fi Device Select 0: SDIO Lightning Peak 1: SDIO Broadcom 2. PCIe Lightning Peak
+ UINT32 IPCBar0Address; ///< (309) IPC Bar0 base address
+ UINT32 IPCBar0Length; ///< (313) IPC Bar0 Length
+ UINT32 SSRAMBar0Address; ///< (317) IPC Bar0 base address
+ UINT32 SSRAMBar0Length; ///< (321) IPC Bar0 Length
+ UINT32 IPCBIOSMailBoxData; ///< (325) IPC BIOS mail box data
+ UINT32 IPCBIOSMailBoxInterface; ///< (329) IPC BIOS mail box interface
+ UINT32 P2SBBaseAddress; ///< (333) P2SB Base Address
+ UINT8 EDPV; ///< (337) Check for eDP display device
+ UINT32 DIDX; ///< (338) Device ID for eDP device
+ UINT8 PrmrrStatus; ///< (342) SGX Feature Status
+ UINT64 PrmrrBaseAddress; ///< (343) SGX Feature PRMRR Base address
+ UINT64 PrmrrSize; ///< (351) SGX Feature PRMRR Length (854-861)
+ UINT8 WorldCameraSel; ///< (359) 0 - Disable, 1 - IMX214, 2 - IMX135
+ UINT8 UserCameraSel; ///< (360) 0 - Disable, 1 - OV2740
+ UINT8 AudioSel; ///< (361) 0 - Disable, 1 - WM8281, 2 - WM8998
+ UINT32 LDMA11Addr; ///< (362) DMA1 BAR1
+ UINT32 LDMA11Len; ///< (366) DMA1 BAR1 Length
+ UINT8 CSDebugLightEC; ///< (370) EC Debug Light (CAPS LOCK) for when in Low Power S0 Idle State
+ UINT8 ECLowPowerMode; ///< (371) EC Low Power Mode: 1 - Enabled, 0 - Disabled
+ UINT8 CSNotifyEC; ///< (372) EC Notification of Low Power S0 Idle State
+ UINT8 EnableModernStandby; ///< (373) Enable / Disable Modern Standby Mode
+ UINT32 I2C21Addr; ///< (374) I2C2 BAR1
+ UINT32 I2C21Len; ///< (378) I2C2 BAR1 Length
+ UINT32 I2C31Addr; ///< (382) I2C3 BAR1
+ UINT32 I2C31Len; ///< (386) I2C3 BAR1 Length
+ UINT32 I2C41Addr; ///< (390) I2C4 BAR1
+ UINT32 I2C41Len; ///< (394) I2C4 BAR1 Length
+ UINT32 I2C51Addr; ///< (398) I2C5 BAR1
+ UINT32 I2C51Len; ///< (402) I2C5 BAR1 Length
+ UINT32 I2C61Addr; ///< (406) I2C6 BAR1
+ UINT32 I2C61Len; ///< (410) I2C6 BAR1 Length
+ UINT32 I2C71Addr; ///< (414) I2C7 BAR1
+ UINT32 I2C71Len; ///< (418) I2C7 BAR1 Length
+ UINT32 UsbOtgAddr; ///< (422) USB OTG BAR0
+ UINT32 UsbOtgAddr1; ///< (426) USB OTG BAR1
+ UINT32 PWM1Addr; ///< (430) PWM1 BAR0
+ UINT32 PWM1Len; ///< (434) PWM1 BAR0 Length
+ UINT32 PWM11Addr; ///< (438) PWM1 BAR1
+ UINT32 PWM11Len; ///< (442) PWM1 BAR1 Length
+ UINT32 PWM21Addr; ///< (446) PWM2 BAR1
+ UINT32 PWM21Len; ///< (450) PWM2 BAR1 Length >> Not used in BXT
+ UINT32 Port80DebugValue; ///< (454) Port 80 Debug Port Value
+ UINT8 Rtd3P0dl; ///< (458) User selectable Delay for Device D0 transition.
+ UINT16 LowPowerS0IdleConstraint; ///< (459) PEP Constraints
+
+/**
+ Bit[1:0] - SATA (0:None, 1:SATA Ports[all], 2:SATA Controller)
+ [2] - En/Dis UART 0
+ [3] - UART 1
+ [4] - SDIO
+ [5] - I2C 0
+ [6] - I2C 1
+ [7] - XHCI
+ [8] - HD Audio (includes ADSP)
+ [9] - Gfx
+ [10] - EMMC
+ [11] - SDXC
+ [12] - CPU
+**/
+ UINT8 PepList; ///< (461) RTD3 PEP support list
+ //
+ //(BIT0 - GFx , BIT1 - Sata, BIT2 - UART, BIT3 - SDHC, Bit4 - I2C0, BIT5 - I2C1, Bit6 - XHCI, Bit7 - Audio)
+ //
+ UINT8 PL1LimitCS; ///< (462) set PL1 limit when entering CS
+ UINT16 PL1LimitCSValue; ///< (463) PL1 limit value
+ UINT8 PstateCapping; ///< (465) P-state Capping
+ UINT8 PassiveThermalTripPoint; ///< (466) Passive Trip Point
+ UINT16 RTD3Config0; ///< (467) RTD3 Config Setting(BIT0:ZPODD,BIT1:USB Camera Port4, BIT2/3:SATA Port3, Bit4/5:Sata Port1/2, Bit6:Card Reader, Bit7:WWAN, Bit8:WSB SIP FAB1 Card reader)
+ UINT8 Rtd3Support; ///< (469) Runtime D3 support.
+ UINT8 LowPowerS0Idle; ///< (470) Low Power S0 Idle Enable
+ UINT32 SPI21Addr; ///< (471) SPI2 BAR1
+ UINT32 SPI21Len; ///< (475) SPI2 BAR1 Length
+ UINT32 SPI31Addr; ///< (479) SPI3 BAR1
+ UINT32 SPI31Len; ///< (483) SPI3 BAR1 Length
+ UINT32 SDIO1Addr; ///< (487) SDCard BAR1
+ UINT32 SDIO1Len; ///< (491) SDCard BAR1 Length
+ UINT32 SDCard1Addr; ///< (495) SDIO BAR1
+ UINT32 SDCard1Len; ///< (499) SDIO BAR1 Length
+ UINT32 SPI1Addr; ///< (503) SPI BAR1
+ UINT32 SPI1Len; ///< (507) SPI BAR1 Length
+ UINT8 SataPortState; ///< (511) SATA port state
+ //
+ //Bit0 - Port0, Bit1 - Port1, Bit2 - Port2, Bit3 - Port3
+ //
+ UINT32 UART11Addr; ///< (512) HSUART BAR1
+ UINT32 UART11Len; ///< (516) HSUART BAR1 Length
+ UINT32 UART21Len; ///< (520) HSUART2 BAR1 Length
+ UINT8 WPCN381U; ///< (524) WPCN381U: only used by BXT-P
+ UINT8 ECAvailability; ///< (525) Embedded Controller Availability Flag.
+ UINT8 PowerButtonSupport; ///< (526) 10sec Power button support
+/**
+ Bit0: 10 sec P-button Enable/Disable
+ Bit1: Internal Flag
+ Bit2: Rotation Lock flag, 0:unlock, 1:lock
+ Bit3: Slate/Laptop Mode Flag, 0: Slate, 1: Laptop
+ Bit4: Undock / Dock Flag, 0: Undock, 1: Dock
+ Bit5: VBDL Flag. 0: VBDL is not called, 1: VBDL is called, Virtual Button Driver is loaded.
+ Bit6: Reserved for future use.
+ Bit7: EC 10sec PB Override state for S3/S4 wake up.
+
+**/
+ UINT8 DebugState; ///< (527) Debug State
+ UINT32 IpuAddr; ///< (528) IPU Base Address
+ UINT8 NumberOfBatteries; ///< (532) Number of batteries
+ UINT8 BatteryCapacity0; ///< (533) Battery 0 Stored Capacity
+ UINT8 PciDelayOptimizationEcr; ///< (534) PciDelayOptimizationEcr
+ UINT8 IgdHpllVco; ///< (535) HPLL VCO
+ UINT32 UsbTypeCOpBaseAddr; ///< (536) USB Type C OpRegion base address
+ UINT8 SelectBtDevice; ///< (540) Blue Tooth Device Selection
+ UINT32 DptfProcActiveTemperature; ///< (541) DptfProcActiveTemperature
+ UINT8 EnableMemoryDevice; ///< (545) EnableMemoryDevice
+ UINT8 ActiveThermalTripPointTMEM; ///< (546) ActiveThermalTripPointTMEM
+ UINT8 PassiveThermalTripPointTMEM; ///< (547) PassiveThermalTripPointTMEM
+ UINT8 CriticalThermalTripPointTMEM; ///< (548) CriticalThermalTripPointTMEM
+ UINT8 ThermalSamplingPeriodTMEM; ///< (549) ThermalSamplingPeriodTMEM
+ UINT8 EnableSen1Participant; ///< (550) EnableSen1Participant
+ UINT8 ActiveThermalTripPointSen1; ///< (551) ActiveThermalTripPointSen1
+ UINT8 PassiveThermalTripPointSen1; ///< (552) PassiveThermalTripPointSen1
+ UINT8 CriticalThermalTripPointSen1; ///< (553) CriticalThermalTripPointSen1
+ UINT8 SensorSamplingPeriodSen1; ///< (554) SensorSamplingPeriodSen1
+ UINT8 EnableActivePolicy; ///< (555) EnableActivePolicy
+ UINT8 EnablePassivePolicy; ///< (556) EnablePassivePolicy
+ UINT8 EnableCriticalPolicy; ///< (557) EnableCriticalPolicy
+ UINT8 EnableAPPolicy; ///< (558) EnableAPPolicy
+ UINT8 PassiveTc1Value; ///< (559) Passive Trip Point TC1 Value
+ UINT8 PassiveTc2Value; ///< (560) Passive Trip Point TC2 Value
+ UINT8 PassiveTspValue; ///< (561) Passive Trip Point TSP Value
+ UINT8 EnableDigitalThermalSensor; ///< (562) Digital Thermal Sensor Enable
+ UINT8 Reserved0; ///< (563) Reserved
+ UINT8 IgdState; ///< (564) IGD State
+ UINT8 HighPerfMode; ///< (565) Enable/Disable HighPerformance mode for Dptf
+ UINT8 DptfWwanDevice; ///< (566) DPTF WWAN
+ UINT8 EnableSen3Participant; ///< (567) EnableSen3Participant
+ UINT8 PassiveThermalTripPointSen3; ///< (568) PassiveThermalTripPointSen3
+ UINT8 CriticalThermalTripPointSen3S3; ///< (569) CriticalThermalTripPointSen3S3
+ UINT8 HotThermalTripPointSen3; ///< (570) HotThermalTripPointSen3
+ UINT8 CriticalThermalTripPointSen3; ///< (571) CriticalThermalTripPointSen3
+ UINT8 Reserved1; ///< Reserved
+ UINT8 PanelSel; ///< (573) Panel AOB 0 - Disable, 1 - TIANMA , 2 - TRULY Fab B TypeC, 3 - TRULY Fab B, 4 -TRULY Fab B Command Mode, 5 - TRULY Fab B Command Mode TypeC
+ UINT8 IrmtCfg; ///< (574) IRMT Configuration
+ UINT8 ThermalSamplingPeriodTCPU; ///< (575) ThermalSamplingPeriodTCPU
+ UINT8 BxtStepping; ///< (576) BXT Stepping
+ UINT8 Reserved2; ///< (577) Reserved
+ UINT8 LtrEnable[6]; ///< (578) Latency Tolerance Reporting Enable
+ ///< (579) Latency Tolerance Reporting Enable
+ ///< (580) Latency Tolerance Reporting Enable
+ ///< (581) Latency Tolerance Reporting Enable
+ ///< (582) Latency Tolerance Reporting Enable
+ ///< (583) Latency Tolerance Reporting Enable
+ UINT8 ObffEnable[6]; ///< (584) Optimized Buffer Flush and Fill
+ ///< (585) Optimized Buffer Flush and Fill
+ ///< (586) Optimized Buffer Flush and Fill
+ ///< (587) Optimized Buffer Flush and Fill
+ ///< (588) Optimized Buffer Flush and Fill
+ ///< (589) Optimized Buffer Flush and Fill
+ UINT32 RpAddress[6]; ///< (590) Root Port address 1
+ ///< (594) Root Port address 2
+ ///< (598) Root Port address 3
+ ///< (602) Root Port address 4
+ ///< (606) Root Port address 5
+ ///< (610) Root Port address 6
+ UINT16 PcieLtrMaxSnoopLatency[6]; ///< (614) PCIE LTR max snoop Latency 1
+ ///< (616) PCIE LTR max snoop Latency 2
+ ///< (618) PCIE LTR max snoop Latency 3
+ ///< (620) PCIE LTR max snoop Latency 4
+ ///< (622) PCIE LTR max snoop Latency 5
+ ///< (624) PCIE LTR max snoop Latency 6
+ UINT16 PcieLtrMaxNoSnoopLatency[6]; ///< (626) PCIE LTR max no snoop Latency 1
+ ///< (628) PCIE LTR max no snoop Latency 2
+ ///< (630) PCIE LTR max no snoop Latency 3
+ ///< (632) PCIE LTR max no snoop Latency 4
+ ///< (634) PCIE LTR max no snoop Latency 5
+ ///< (636) PCIE LTR max no snoop Latency 6
+ UINT8 TrtRevision; ///< (638) TrtRevision
+ UINT32 Reserved3; ///<
+ UINT8 EnablePowerParticipant; ///< (643) EnablePowerParticipant
+ UINT8 EnablePowerBossPolicy; ///< (644) EnablePowerBossPolicy
+ //
+ // Hybrid Graphics Support
+ //
+ UINT8 HgEnabled; ///< (645) HG Enabled (0=Disabled, 1=Enabled)
+ UINT32 XPcieCfgBaseAddress; ///< (646) Any Device's PCIe Config Space Base Address
+ UINT16 DelayAfterPwrEn; ///< (650) Delay after Power Enable
+ UINT16 DelayAfterHoldReset; ///< (652) Delay after Hold Reset
+ UINT32 HgHoldRstCommOffset; ///< (654) dGPU HLD RST GPIO Community Offset
+ UINT16 HgHoldRstPinOffset; ///< (658) dGPU HLD RST GPIO Pin Offset
+ UINT8 HgHoldRstActiveInfo; ///< (660) dGPU HLD RST GPIO Active Information
+ UINT32 HgPwrEnableCommOffset; ///< (661) dGPU PWR Enable GPIO Community Offset
+ UINT16 HgPwrEnablePinOffset; ///< (665) dGPU PWR Enable GPIO Pin Offset
+ UINT8 HgPwrEnableActiveInfo; ///< (667) dGPU PWR Enable GPIO Active Information
+ UINT8 PcieEpSecBusNum; ///< (668) dGPU Root Port Base Address
+ UINT8 PcieEpCapOffset; ///< (669) dGPU Base Address
+ UINT32 RootPortBaseAddress; ///< (670) dGPU Root Port Base Address
+ UINT32 NvIgOpRegionAddress; ///< (674) NVIG support
+ UINT32 NvHmOpRegionAddress; ///< (678) NVHM support
+ UINT32 ApXmOpRegionAddress; ///< (682) AMDA support
+ UINT8 EnableGen1Participant; ///< (686) EnableGen1Participant
+ UINT8 EnableGen2Participant; ///< (687) EnableGen2Participant
+ UINT8 EnableGen3Participant; ///< (688) EnableGen3Participant
+ UINT8 EnableGen4Participant; ///< (689) EnableGen4Participant
+ UINT8 ActiveThermalTripPointGen1; ///< (690) ActiveThermalTripPointGen1
+ UINT8 PassiveThermalTripPointGen1; ///< (691) PassiveThermalTripPointGen1
+ UINT8 CriticalThermalTripPointGen1; ///< (692) CriticalThermalTripPointGen1
+ UINT8 HotThermalTripPointGen1; ///< (693) HotThermalTripPointGen1
+ UINT8 CriticalThermalTripPointGen1S3; ///< (694) CriticalThermalTripPointGen1S3
+ UINT8 ThermistorSamplingPeriodGen1; ///< (695) ThermistorSamplingPeriodGen1
+ UINT8 ActiveThermalTripPointGen2; ///< (696) ActiveThermalTripPointGen2
+ UINT8 PassiveThermalTripPointGen2; ///< (697) PassiveThermalTripPointGen2
+ UINT8 CriticalThermalTripPointGen2; ///< (698) CriticalThermalTripPointGen2
+ UINT8 HotThermalTripPointGen2; ///< (699) HotThermalTripPointGen2
+ UINT8 CriticalThermalTripPointGen2S3; ///< (700) CriticalThermalTripPointGen2S3
+ UINT8 ThermistorSamplingPeriodGen2; ///< (701) ThermistorSamplingPeriodGen2
+ UINT8 ActiveThermalTripPointGen3; ///< (702) ActiveThermalTripPointGen3
+ UINT8 PassiveThermalTripPointGen3; ///< (703) PassiveThermalTripPointGen3
+ UINT8 CriticalThermalTripPointGen3; ///< (704) CriticalThermalTripPointGen3
+ UINT8 HotThermalTripPointGen3; ///< (705) HotThermalTripPointGen3
+ UINT8 CriticalThermalTripPointGen3S3; ///< (706) CriticalThermalTripPointGen3S3
+ UINT8 ThermistorSamplingPeriodGen3; ///< (707) ThermistorSamplingPeriodGen3
+ UINT8 ActiveThermalTripPointGen4; ///< (708) ActiveThermalTripPointGen4
+ UINT8 PassiveThermalTripPointGen4; ///< (709) PassiveThermalTripPointGen4
+ UINT8 CriticalThermalTripPointGen4; ///< (710) CriticalThermalTripPointGen4
+ UINT8 HotThermalTripPointGen4; ///< (711) HotThermalTripPointGen4
+ UINT8 CriticalThermalTripPointGen4S3; ///< (712) CriticalThermalTripPointGen4S3
+ UINT8 ThermistorSamplingPeriodGen4; ///< (713) ThermistorSamplingPeriodGen4
+ UINT32 DptfProcCriticalTemperatureS3; ///< (714) DptfProcCriticalTemperatureS3
+ UINT32 DptfProcHotThermalTripPoint; ///< (718) DptfProcHotThermalTripPoint
+ UINT8 CriticalThermalTripPointSen1S3; ///< (722) CriticalThermalTripPointSen1S3
+ UINT8 HotThermalTripPointSen1; ///< (723) HotThermalTripPointSen1
+ UINT8 PmicStepping; ///< (724) PMIC Stepping
+ UINT8 ScHdAudioIoBufferOwnership; ///< (725) ScHdAudioIoBufferOwnership
+ UINT8 XdciEnable; ///< (726) Xdci Enable
+ UINT8 Reserved4; ///< (727) Reserved
+ UINT8 Reserved5; ///< (728) Reserved
+ UINT8 VirtualKeyboard; ///< (729) Virtual keyboard Function 0- Disable 1- Discrete Touch 2- Integrated Touch
+ UINT8 WiGigEnable; ///< (730) WiGig Enable for BXTM B0
+ UINT16 WiGigSPLCPwrLimit; ///< (731) WiGig SPLC Power Limit
+ UINT32 WiGigSPLCTimeWindow; ///< (733) WiGig SPLC Time Window
+ UINT8 PsmEnable; ///< (737) WiGig Power sharing manager enabling
+ UINT8 PsmSPLC0DomainType; ///< (738) WiGig PSM SPLC0 Domain Type
+ UINT16 PsmSPLC0PwrLimit; ///< (739) WiGig PSM SPLC0 Power Limit
+ UINT32 PsmSPLC0TimeWindow; ///< (741) WiGig PSM SPLC0 Time Window
+ UINT8 PsmSPLC1DomainType; ///< (745) WiGig PSM SPLC1 Domain Type
+ UINT16 PsmSPLC1PwrLimit; ///< (746) WiGig PSM SPLC1 Power Limit
+ UINT32 PsmSPLC1TimeWindow; ///< (748) WiGig PSM SPLC1 Time Window
+ UINT8 PsmDPLC0DomainType; ///< (752) WiGig PSM DPLC0 Domain Type
+ UINT8 PsmDPLC0DomainPerference; ///< (753) WiGig PSM DPLC0 Domain Preference
+ UINT8 PsmDPLC0PowerLimitIndex; ///< (754) WiGig PSM DPLC0 Power Limit Index
+ UINT16 PsmDPLC0PwrLimit; ///< (755) WiGig PSM DPLC0 Power Limit
+ UINT32 PsmDPLC0TimeWindow; ///< (757) WiGig PSM DPLC0 Time Window
+ UINT8 PsmDPLC1DomainType; ///< (761) WiGig PSM DPLC1 Domain Type
+ UINT8 PsmDPLC1DomainPerference; ///< (762) WiGig PSM DPLC1 Domain Preference
+ UINT8 PsmDPLC1PowerLimitIndex; ///< (763) WiGig PSM DPLC1 Power Limit Index
+ UINT16 PsmDPLC1PwrLimit; ///< (764) WiGig PSM DPLC1 Power Limit
+ UINT32 PsmDPLC1TimeWindow; ///< (766) WiGig PSM DPLC1 Time Window
+ UINT8 I2s343A; ///< (770) I2S audio codec device - INT343A
+ UINT8 I2s34C1; ///< (771) I2S audio codec device - INT34C1
+ UINT8 I2cNfc; ///< (772) I2C NFC device - NXP1001
+ UINT8 I2cPss; ///< (773) I2S PSS device - IMPJ0003
+ UINT8 UartBt; ///< (774) UART BT device - BCM2E40
+ UINT8 UartGps; ///< (775) UART GPS device - BCM4752
+ UINT64 HdaDspPpModCustomGuid1Low; ///< (776)
+ UINT64 HdaDspPpModCustomGuid1High; ///< (784)
+ UINT64 HdaDspPpModCustomGuid2Low; ///< (792)
+ UINT64 HdaDspPpModCustomGuid2High; ///< (800)
+ UINT64 HdaDspPpModCustomGuid3Low; ///< (808)
+ UINT64 HdaDspPpModCustomGuid3High; ///< (816)
+ UINT16 PowerParticipantPollingRate; ///< (824) DPTF PowerParticipantPollingRate
+ UINT16 EnableDCFG; ///< (826) DPTF Enable DPTF Configuration
+ UINT8 OemDesignVariable0; ///< (828) DPTF Oem Design Variable
+ UINT8 OemDesignVariable1; ///< (829) DPTF Oem Design Variable
+ UINT8 OemDesignVariable2; ///< (830) DPTF Oem Design Variable
+ UINT8 OemDesignVariable3; ///< (831) DPTF Oem Design Variable
+ UINT8 OemDesignVariable4; ///< (832) DPTF Oem Design Variable
+ UINT8 OemDesignVariable5; ///< (833) DPTF Oem Design Variable
+ UINT8 EnableVS1Participant; ///< (834) EnableVS1Participant
+ UINT8 ActiveThermalTripPointVS1; ///< (835) ActiveThermalTripPointVS1
+ UINT8 PassiveThermalTripPointVS1; //< (836) PassiveThermalTripPointVS1
+ UINT8 CriticalThermalTripPointVS1; ///< (837) CriticalThermalTripPointVS1
+ UINT8 CriticalThermalTripPointVS1S3; ///< (838) CriticalThermalTripPointVS1S3
+ UINT8 HotThermalTripPointVS1; ///< (839) HotThermalTripPointVS1
+ UINT8 EnableVS2Participant; ///< (840) EnableVS2Participant
+ UINT8 ActiveThermalTripPointVS2; ///< (841) ActiveThermalTripPointVS2
+ UINT8 PassiveThermalTripPointVS2; //< (842) PassiveThermalTripPointVS2
+ UINT8 CriticalThermalTripPointVS2; ///< (843) CriticalThermalTripPointVS2
+ UINT8 CriticalThermalTripPointVS2S3; ///< (844) CriticalThermalTripPointVS2S3
+ UINT8 HotThermalTripPointVS2; ///< (845) HotThermalTripPointVS2
+ UINT8 EnableVS3Participant; ///< (846) EnableVS3Participant
+ UINT8 ActiveThermalTripPointVS3; ///< (847) ActiveThermalTripPointVS3
+ UINT8 PassiveThermalTripPointVS3; ///< (848) PassiveThermalTripPointVS3
+ UINT8 CriticalThermalTripPointVS3; ///< (849) CriticalThermalTripPointVS3
+ UINT8 CriticalThermalTripPointVS3S3; ///< (850) CriticalThermalTripPointVS3S3
+ UINT8 HotThermalTripPointVS3; ///< (851) HotThermalTripPointVS3
+ UINT8 EnableVSPolicy; ///< (852) EnableVsPolicy
+ UINT8 Spi1SensorDevice; ///< (853) SPI1 Fingerprint device - FPC1020/FPC1021
+ UINT8 NfcSelect; ///< (854) NFC device select: 0: disabled; 1: NFC (IPT)/secure NFC; 2: NFC;
+ UINT16 RfemSPLCPwrLimit; ///< (855) RFEM SPLC Power Limit
+ UINT32 RfemSPLCTimeWindow; ///< (857) RFEM SPLC Time Window
+ UINT8 PanelSelect; ///< (861) Panel Selection (0=eDP, >=1 for MIPI)
+ UINT8 EPIEnable; ///< (862) EPIEnable
+ UINT8 TypeCEnable; ///< (863) TypeCEnable
+ UINT8 PassiveThermalTripPointWWAN; ///< (864) PassiveThermalTripPointWWAN
+ UINT8 CriticalThermalTripPointWWANS3; ///< (865) CriticalThermalTripPointWWANS3
+ UINT8 HotThermalTripPointWWAN; ///< (866) HotThermalTripPointWWAN
+ UINT8 CriticalThermalTripPointWWAN; ///< (867) CriticalThermalTripPointWWAN
+ UINT8 DisplayHighLimit; ///< (868) DisplayHighLimit
+ UINT8 DisplayLowLimit; ///< (869) DisplayLowLimit
+ UINT8 OsDbgEnable; ///< (871) OsDbgEnable
+ UINT32 Mmio32Base; ///< (874) PCIE MMIO resource base
+ UINT32 Mmio32Length; ///< (878) PCIE MMIO resource length
+ UINT8 CameraRotationAngle; ///< (883) Camera Sensor Rotation Angle
+ UINT8 I2cTouchPanel; ///< (884) I2c Touch Panel
+ UINT8 I2cTouchPad; ///< (885) I2c Touch pad
+ UINT32 I2C0Speed; ///< (886) I2C0 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode
+ UINT32 I2C1Speed; ///< (890) I2C1 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode
+ UINT32 I2C2Speed; ///< (894) I2C2 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode
+ UINT32 I2C3Speed; ///< (898) I2C3 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode
+ UINT32 I2C4Speed; ///< (902) I2C4 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode
+ UINT32 I2C5Speed; ///< (906) I2C5 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode
+ UINT32 I2C6Speed; ///< (910) I2C6 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode
+ UINT32 I2C7Speed; ///< (914) I2C7 Speed - Standard mode/Fast mode/FastPlus mode/HighSpeed mode
+ UINT8 EnableSen2Participant; ///< (918) EnableSen2Participant
+ UINT8 PassiveThermalTripPointSen2; ///< (919) PassiveThermalTripPointSen2
+ UINT8 CriticalThermalTripPointSen2S3; ///< (920) CriticalThermalTripPointSen2S3
+ UINT8 HotThermalTripPointSen2; ///< (921) HotThermalTripPointSen2
+ UINT8 CriticalThermalTripPointSen2; ///< (922) CriticalThermalTripPointSen2
+} EFI_GLOBAL_NVS_AREA;
+#pragma pack ()
+
+//
+// Global NVS Area Protocol
+//
+typedef struct _EFI_GLOBAL_NVS_AREA_PROTOCOL {
+ EFI_GLOBAL_NVS_AREA *Area;
+} EFI_GLOBAL_NVS_AREA_PROTOCOL;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/IgdOpRegion.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/IgdOpRegion.h new file mode 100644 index 0000000000..64d77d6d44 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/IgdOpRegion.h @@ -0,0 +1,215 @@ +/** @file
+ This file is part of the IGD OpRegion Implementation. The IGD OpRegion is
+ an interface between system BIOS, ASL code, and Graphics drivers.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _IGD_OPREGION_PROTOCOL_H_
+#define _IGD_OPREGION_PROTOCOL_H_
+
+//
+// OpRegion / Software SCI protocol GUID
+//
+#define IGD_OPREGION_PROTOCOL_GUID \
+ { \
+ 0xcdc5dddf, 0xe79d, 0x41ec, 0xa9, 0xb0, 0x65, 0x65, 0x49, 0xd, 0xb9, 0xd3 \
+ }
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gIgdOpRegionProtocolGuid;
+
+//
+// Forward reference for pure ANSI compatability
+//
+typedef struct _IGD_OPREGION_PROTOCOL IGD_OPREGION_PROTOCOL;
+
+//
+// Protocol data definitions
+//
+
+//
+// OpRegion structures:
+// Sub-structures define the different parts of the OpRegion followed by the
+// main structure representing the entire OpRegion.
+//
+// Note: These structures are packed to 1 byte offsets because the exact
+// data location is requred by the supporting design specification due to
+// the fact that the data is used by ASL and Graphics driver code compiled
+// separatly.
+//
+#pragma pack(1)
+//
+// OpRegion header (mailbox 0) structure and defines.
+//
+typedef struct {
+ CHAR8 SIGN[0x10]; ///< Offset 0 OpRegion signature
+ UINT32 SIZE; ///< Offset 16 OpRegion size
+ UINT32 OVER; ///< Offset 20 OpRegion structure version
+ UINT8 SVER[0x20]; ///< Offset 24 System BIOS build version
+ UINT8 VVER[0x10]; ///< Offset 56 Video BIOS build version
+ UINT8 GVER[0x10]; ///< Offset 72 Graphic driver build version
+ UINT32 MBOX; ///< Offset 88 Mailboxes supported
+ UINT32 DMOD; ///< Offset 92 Driver Model
+ UINT32 PCON; ///< Offset 96 Platform Capabilities
+ CHAR16 DVER[0x10]; ///< Offset 100 GOP Version
+ UINT8 RHD1[0x7C]; ///< Offset 132 Reserved
+} OPREGION_HEADER;
+#pragma pack()
+
+#pragma pack(1)
+typedef struct {
+ UINT32 DRDY; ///< Offset 0 Driver readiness
+ UINT32 CSTS; ///< Offset 4 Status
+ UINT32 CEVT; ///< Offset 8 Current event
+ UINT8 RM11[0x14]; ///< Offset 12 Reserved
+ UINT32 DIDL; ///< Offset 32 Supported display device 1
+ UINT32 DDL2; ///< Offset 36 Supported display device 2
+ UINT32 DDL3; ///< Offset 40 Supported display device 3
+ UINT32 DDL4; ///< Offset 44 Supported display device 4
+ UINT32 DDL5; ///< Offset 48 Supported display device 5
+ UINT32 DDL6; ///< Offset 52 Supported display device 6
+ UINT32 DDL7; ///< Offset 56 Supported display device 7
+ UINT32 DDL8; ///< Offset 60 Supported display device 8
+ UINT32 CPDL; ///< Offset 64 Currently present display device 1
+ UINT32 CPL2; ///< Offset 68 Currently present display device 2
+ UINT32 CPL3; ///< Offset 72 Currently present display device 3
+ UINT32 CPL4; ///< Offset 76 Currently present display device 4
+ UINT32 CPL5; ///< Offset 80 Currently present display device 5
+ UINT32 CPL6; ///< Offset 84 Currently present display device 6
+ UINT32 CPL7; ///< Offset 88 Currently present display device 7
+ UINT32 CPL8; ///< Offset 92 Currently present display device 8
+ UINT32 CADL; ///< Offset 96 Currently active display device 1
+ UINT32 CAL2; ///< Offset 100 Currently active display device 2
+ UINT32 CAL3; ///< Offset 104 Currently active display device 3
+ UINT32 CAL4; ///< Offset 108 Currently active display device 4
+ UINT32 CAL5; ///< Offset 112 Currently active display device 5
+ UINT32 CAL6; ///< Offset 116 Currently active display device 6
+ UINT32 CAL7; ///< Offset 120 Currently active display device 7
+ UINT32 CAL8; ///< Offset 124 Currently active display device 8
+ UINT32 NADL; ///< Offset 128 Next active device 1
+ UINT32 NDL2; ///< Offset 132 Next active device 2
+ UINT32 NDL3; ///< Offset 136 Next active device 3
+ UINT32 NDL4; ///< Offset 140 Next active device 4
+ UINT32 NDL5; ///< Offset 144 Next active device 5
+ UINT32 NDL6; ///< Offset 148 Next active device 6
+ UINT32 NDL7; ///< Offset 152 Next active device 7
+ UINT32 NDL8; ///< Offset 156 Next active device 8
+ UINT32 ASLP; ///< Offset 160 ASL sleep timeout
+ UINT32 TIDX; ///< Offset 164 Toggle table index
+ UINT32 CHPD; ///< Offset 168 Current hot plug enable indicator
+ UINT32 CLID; ///< Offset 172 Current lid state indicator
+ UINT32 CDCK; ///< Offset 176 Current docking state indicator
+ UINT32 SXSW; ///< Offset 180 Display Switch notification on Sx State resume
+ UINT32 EVTS; ///< Offset 184 Events supported by ASL
+ UINT32 CNOT; ///< Offset 188 Current OS Notification
+ UINT32 NRDY; ///< Offset 192 Reasons for DRDY = 0
+ UINT32 DDL9; ///< Offset 196 Extended Supported display device 1
+ UINT32 DD10; ///< Offset 200 Extended Supported display device 2
+ UINT32 DD11; ///< Offset 204 Extended Supported display device 3
+ UINT32 DD12; ///< Offset 208 Extended Supported display device 4
+ UINT32 DD13; ///< Offset 212 Extended Supported display device 5
+ UINT32 DD14; ///< Offset 216 Extended Supported display device 6
+ UINT32 DD15; ///< Offset 220 Extended Supported display device 7
+ UINT32 CPL9; ///< Offset 224 Extended Currently present device 1
+ UINT32 CP10; ///< Offset 228 Extended Currently present device 2
+ UINT32 CP11; ///< Offset 232 Extended Currently present device 3
+ UINT32 CP12; ///< Offset 236 Extended Currently present device 4
+ UINT32 CP13; ///< Offset 240 Extended Currently present device 5
+ UINT32 CP14; ///< Offset 244 Extended Currently present device 6
+ UINT32 CP15; ///< Offset 248 Extended Currently present device 7
+ UINT8 RM12[0x4]; ///< Offset 252 Reserved 4 bytes
+} OPREGION_MBOX1;
+#pragma pack()
+
+#pragma pack(1)
+//
+// OpRegion mailbox 2 (Software SCI Interface).
+//
+typedef struct {
+ UINT32 SCIC; ///< Offset 0 Software SCI function number parameters
+ UINT32 PARM; ///< Offset 4 Software SCI additional parameters
+ UINT32 DSLP; ///< Offset 8 Driver sleep timeout
+ UINT8 RM21[0xF4]; ///< Offset 12 Reserved
+} OPREGION_MBOX2;
+#pragma pack()
+
+#pragma pack(1)
+//
+// OpRegion mailbox 3 (Power Conservation).
+//
+typedef struct {
+ UINT32 ARDY; ///< Offset 0 Driver readiness
+ UINT32 ASLC; ///< Offset 4 ASLE interrupt command / status
+ UINT32 TCHE; ///< Offset 8 Technology enabled indicator
+ UINT32 ALSI; ///< Offset 12 Current ALS illuminance reading
+ UINT32 BCLP; ///< Offset 16 Backlight britness to set
+ UINT32 PFIT; ///< Offset 20 Panel fitting Request
+ UINT32 CBLV; ///< Offset 24 Brightness Current State
+ UINT16 BCLM[0x14]; ///< Offset 28 Backlight Brightness Level Duty Cycle Mapping Table
+ UINT32 CPFM; ///< Offset 68 Panel Fitting Current Mode
+ UINT32 EPFM; ///< Offset 72 Enabled Panel Fitting Modes
+ UINT8 PLUT[0x4A]; ///< Offset 76 Panel Look Up Table
+ UINT32 PFMB; ///< Offset 150 PWM Frequency and Minimum Brightness
+ UINT32 CCDV; ///< Offset 154 Color Correction Default Values
+ UINT32 PCFT; ///< Offset 158 Power Conservation Features
+ UINT32 SROT; ///< Offset 162 Supported Rotation angle
+ UINT32 IUER; ///< Offset 166 Intel Ultrabook Event Register
+ UINT64 FDSP; ///< Offset 170 FFS Display Physical address
+ UINT32 FDSS; ///< Offset 178 FFS Display Size
+ UINT32 STAT; ///< Offset 182 State Indicator
+ UINT64 RVDA; ///< Offset 186 (Igd opregion offset 0x3BAh) Physical address of Raw VBT data
+ UINT32 RVDS; ///< Offset 194 (Igd opregion offset 0x3C2h) Size of Raw VBT data
+ UINT8 RMEM[0x3A]; ///< Offset 198 Reserved
+} OPREGION_MBOX3;
+#pragma pack()
+
+#pragma pack(1)
+//
+// OpRegion mailbox 4 (VBT).
+//
+typedef struct {
+ UINT8 GVD1[0x1800]; ///< Offset 1024 6K Reserved
+} OPREGION_VBT;
+#pragma pack ()
+
+#pragma pack (1)
+typedef struct {
+ UINT32 PHED; ///< Offset 7168 Panel Header
+ UINT8 BDDC[0x100]; ///< Offset 7172 Panel EDID
+ UINT8 RM51[0x2FC]; ///< Offset 7428 764 bytes
+} OPREGION_MBOX5;
+#pragma pack ()
+//
+// Entire OpRegion
+//
+#pragma pack (1)
+typedef struct {
+ OPREGION_HEADER Header; ///< OpRegion header
+ OPREGION_MBOX1 MBox1; ///< Mailbox 1: Public ACPI Methods
+ OPREGION_MBOX2 MBox2; ///< Mailbox 2: Software SCI Inteface
+ OPREGION_MBOX3 MBox3; ///< Mailbox 3: Power Conservation
+ OPREGION_VBT VBT; ///< VBT: Video BIOS Table (OEM customizable data)
+ OPREGION_MBOX5 MBox5; ///< Mailbox 5: BIOS to Driver Notification Extension
+} IGD_OPREGION_STRUC;
+#pragma pack()
+//
+// IGD OpRegion Protocol
+//
+struct _IGD_OPREGION_PROTOCOL {
+ IGD_OPREGION_STRUC *OpRegion; ///< IGD Operation Region Structure
+};
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/IgdPanelConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/IgdPanelConfig.h new file mode 100644 index 0000000000..2b39bb922f --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/IgdPanelConfig.h @@ -0,0 +1,41 @@ +/** @file
+ Policy definition of IGD Panel Config Block.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _IGD_PANEL_CONFIG_H_
+#define _IGD_PANEL_CONFIG_H_
+
+#pragma pack(1)
+
+#define IGD_PANEL_CONFIG_REVISION 1
+
+extern EFI_GUID gIgdPanelConfigGuid;
+
+//
+// IGD Panel Features
+//
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Block Header
+ UINT8 PFITStatus;
+ UINT8 IgdThermalSupport;
+ UINT8 ALSEnabled;
+#if (ENBDT_PF_ENABLE == 1)
+ UINT8 PanelSelect; ///< 0=eDP, >=1 for MIPI
+#endif
+} IGD_PANEL_CONFIG;
+
+#pragma pack()
+
+#endif // _IGD_PANEL_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/MemInfo.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/MemInfo.h new file mode 100644 index 0000000000..5acaadd07a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/MemInfo.h @@ -0,0 +1,84 @@ +/** @file
+ This protocol provides the memory information data, such as
+ total physical memory size, memory frequency, memory size
+ of each dimm and rank.
+
+ This protocol is EFI compatible.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _MEM_INFO_PROTOCOL_H_
+#define _MEM_INFO_PROTOCOL_H_
+
+//
+// Define the protocol GUID
+//
+#define MEM_INFO_PROTOCOL_GUID \
+ { \
+ 0x6f20f7c8, 0xe5ef, 0x4f21, 0x8d, 0x19, 0xed, 0xc5, 0xf0, 0xc4, 0x96, 0xae \
+ }
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gMemInfoProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _MEM_INFO_PROTOCOL MEM_INFO_PROTOCOL;
+
+//
+// Protocol definitions
+//
+
+#define CH_NUM 4
+#define DIMM_NUM 1
+#define RANK_NUM 2
+#define MAX_SOCKETS (CH_NUM * DIMM_NUM)
+
+/**
+ memSize Total physical memory size
+ ddrFreq DDR Frequency
+ EccSupport ECC Support
+ dimmSize Dimm Size
+ DimmExist Dimm Present or not
+ RankInDimm No. of ranks in a dimm
+
+**/
+#pragma pack(1)
+
+typedef struct {
+ UINT32 memSize;
+ UINT16 ddrFreq;
+ UINT16 ddrType;
+ BOOLEAN EccSupport;
+ UINT32 dimmSize[CH_NUM * DIMM_NUM];
+ UINT8 reserved;
+ UINT16 reserved2;
+ UINT8 DimmPresent[CH_NUM * DIMM_NUM];
+ UINT8 *DimmsSpdData[CH_NUM * DIMM_NUM];
+ UINT8 BusWidth;
+} MEMORY_INFO_DATA;
+
+#pragma pack()
+
+//
+// Memory Information Protocol
+//
+struct _MEM_INFO_PROTOCOL {
+ MEMORY_INFO_DATA MemInfoData;
+};
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/PlatformGopPolicy.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/PlatformGopPolicy.h new file mode 100644 index 0000000000..cad275683e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/PlatformGopPolicy.h @@ -0,0 +1,98 @@ +/** @file
+ Header file for Platform GOP Policy.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_GOP_POLICY_PROTOCOL_H_
+#define _PLATFORM_GOP_POLICY_PROTOCOL_H_
+
+#define EFI_PLATFORM_GOP_POLICY_PROTOCOL_GUID \
+ { 0xec2e931b, 0x3281, 0x48a5, 0x81, 0x7, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d }
+
+#define EFI_BMP_IMAGE_GUID \
+ { 0x878AC2CC, 0x5343, 0x46F2, 0xB5, 0x63, 0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA }
+
+#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_01 0x01
+#define PLATFORM_GOP_POLICY_PROTOCOL_REVISION_02 x0222
+
+#pragma pack(1)
+
+typedef enum {
+ LidClosed,
+ LidOpen,
+ LidStatusMax
+} LID_STATUS;
+
+typedef enum {
+ Docked,
+ UnDocked,
+ DockStatusMax
+} DOCK_STATUS;
+
+/**
+ Get platform LID status.
+
+ @param[out] CurrentLidStatus Current Lid status.
+
+ @retval EFI_STATUS
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+ OUT LID_STATUS *CurrentLidStatus
+);
+
+/**
+ Get VBT data.
+
+ @param[out] VbtAddress Address of VBT.
+ @param[out] VbtSize Size of VBT.
+
+ @retval EFI_STATUS
+
+**/
+typedef
+EFI_STATUS
+(EFIAPI *GET_VBT_DATA) (
+ OUT EFI_PHYSICAL_ADDRESS *VbtAddress,
+ OUT UINT32 *VbtSize
+);
+
+#pragma pack()
+
+//
+// Platform GOP policy Protocol
+//
+typedef struct _PLATFORM_GOP_POLICY_PROTOCOL {
+ UINT32 Revision;
+ GET_PLATFORM_LID_STATUS GetPlatformLidStatus;
+ GET_VBT_DATA GetVbtData;
+} PLATFORM_GOP_POLICY_PROTOCOL;
+
+//
+// VBT Information
+//
+typedef struct {
+ EFI_PHYSICAL_ADDRESS VbtAddress;
+ UINT32 VbtSize;
+} VBT_INFO;
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPlatformGOPPolicyGuid;
+extern EFI_GUID gVbtInfoGuid;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/SaDxeMiscConfig.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/SaDxeMiscConfig.h new file mode 100644 index 0000000000..e0a299438f --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/SaDxeMiscConfig.h @@ -0,0 +1,37 @@ +/** @file
+ Policy definition of SA DXE Misc Config Block.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SA_DXE_MISC_CONFIG_H_
+#define _SA_DXE_MISC_CONFIG_H_
+
+#pragma pack(1)
+
+#define SA_DXE_MISC_CONFIG_REVISION 1
+
+extern EFI_GUID gSaDxeMiscConfigGuid;
+
+//
+// SA MISC Features
+//
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Block Header
+ UINT8 S0ixSupported;
+ UINT8 AudioTypeSupport;
+} SA_DXE_MISC_CONFIG;
+
+#pragma pack()
+
+#endif // _SA_DXE_MISC_CONFIG_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/SaPolicy.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/SaPolicy.h new file mode 100644 index 0000000000..ada6bf34d6 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/Protocol/SaPolicy.h @@ -0,0 +1,56 @@ +/** @file
+ Interface definition details between System Agent and platform drivers during DXE phase.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SA_POLICY_H_
+#define _SA_POLICY_H_
+
+#include <ConfigBlock.h>
+#include <Protocol/SaDxeMiscConfig.h>
+#include <Protocol/IgdPanelConfig.h>
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gSaPolicyProtocolGuid;
+
+//
+// Protocol revision number
+// Any backwards compatible changes to this protocol will result in an update in the revision number
+// Major changes will require publication of a new protocol
+//
+#define SA_POLICY_PROTOCOL_REVISION_1 0
+
+//
+// Generic definitions for device enabling/disabling used by NC code.
+//
+#define DEVICE_ENABLE 1
+#define DEVICE_DISABLE 0
+
+#define NO_AUDIO 0
+#define HD_AUDIO 1
+#define LPE_AUDIO 2
+
+//
+// SA Policy Protocol
+//
+typedef struct _SA_POLICY_PROTOCOL {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Offset 0-31
+ //
+ // Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+ //
+} SA_POLICY_PROTOCOL;
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaAccess.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaAccess.h new file mode 100644 index 0000000000..95691b5f66 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaAccess.h @@ -0,0 +1,282 @@ +/** @file
+ Macros to simplify and abstract the interface to PCI configuration.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SAACCESS_H_
+#define _SAACCESS_H_
+
+#include "SaRegs.h"
+#include "SaCommonDefinitions.h"
+#include <Library/IoLib.h>
+#include "PlatformBaseAddresses.h"
+
+//
+// Memory Mapped IO access macros used by MSG BUS LIBRARY
+//
+#define MmioAddress( BaseAddr, Register ) \
+ ( (UINTN)BaseAddr + \
+ (UINTN)(Register) \
+ )
+
+//
+// UINT64
+//
+
+#define Mmio64Ptr( BaseAddr, Register ) \
+ ( (volatile UINT64 *)MmioAddress( BaseAddr, Register ) )
+
+#define Mmio64( BaseAddr, Register ) \
+ *Mmio64Ptr( BaseAddr, Register )
+
+#define Mmio64Or( BaseAddr, Register, OrData ) \
+ Mmio64( BaseAddr, Register ) = \
+ (UINT64) ( \
+ Mmio64( BaseAddr, Register ) | \
+ (UINT64)(OrData) \
+ )
+
+#define Mmio64And( BaseAddr, Register, AndData ) \
+ Mmio64( BaseAddr, Register ) = \
+ (UINT64) ( \
+ Mmio64( BaseAddr, Register ) & \
+ (UINT64)(AndData) \
+ )
+
+#define Mmio64AndThenOr( BaseAddr, Register, AndData, OrData ) \
+ Mmio64( BaseAddr, Register ) = \
+ (UINT64) ( \
+ ( Mmio64( BaseAddr, Register ) & \
+ (UINT64)(AndData) \
+ ) | \
+ (UINT64)(OrData) \
+ )
+
+//
+// UINT32
+//
+
+#define Mmio32Ptr( BaseAddr, Register ) \
+ ( (volatile UINT32 *)MmioAddress( BaseAddr, Register ) )
+
+#define Mmio32( BaseAddr, Register ) \
+ *Mmio32Ptr( BaseAddr, Register )
+
+#define Mmio32Or( BaseAddr, Register, OrData ) \
+ Mmio32( BaseAddr, Register ) = \
+ (UINT32) ( \
+ Mmio32( BaseAddr, Register ) | \
+ (UINT32)(OrData) \
+ )
+
+#define Mmio32And( BaseAddr, Register, AndData ) \
+ Mmio32( BaseAddr, Register ) = \
+ (UINT32) ( \
+ Mmio32( BaseAddr, Register ) & \
+ (UINT32)(AndData) \
+ )
+
+#define Mmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \
+ Mmio32( BaseAddr, Register ) = \
+ (UINT32) ( \
+ ( Mmio32( BaseAddr, Register ) & \
+ (UINT32)(AndData) \
+ ) | \
+ (UINT32)(OrData) \
+ )
+
+//
+// UINT16
+//
+
+#define Mmio16Ptr( BaseAddr, Register ) \
+ ( (volatile UINT16 *)MmioAddress( BaseAddr, Register ) )
+
+#define Mmio16( BaseAddr, Register ) \
+ *Mmio16Ptr( BaseAddr, Register )
+
+#define Mmio16Or( BaseAddr, Register, OrData ) \
+ Mmio16( BaseAddr, Register ) = \
+ (UINT16) ( \
+ Mmio16( BaseAddr, Register ) | \
+ (UINT16)(OrData) \
+ )
+
+#define Mmio16And( BaseAddr, Register, AndData ) \
+ Mmio16( BaseAddr, Register ) = \
+ (UINT16) ( \
+ Mmio16( BaseAddr, Register ) & \
+ (UINT16)(AndData) \
+ )
+
+#define Mmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \
+ Mmio16( BaseAddr, Register ) = \
+ (UINT16) ( \
+ ( Mmio16( BaseAddr, Register ) & \
+ (UINT16)(AndData) \
+ ) | \
+ (UINT16)(OrData) \
+ )
+
+//
+// UINT8
+//
+
+#define Mmio8Ptr( BaseAddr, Register ) \
+ ( (volatile UINT8 *)MmioAddress( BaseAddr, Register ) )
+
+#define Mmio8( BaseAddr, Register ) \
+ *Mmio8Ptr( BaseAddr, Register )
+
+#define Mmio8Or( BaseAddr, Register, OrData ) \
+ Mmio8( BaseAddr, Register ) = \
+ (UINT8) ( \
+ Mmio8( BaseAddr, Register ) | \
+ (UINT8)(OrData) \
+ )
+
+#define Mmio8And( BaseAddr, Register, AndData ) \
+ Mmio8( BaseAddr, Register ) = \
+ (UINT8) ( \
+ Mmio8( BaseAddr, Register ) & \
+ (UINT8)(AndData) \
+ )
+
+#define Mmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \
+ Mmio8( BaseAddr, Register ) = \
+ (UINT8) ( \
+ ( Mmio8( BaseAddr, Register ) & \
+ (UINT8)(AndData) \
+ ) | \
+ (UINT8)(OrData) \
+ )
+
+/**
+ All sideband access has moved to SideBandLib in BxtSocRefCodePkg/BroxtonSoc/Library/SideBandLib.
+
+ Any sideband read and write operations should be performed by calling SideBandRead32() and
+ SideBandWrite32() which will internally determine whether to access the sideband private
+ configuration registers via MMIO or Sideband Message Interface based on whether the P2SB
+ BAR (SBREG_BAR) is set.
+
+**/
+
+#define N_PCICFGCTRL_PCI_IRQ 20
+#define N_PCICFGCTRL_ACPI_IRQ 12
+#define N_PCICFGCTRL_INT_PIN 8
+#define V_PCICFG_CTRL_NONE 0
+#define V_PCICFG_CTRL_INTA 1
+#define V_PCICFG_CTRL_INTB 2
+#define V_PCICFG_CTRL_INTC 3
+#define V_PCICFG_CTRL_INTD 4
+
+//
+// Memory mapped PCI IO
+//
+#define PciCfgPtr(Bus, Device, Function, Register )\
+ (UINTN)(Bus << 20) + \
+ (UINTN)(Device << 15) + \
+ (UINTN)(Function << 12) + \
+ (UINTN)(Register)
+
+#define PciCfg32Read_CF8CFC(B,D,F,R) \
+ (UINT32)(IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoIn32(0xCFC))
+
+#define PciCfg32Write_CF8CFC(B,D,F,R,Data) \
+ (IoOut32(0xCF8,(0x80000000|(B<<16)|(D<<11)|(F<<8)|(R))),IoOut32(0xCFC,Data))
+
+#define PciCfg32Or_CF8CFC(B,D,F,R,O) \
+ PciCfg32Write_CF8CFC(B,D,F,R, \
+ (PciCfg32Read_CF8CFC(B,D,F,R) | (O)))
+
+#define PciCfg32And_CF8CFC(B,D,F,R,A) \
+ PciCfg32Write_CF8CFC(B,D,F,R, \
+ (PciCfg32Read_CF8CFC(B,D,F,R) & (A)))
+
+#define PciCfg32AndThenOr_CF8CFC(B,D,F,R,A,O) \
+ PciCfg32Write_CF8CFC(B,D,F,R, \
+ (PciCfg32Read_CF8CFC(B,D,F,R) & (A)) | (O))
+
+//
+// Device 0, Function 0
+//
+#define McD0PciCfg64(Register) MmPci64 (0, SA_MC_BUS, 0, 0, Register)
+#define McD0PciCfg64Or(Register, OrData) MmPci64Or (0, SA_MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg64And(Register, AndData) MmPci64And (0, SA_MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, SA_MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg32(Register) MmPci32 (0, SA_MC_BUS, 0, 0, Register)
+#define McD0PciCfg32Or(Register, OrData) MmPci32Or (0, SA_MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg32And(Register, AndData) MmPci32And (0, SA_MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, SA_MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg16(Register) MmPci16 (0, SA_MC_BUS, 0, 0, Register)
+#define McD0PciCfg16Or(Register, OrData) MmPci16Or (0, SA_MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg16And(Register, AndData) MmPci16And (0, SA_MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, SA_MC_BUS, 0, 0, Register, AndData, OrData)
+
+#define McD0PciCfg8(Register) MmPci8 (0, SA_MC_BUS, 0, 0, Register)
+#define McD0PciCfg8Or(Register, OrData) MmPci8Or (0, SA_MC_BUS, 0, 0, Register, OrData)
+#define McD0PciCfg8And(Register, AndData) MmPci8And (0, SA_MC_BUS, 0, 0, Register, AndData)
+#define McD0PciCfg8AndThenOr( Register, AndData, OrData ) MmPci8AndThenOr (0, SA_MC_BUS, 0, 0, Register, AndData, OrData)
+
+
+//
+// Device 2, Function 0
+//
+#define McD2PciCfg64(Register) MmPci64 (0, SA_MC_BUS, 2, 0, Register)
+#define McD2PciCfg64Or(Register, OrData) MmPci64Or (0, SA_MC_BUS, 2, 0, Register, OrData)
+#define McD2PciCfg64And(Register, AndData) MmPci64And (0, SA_MC_BUS, 2, 0, Register, AndData)
+#define McD2PciCfg64AndThenOr(Register, AndData, OrData) MmPci64AndThenOr (0, SA_MC_BUS, 2, 0, Register, AndData, OrData)
+
+#define McD2PciCfg32(Register) MmPci32 (0, SA_MC_BUS, 2, 0, Register)
+#define McD2PciCfg32Or(Register, OrData) MmPci32Or (0, SA_MC_BUS, 2, 0, Register, OrData)
+#define McD2PciCfg32And(Register, AndData) MmPci32And (0, SA_MC_BUS, 2, 0, Register, AndData)
+#define McD2PciCfg32AndThenOr(Register, AndData, OrData) MmPci32AndThenOr (0, SA_MC_BUS, 2, 0, Register, AndData, OrData)
+
+#define McD2PciCfg16(Register) MmPci16 (0, SA_MC_BUS, 2, 0, Register)
+#define McD2PciCfg16Or(Register, OrData) MmPci16Or (0, SA_MC_BUS, 2, 0, Register, OrData)
+#define McD2PciCfg16And(Register, AndData) MmPci16And (0, SA_MC_BUS, 2, 0, Register, AndData)
+#define McD2PciCfg16AndThenOr(Register, AndData, OrData) MmPci16AndThenOr (0, SA_MC_BUS, 2, 0, Register, AndData, OrData)
+
+#define McD2PciCfg8(Register) MmPci8 (0, SA_MC_BUS, 2, 0, Register)
+#define McD2PciCfg8Or(Register, OrData) MmPci8Or (0, SA_MC_BUS, 2, 0, Register, OrData)
+#define McD2PciCfg8And(Register, AndData) MmPci8And (0, SA_MC_BUS, 2, 0, Register, AndData)
+#define McD2PciCfg8AndThenOr(Register, AndData, OrData) MmPci8AndThenOr (0, SA_MC_BUS, 2, 0, Register, AndData, OrData)
+
+//
+// IO
+//
+#ifndef IoIn8
+#define IoIn8(Port) \
+ IoRead8(Port)
+
+#define IoIn16(Port) \
+ IoRead16(Port)
+
+#define IoIn32(Port) \
+ IoRead32(Port)
+
+#define IoOut8(Port, Data) \
+ IoWrite8(Port, Data)
+
+#define IoOut16(Port, Data) \
+ IoWrite16(Port, Data)
+
+#define IoOut32(Port, Data) \
+ IoWrite32(Port, Data)
+
+#endif
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaCommonDefinitions.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaCommonDefinitions.h new file mode 100644 index 0000000000..9889bd80c7 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaCommonDefinitions.h @@ -0,0 +1,247 @@ +/** @file
+ This header file provides common definitions just for System Agent
+ using to avoid including extra module's file.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SA_COMMON_DEFINITIONS_H_
+#define _SA_COMMON_DEFINITIONS_H_
+
+#ifndef PCI_VID
+#define PCI_VID 0x0000 ///< Vendor ID Register
+#define PCI_DID 0x0002 ///< Device ID Register
+#define PCI_CMD 0x0004 ///< PCI Command Register
+#define PCI_STS 0x0006 ///< PCI Status Register
+#define PCI_RID 0x0008 ///< Revision ID Register
+#define PCI_IFT 0x0009 ///< Interface Type
+#define PCI_SCC 0x000A ///< Sub Class Code Register
+#define PCI_BCC 0x000B ///< Base Class Code Register
+#define PCI_CLS 0x000C ///< Cache Line Size
+#define PCI_PMLT 0x000D ///< Primary Master Latency Timer
+#define PCI_HDR 0x000E ///< Header Type Register
+#define PCI_BIST 0x000F ///< Built in Self Test Register
+#define PCI_BAR0 0x0010 ///< Base Address Register 0
+#define PCI_BAR1 0x0014 ///< Base Address Register 1
+#define PCI_BAR2 0x0018 ///< Base Address Register 2
+#define PCI_PBUS 0x0018 ///< Primary Bus Number Register
+#define PCI_SBUS 0x0019 ///< Secondary Bus Number Register
+#define PCI_SUBUS 0x001A ///< Subordinate Bus Number Register
+#define PCI_SMLT 0x001B ///< Secondary Master Latency Timer
+#define PCI_BAR3 0x001C ///< Base Address Register 3
+#define PCI_IOBASE 0x001C ///< I/O base Register
+#define PCI_IOLIMIT 0x001D ///< I/O Limit Register
+#define PCI_SECSTATUS 0x001E ///< Secondary Status Register
+#define PCI_BAR4 0x0020 ///< Base Address Register 4
+#define PCI_MEMBASE 0x0020 ///< Memory Base Register
+#define PCI_MEMLIMIT 0x0022 ///< Memory Limit Register
+#define PCI_BAR5 0x0024 ///< Base Address Register 5
+#define PCI_PRE_MEMBASE 0x0024 ///< Prefetchable memory Base register
+#define PCI_PRE_MEMLIMIT 0x0026 ///< Prefetchable memory Limit register
+#define PCI_PRE_MEMBASE_U 0x0028 ///< Prefetchable memory base upper 32 bits
+#define PCI_PRE_MEMLIMIT_U 0x002C ///< Prefetchable memory limit upper 32 bits
+#define PCI_SVID 0x002C ///< Subsystem Vendor ID
+#define PCI_SID 0x002E ///< Subsystem ID
+#define PCI_IOBASE_U 0x0030 ///< I/O base Upper Register
+#define PCI_IOLIMIT_U 0x0032 ///< I/O Limit Upper Register
+#define PCI_CAPP 0x0034 ///< Capabilities Pointer
+#define PCI_EROM 0x0038 ///< Expansion ROM Base Address
+#define PCI_INTLINE 0x003C ///< Interrupt Line Register
+#define PCI_INTPIN 0x003D ///< Interrupt Pin Register
+#define PCI_MAXGNT 0x003E ///< Max Grant Register
+#define PCI_BRIDGE_CNTL 0x003E ///< Bridge Control Register
+#define PCI_MAXLAT 0x003F ///< Max Latency Register
+#endif
+//
+// Bit Difinitions
+//
+#ifndef BIT0
+#define BIT0 0x0001
+#define BIT1 0x0002
+#define BIT2 0x0004
+#define BIT3 0x0008
+#define BIT4 0x0010
+#define BIT5 0x0020
+#define BIT6 0x0040
+#define BIT7 0x0080
+#define BIT8 0x0100
+#define BIT9 0x0200
+#define BIT10 0x0400
+#define BIT11 0x0800
+#define BIT12 0x1000
+#define BIT13 0x2000
+#define BIT14 0x4000
+#define BIT15 0x8000
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+#endif
+
+#ifndef _PCIACCESS_H_INCLUDED_
+
+#ifndef MmPciAddress
+#define MmPciAddress( Segment, Bus, Device, Function, Register ) \
+ ( (UINTN) PcdGet64 (PcdPciExpressBaseAddress) + \
+ (UINTN)(Bus << 20) + \
+ (UINTN)(Device << 15) + \
+ (UINTN)(Function << 12) + \
+ (UINTN)(Register) \
+ )
+#endif
+
+//
+// UINT64
+//
+#define MmPci64Ptr( Segment, Bus, Device, Function, Register ) \
+ ( (volatile UINT64 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
+
+#define MmPci64( Segment, Bus, Device, Function, Register ) \
+ *MmPci64Ptr( Segment, Bus, Device, Function, Register )
+
+#define MmPci64Or( Segment, Bus, Device, Function, Register, OrData ) \
+ MmPci64( Segment, Bus, Device, Function, Register ) = \
+ (UINT64) ( \
+ MmPci64( Segment, Bus, Device, Function, Register ) | \
+ (UINT64)(OrData) \
+ )
+
+#define MmPci64And( Segment, Bus, Device, Function, Register, AndData ) \
+ MmPci64( Segment, Bus, Device, Function, Register ) = \
+ (UINT64) ( \
+ MmPci64( Segment, Bus, Device, Function, Register ) & \
+ (UINT64)(AndData) \
+ )
+
+#define MmPci64AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
+ MmPci64( Segment, Bus, Device, Function, Register ) = \
+ (UINT64) ( \
+ ( MmPci64( Segment, Bus, Device, Function, Register ) & \
+ (UINT64)(AndData) \
+ ) | \
+ (UINT64)(OrData) \
+ )
+
+//
+// UINT32
+//
+
+#define MmPci32Ptr( Segment, Bus, Device, Function, Register ) \
+ ( (volatile UINT32 *) MmPciAddress( Segment, Bus, Device, Function, Register ) )
+
+#define MmPci32( Segment, Bus, Device, Function, Register ) \
+ *MmPci32Ptr( Segment, Bus, Device, Function, Register )
+
+#define MmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \
+ MmPci32( Segment, Bus, Device, Function, Register ) = \
+ (UINT32) ( \
+ MmPci32( Segment, Bus, Device, Function, Register ) | \
+ (UINT32)(OrData) \
+ )
+
+#define MmPci32And( Segment, Bus, Device, Function, Register, AndData ) \
+ MmPci32( Segment, Bus, Device, Function, Register ) = \
+ (UINT32) ( \
+ MmPci32( Segment, Bus, Device, Function, Register ) & \
+ (UINT32)(AndData) \
+ )
+
+#define MmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
+ MmPci32( Segment, Bus, Device, Function, Register ) = \
+ (UINT32) ( \
+ ( MmPci32( Segment, Bus, Device, Function, Register ) & \
+ (UINT32)(AndData) \
+ ) | \
+ (UINT32)(OrData) \
+ )
+
+//
+// UINT16
+//
+
+#define MmPci16Ptr( Segment, Bus, Device, Function, Register ) \
+ ( (volatile UINT16 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
+
+#define MmPci16( Segment, Bus, Device, Function, Register ) \
+ *MmPci16Ptr( Segment, Bus, Device, Function, Register )
+
+#define MmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \
+ MmPci16( Segment, Bus, Device, Function, Register ) = \
+ (UINT16) ( \
+ MmPci16( Segment, Bus, Device, Function, Register ) | \
+ (UINT16)(OrData) \
+ )
+
+#define MmPci16And( Segment, Bus, Device, Function, Register, AndData ) \
+ MmPci16( Segment, Bus, Device, Function, Register ) = \
+ (UINT16) ( \
+ MmPci16( Segment, Bus, Device, Function, Register ) & \
+ (UINT16)(AndData) \
+ )
+
+#define MmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
+ MmPci16( Segment, Bus, Device, Function, Register ) = \
+ (UINT16) ( \
+ ( MmPci16( Segment, Bus, Device, Function, Register ) & \
+ (UINT16)(AndData) \
+ ) | \
+ (UINT16)(OrData) \
+ )
+
+//
+// UINT8
+//
+
+#define MmPci8Ptr( Segment, Bus, Device, Function, Register ) \
+ ( (volatile UINT8 *)MmPciAddress( Segment, Bus, Device, Function, Register ) )
+
+#define MmPci8( Segment, Bus, Device, Function, Register ) \
+ *MmPci8Ptr( Segment, Bus, Device, Function, Register )
+
+#define MmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \
+ MmPci8( Segment, Bus, Device, Function, Register ) = \
+ (UINT8) ( \
+ MmPci8( Segment, Bus, Device, Function, Register ) | \
+ (UINT8)(OrData) \
+ )
+
+#define MmPci8And( Segment, Bus, Device, Function, Register, AndData ) \
+ MmPci8( Segment, Bus, Device, Function, Register ) = \
+ (UINT8) ( \
+ MmPci8( Segment, Bus, Device, Function, Register ) & \
+ (UINT8)(AndData) \
+ )
+
+#define MmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \
+ MmPci8( Segment, Bus, Device, Function, Register ) = \
+ (UINT8) ( \
+ ( MmPci8( Segment, Bus, Device, Function, Register ) & \
+ (UINT8)(AndData) \
+ ) | \
+ (UINT8)(OrData) \
+ )
+
+#endif
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h new file mode 100644 index 0000000000..5dd8440926 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Include/SaRegs.h @@ -0,0 +1,230 @@ +/** @file
+ Register names for System Agent (SA) registers.
+ <b>Conventions</b>:
+ Prefixes:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values of bits within the registers
+ Definitions beginning with "S_" are register sizes
+ Definitions beginning with "N_" are the bit position
+ In general, SA registers are denoted by "_SA_" in register names
+ Registers / bits that are different between SA generations are denoted by
+ "_SA_[generation_name]_" in register/bit names. e.g., "_SA_BXT_"
+ Registers / bits that are different between SKUs are denoted by "_[SKU_name]"
+ at the end of the register/bit names
+ Registers / bits of new devices introduced in a SA generation will be just named
+ as "_SA_" without [generation_name] inserted.
+
+ Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SA_REGS_H_
+#define _SA_REGS_H_
+
+#include "PlatformBaseAddresses.h"
+
+#define BUNIT_BMISC_MCHBAR_OFFSET 0x6800
+#define BSMR_SMM_OPEN_FOR_IA 0x14
+
+//
+// Default Vendor ID and Subsystem ID
+//
+#define V_INTEL_VENDOR_ID 0x8086 ///< Default Intel Vendor ID
+#define V_SA_DEFAULT_SID 0x7270 ///< Default Intel Subsystem ID
+
+//
+// DEVICE 0 (Memory Controller Hub)
+//
+#define SA_MC_BUS 0x00
+#define SA_MC_DEV 0x00
+#define SA_MC_FUN 0x00
+#define R_SA_MC_VENDOR_ID 0x00
+#define R_SA_MC_DEVICE_ID 0x02
+#define R_SA_MC_REVISION_ID 0x08
+#define V_SA_MC_VID 0x8086
+#define V_SA_MC_DID0 0x0AF0 //Broxton
+#define V_SA_MC_DID1 0x1AF0 //Broxton1
+#define V_SA_MC_DID2 0x4AF0 //Broxton-X
+#define V_SA_MC_DID3 0x5AF0 //Broxton-P
+#define R_SA_MC_CAPID0_A 0xE4
+#define R_SA_MC_CAPID0_B 0xE8
+#define R_SA_MCHBAR_REG 0x48
+
+//
+// Silicon Steppings
+//
+#define V_SA_MC_RID_0 0x00
+#define V_SA_MC_RID_1 0x01
+#define V_SA_MC_RID_3 0x03
+#define V_SA_MC_RID_4 0x04
+#define V_SA_MC_RID_5 0x05
+#define V_SA_MC_RID_6 0x06
+#define V_SA_MC_RID_7 0x07
+#define V_SA_MC_RID_8 0x08
+#define V_SA_MC_RID_9 0x09
+#define V_SA_MC_RID_A 0x0A
+#define V_SA_MC_RID_B 0x0B
+#define V_SA_MC_RID_C 0x0C
+
+///
+/// Maximum number of SDRAM channels supported by the memory controller
+///
+#define SA_MC_MAX_CHANNELS 4
+///
+/// Maximum number of DIMM sockets supported by each channel
+///
+#define SA_MC_MAX_SLOTS 1
+
+///
+/// Maximum number of sides supported per DIMM
+///
+#define SA_MC_MAX_SIDES 2
+
+///
+/// Maximum number of DIMM sockets supported by the memory controller
+///
+#define SA_MC_MAX_SOCKETS (SA_MC_MAX_CHANNELS * SA_MC_MAX_SLOTS)
+
+///
+/// Maximum number of rows supported by the memory controller
+///
+#define SA_MC_MAX_RANKS (SA_MC_MAX_SOCKETS * SA_MC_MAX_SIDES)
+
+///
+/// Maximum number of rows supported by the memory controller
+///
+#define SA_MC_MAX_ROWS (SA_MC_MAX_SIDES * SA_MC_MAX_SOCKETS)
+
+///
+/// Maximum memory supported by the memory controller
+/// 4 GB in terms of KB
+///
+#define SA_MC_MAX_MEM_CAPACITY (4 * 1024 * 1024)
+
+///
+/// Define the SPD Address for DIMM 0
+///
+#define SA_MC_DIMM0_SPD_ADDRESS 0xA0
+
+///
+/// Define the maximum number of data bytes on a system with no ECC memory support.
+///
+#define SA_MC_MAX_BYTES_NO_ECC (8)
+
+///
+/// Define the maximum number of SPD data bytes on a DIMM.
+///
+#define SA_MC_MAX_SPD_SIZE (512)
+
+#define R_SA_GGC (0x50)
+
+#define N_SA_GGC_GGCLCK_OFFSET (0x0)
+#define S_SA_GGC_GGCLCK_WIDTH (0x1)
+#define B_SA_GGC_GGCLCK_MASK (0x1)
+#define V_SA_GGC_GGCLCK_DEFAULT (0x0)
+
+#define N_SA_GGC_IVD_OFFSET (0x1)
+#define S_SA_GGC_IVD_WIDTH (0x1)
+#define B_SA_GGC_IVD_MASK (0x2)
+#define V_SA_GGC_IVD_DEFAULT (0x0)
+
+#define N_SA_GGC_VAMEM_OFFSET (0x2)
+#define S_SA_GGC_VAMEM_WIDTH (0x1)
+#define B_SA_GGC_VAMEM_MASK (0x4)
+#define V_SA_GGC_VAMEM_DEFAULT (0x0)
+
+#define N_SA_GCC_RSVD0_OFFSET (0x3)
+#define S_SA_GCC_RSVD0_WIDTH (0x3)
+#define B_SA_GCC_RSVD0_MASK (0x38)
+#define V_SA_GCC_RSVD0_DEFAULT (0x0)
+
+#define N_SA_GGC_GGMS_OFFSET (0x6)
+#define S_SA_GGC_GGMS_WIDTH (0x2)
+#define B_SA_GGC_GGMS_MASK (0xc0)
+#define V_SA_GGC_GGMS_DEFAULT (0x0)
+#define V_SA_GGC_GGMS_DIS 0
+#define V_SA_GGC_GGMS_2MB 1
+#define V_SA_GGC_GGMS_4MB 2
+#define V_SA_GGC_GGMS_8MB 3
+
+#define N_SA_GGC_GMS_OFFSET (0x8)
+#define S_SA_GGC_GMS_WIDTH (0x8)
+#define B_SA_GGC_GMS_MASK (0xff00)
+#define V_SA_GGC_GMS_DEFAULT (0x01)
+#define V_SA_GGC_GMS_2016MB 0x3F
+
+#define N_SA_GCC_RSVD1_OFFSET (0x10)
+#define S_SA_GCC_RSVD1_WIDTH (0xff)
+#define B_SA_GCC_RSVD1_MASK (0xffff0000)
+#define V_SA_GCC_RSVD1_DEFAULT (0x0)
+
+#define R_SA_DEVEN (0x54)
+
+#define N_SA_DEVEN_D0F0EN_OFFSET (0x0)
+#define S_SA_DEVEN_D0F0EN_WIDTH (0x1)
+#define B_SA_DEVEN_D0F0EN_MASK (0x1)
+#define V_SA_DEVEN_D0F0EN_DEFAULT (0x1)
+
+#define N_SA_DEVEN_D0F1EN_OFFSET (0x1)
+#define S_SA_DEVEN_D0F1EN_WIDTH (0x1)
+#define B_SA_DEVEN_D0F1EN_MASK (0x2)
+#define V_SA_DEVEN_D0F1EN_DEFAULT (0x2)
+
+#define N_SA_DEVEN_RSVD0_OFFSET (0x2)
+#define S_SA_DEVEN_RSVD0_WIDTH (0x1)
+#define B_SA_DEVEN_RSVD0_MASK (0x4)
+#define V_SA_DEVEN_RSVD0_DEFAULT (0x0)
+
+#define N_SA_DEVEN_RSVD_OFFSET (0x3)
+#define S_SA_DEVEN_RSVD_WIDTH (0x1)
+#define B_SA_DEVEN_RSVD_MASK (0x8)
+#define V_SA_DEVEN_RSVD_DEFAULT (0x0)
+
+#define N_SA_DEVEN_D2F0EN_OFFSET (0x4)
+#define S_SA_DEVEN_D2F0EN_WIDTH (0x1)
+#define B_SA_DEVEN_D2F0EN_MASK (0x10)
+#define V_SA_DEVEN_D2F0EN_DEFAULT (0x10)
+
+#define N_SA_DEVEN_D3F0EN_OFFSET (0x5)
+#define S_SA_DEVEN_D3F0EN_WIDTH (0x1)
+#define B_SA_DEVEN_D3F0EN_MASK (0x20)
+#define V_SA_DEVEN_D3F0EN_DEFAULT (0x20)
+
+#define N_SA_DEVEN_RSVD1_OFFSET (0x6)
+#define S_SA_DEVEN_RSVD1_WIDTH (0x1A)
+#define B_SA_DEVEN_RSVD1_MASK (0xFFFFFFC0)
+#define V_SA_DEVEN_RSVD1_DEFAULT (0x0)
+
+#define R_SA_TOLUD (0xbc)
+
+#define SA_IGD_BUS 0x00
+#define SA_IGD_DEV 0x02
+#define SA_IGD_FUN_0 0x00
+#define SA_IGD_FUN_1 0x01
+#define SA_IGD_DEV_FUN (SA_IGD_DEV << 3)
+#define SA_IGD_BUS_DEV_FUN (SA_MC_BUS << 8) + SA_IGD_DEV_FUN
+
+#define R_SA_IGD_VID 0x00
+#define V_SA_IGD_VID 0x8086
+#define V_SA_IGD_DID 0x0A84
+#define V_SA_IGD_DID_BXTP 0x5A84
+#define V_SA_IGD_DID_BXTP_1 0x5A85
+#define R_SA_IGD_CMD 0x04
+#define R_SA_IGD_GTTMMADR 0x10
+#define R_SA_IGD_GMADR 0x18
+#define R_SA_IGD_MSAC_OFFSET 0x62
+
+#define IGD_SWSCI_OFFSET 0x00E0
+#define IGD_ASLS_OFFSET 0x00FC
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSaPolicyLib/DxeSaPolicyLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSaPolicyLib/DxeSaPolicyLib.c new file mode 100644 index 0000000000..0313a07274 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSaPolicyLib/DxeSaPolicyLib.c @@ -0,0 +1,250 @@ +/** @file
+ This file provides services for Dxe SA policy library.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "DxeSaPolicyLibrary.h"
+
+#define SA_DXE_MISC_CONFIG_GUID { 0xc7715fbc, 0xe2ab, 0x4a33, {0x84, 0x0f, 0x5d, 0xcd, 0x01, 0x98, 0xe5, 0x52}}
+#define IGD_PANEL_CONFIG_GUID { 0x5fd88b4c, 0xb658, 0x4650, {0xb3, 0xce, 0xa5, 0x9b, 0xb9, 0x91, 0xbf, 0xd4}}
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONFIG_BLOCK_HEADER mBxtSaDxeIpBlocks[] = {
+ // Block GUID Block Size, Revision
+ { SA_DXE_MISC_CONFIG_GUID, sizeof (SA_DXE_MISC_CONFIG), SA_DXE_MISC_CONFIG_REVISION, { 0, 0, 0 } },
+ { IGD_PANEL_CONFIG_GUID, sizeof (IGD_PANEL_CONFIG), IGD_PANEL_CONFIG_REVISION, { 0, 0, 0 } }
+};
+
+//
+// Function call to Load defaults for Individial IP Blocks
+//
+EFI_STATUS
+EFIAPI
+LoadIgdPanelDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ IGD_PANEL_CONFIG *IgdPanelConfig = NULL;
+
+ //
+ // Initialize the IGD Panel configuration
+ //
+ IgdPanelConfig = ConfigBlockPointer;
+ IgdPanelConfig->PFITStatus = 0x00;
+#if (ENBDT_PF_ENABLE == 1)
+ IgdPanelConfig->PanelSelect = 0x00;
+#endif
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EFIAPI
+LoadSaDxeMiscDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ SA_DXE_MISC_CONFIG *SaDxeMiscConfig = NULL;
+
+ SaDxeMiscConfig = ConfigBlockPointer;
+
+ DEBUG ((DEBUG_INFO, "SaDxeMiscConfig->Header.Guid = %g\n", SaDxeMiscConfig->Header.Guid));
+ DEBUG ((DEBUG_INFO, "SaDxeMiscConfig->Header.Size = 0x%x\n", SaDxeMiscConfig->Header.Size));
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Initialize default settings for each SA DXE Config block.
+
+ @param[in] ConfigBlockPointer The buffer pointer that will be initialized as specific config block.
+ @param[in] BlockId Request to initialize defaults of specified config block by given Block ID.
+
+ @retval EFI_SUCCESS The given buffer has contained the defaults of requested config block.
+ @retval EFI_NOT_FOUND Block ID is not defined so no default Config block will be initialized.
+
+**/
+EFI_STATUS
+EFIAPI
+LoadSaDxeConfigBlockDefault (
+ IN VOID *ConfigBlockPointer,
+ IN EFI_GUID BlockGuid
+ )
+{
+ if (CompareGuid (&BlockGuid, &gIgdPanelConfigGuid)) {
+ LoadIgdPanelDefault (ConfigBlockPointer);
+ } else {
+ if (CompareGuid (&BlockGuid, &gSaDxeMiscConfigGuid)) {
+ LoadSaDxeMiscDefault (ConfigBlockPointer);
+ } else {
+ return EFI_NOT_FOUND;
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Creates the Config Blocks for SA DXE Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[in, out] SiSaPolicy The pointer to get SI/SA Policy Protocol.
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateSaDxeConfigBlocks(
+ IN OUT SA_POLICY_PROTOCOL **SaPolicy
+ )
+{
+ UINT32 TotalBlockSize;
+ UINT16 TotalBlockCount;
+ UINT16 BlockCount;
+ VOID *ConfigBlockPointer;
+ EFI_STATUS Status;
+ SA_POLICY_PROTOCOL *SaDxeInitPolicy;
+ UINT32 ConfigBlockHdrSize;
+ UINT32 RequiredSize;
+
+ SaDxeInitPolicy = NULL;
+ TotalBlockSize = 0;
+
+ TotalBlockCount = sizeof (mBxtSaDxeIpBlocks) / sizeof (CONFIG_BLOCK_HEADER);
+ DEBUG ((DEBUG_INFO, "TotalBlockCount = 0x%x\n", TotalBlockCount));
+
+ for (BlockCount = 0; BlockCount < TotalBlockCount; BlockCount++) {
+ TotalBlockSize += (UINT32) mBxtSaDxeIpBlocks[BlockCount].Size;
+ DEBUG ((DEBUG_INFO, "TotalBlockSize after adding Block[0x%x]= 0x%x\n", BlockCount, TotalBlockSize));
+ }
+ DEBUG ((DEBUG_INFO, "TotalBlockSize Final = 0x%x\n", TotalBlockSize));
+
+ ConfigBlockHdrSize = GetSizeOfConfigBlockTableHeaders ((UINT16) TotalBlockCount);
+
+ RequiredSize = ConfigBlockHdrSize + TotalBlockSize;
+
+ Status = CreateConfigBlockTable ((VOID *) &SaDxeInitPolicy, TotalBlockCount, RequiredSize);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize Policy Revision
+ //
+ SaDxeInitPolicy->TableHeader.Header.Revision = SA_POLICY_PROTOCOL_REVISION_1;
+
+ //
+ // Initialize ConfigBlockPointer to NULL
+ //
+ ConfigBlockPointer = NULL;
+
+ //
+ // Loop to identify each config block from mBxtSaIpBlocks[] Table and add each of them
+ //
+ for (BlockCount = 0; BlockCount < TotalBlockCount; BlockCount++) {
+ ConfigBlockPointer = (VOID *) &mBxtSaDxeIpBlocks[BlockCount];
+ Status = AddConfigBlock ((VOID *) SaDxeInitPolicy, (VOID *) &ConfigBlockPointer);
+ ASSERT_EFI_ERROR (Status);
+ LoadSaDxeConfigBlockDefault ((VOID *) ConfigBlockPointer, mBxtSaDxeIpBlocks[BlockCount].Guid);
+ }
+
+ //
+ // Assignment for returning SaInitPolicy config block base address
+ //
+ *SaPolicy = SaDxeInitPolicy;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Install protocol for SA Policy.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] DxeSaPolicy The pointer to SA Policy Protocol instance
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval Others Internal error when install protocol.
+
+**/
+EFI_STATUS
+EFIAPI
+SaInstallPolicyProtocol (
+ IN SA_POLICY_PROTOCOL *DxeSaPolicy
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE Handle;
+
+ //
+ // Print SA DXE Policy
+ //
+ SaPrintPolicyProtocol (DxeSaPolicy);
+
+ //
+ // Install protocol to to allow access to this Policy.
+ //
+ Handle = NULL;
+ Status = gBS->InstallProtocolInterface (
+ &Handle,
+ &gSaPolicyProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ DxeSaPolicy
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
+/**
+ This function prints the SA DXE phase policy.
+
+ @param[in] SaPolicy The pointer to SA Policy Protocol instance.
+
+**/
+VOID
+SaPrintPolicyProtocol (
+ IN SA_POLICY_PROTOCOL *SaPolicy
+ )
+{
+ EFI_STATUS Status;
+ SA_DXE_MISC_CONFIG *SaDxeMiscConfig = NULL;
+ IGD_PANEL_CONFIG *IgdPanelConfig = NULL;
+
+ Status = GetConfigBlock ((CONFIG_BLOCK_TABLE_HEADER *) SaPolicy, &gIgdPanelConfigGuid, (VOID *) &IgdPanelConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = GetConfigBlock ((CONFIG_BLOCK_TABLE_HEADER *) SaPolicy, &gSaDxeMiscConfigGuid, (VOID *) &SaDxeMiscConfig);
+ ASSERT_EFI_ERROR (Status);
+
+ DEBUG ((DEBUG_INFO, "\n------------------------ SA Platform Policy (DXE) dump BEGIN -----------------\n"));
+ DEBUG ((DEBUG_INFO, " Revision : %x\n", SaPolicy->TableHeader.Header.Revision));
+
+ DEBUG ((DEBUG_INFO, "------------------------ IGD_PANEL_CONFIGURATION -----------------\n"));
+ DEBUG ((DEBUG_INFO, " Panel Scaling : %x\n", IgdPanelConfig->PFITStatus));
+#if (ENBDT_PF_ENABLE == 1)
+ DEBUG ((DEBUG_INFO, " Panel Selection : %x\n", IgdPanelConfig->PanelSelect));
+#endif
+ DEBUG ((DEBUG_INFO, "------------------------ SA_MISC_CONFIGURATION -----------------\n"));
+ DEBUG ((DEBUG_INFO, " S0ix Support : %x\n", SaDxeMiscConfig->S0ixSupported));
+ DEBUG ((DEBUG_INFO, " Audio Type Support : %x\n", SaDxeMiscConfig->AudioTypeSupport));
+
+ DEBUG ((DEBUG_INFO, "\n------------------------ SA Platform Policy (DXE) dump END -----------------\n"));
+
+ return;
+}
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf new file mode 100644 index 0000000000..64abde7e03 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSaPolicyLib/DxeSaPolicyLib.inf @@ -0,0 +1,44 @@ +## @file
+# Dxe SA policy library.
+#
+# Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = DxeSaPolicyLib
+ FILE_GUID = B402A3A4-4B82-410E-B79C-5914880A05E7
+ VERSION_STRING = 1.0
+ MODULE_TYPE = BASE
+ LIBRARY_CLASS = DxeSaPolicyLib
+
+[Sources]
+ DxeSaPolicyLib.c
+ DxeSaPolicyLibrary.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BroxtonSiPkg/BroxtonSiPkg.dec
+
+[LibraryClasses]
+ BaseMemoryLib
+ UefiRuntimeServicesTableLib
+ UefiBootServicesTableLib
+ PciLib
+ DebugLib
+ PostCodeLib
+ ConfigBlockLib
+
+[Protocols]
+ gSaPolicyProtocolGuid ## PRODUCES
+ gIgdPanelConfigGuid
+ gSaDxeMiscConfigGuid
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h new file mode 100644 index 0000000000..6b54ce2d63 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h @@ -0,0 +1,30 @@ +/** @file
+ Header file for the Dxe SA policy library.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _DXE_SA_POLICY_LIBRARY_H_
+#define _DXE_SA_POLICY_LIBRARY_H_
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DxeSaPolicyLib.h>
+#include <Protocol/SaPolicy.h>
+#include <Library/ConfigBlockLib.h>
+
+#endif // _DXE_SA_POLICY_LIBRARY_H_
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/DxeSmbiosMemoryLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/DxeSmbiosMemoryLib.c new file mode 100644 index 0000000000..41330db082 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/DxeSmbiosMemoryLib.c @@ -0,0 +1,139 @@ +/** @file
+ This driver will determine memory configuration information from the chipset
+ and memory and create SMBIOS memory structures appropriately.
+
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SmbiosMemory.h"
+
+/**
+ This library will determine memory configuration information from the chipset
+ and memory and report the memory configuration info to the DataHub.
+
+ @param[in] ImageHandle Handle for the image of this driver.
+ @param[in] SystemTable Pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS If the data is successfully reported.
+ @retval EFI_NOT_FOUND If the HOB list could not be located.
+
+**/
+EFI_STATUS
+EFIAPI
+SmbiosMemory (
+ )
+{
+ EFI_STATUS Status;
+
+ Status = InstallSmbiosType16 ();
+ ASSERT_EFI_ERROR (Status);
+
+ Status = InstallSmbiosType17 ();
+ ASSERT_EFI_ERROR (Status);
+
+ Status = InstallSmbiosType19 ();
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
+/**
+ Add an SMBIOS table entry using EFI_SMBIOS_PROTOCOL.
+ Create the full table record using the formatted section plus each non-null string, plus the terminating (double) null.
+
+ @param[in] Entry The data for the fixed portion of the SMBIOS entry.
+ The format of the data is determined by EFI_SMBIOS_TABLE_HEADER.
+ Type. The size of the formatted area is defined by
+ EFI_SMBIOS_TABLE_HEADER. Length and either followed by a
+ double-null (0x0000) or a set of null terminated strings and a null.
+ @param[in] TableStrings Set of string pointers to append onto the full record.
+ If TableStrings is null, no strings are appended. Null strings
+ are skipped.
+ @param[in] NumberOfStrings Number of TableStrings to append, null strings are skipped.
+ @param[out] SmbiosHandle A unique handle will be assigned to the SMBIOS record.
+
+ @retval EFI_SUCCESS Table was added.
+ @retval EFI_OUT_OF_RESOURCES Table was not added due to lack of system resources.
+
+**/
+EFI_STATUS
+AddSmbiosEntry (
+ IN EFI_SMBIOS_TABLE_HEADER *Entry,
+ IN CHAR8 **TableStrings,
+ IN UINT8 NumberOfStrings,
+ OUT EFI_SMBIOS_HANDLE *SmbiosHandle
+ )
+{
+ EFI_STATUS Status;
+ EFI_SMBIOS_TABLE_HEADER *Record;
+ CHAR8 *StringPtr;
+ UINTN Size;
+ UINTN i;
+
+ //
+ // Calculate the total size of the full record
+ //
+ Size = Entry->Length;
+
+ //
+ // Add the size of each non-null string
+ //
+ if (TableStrings != NULL) {
+ for (i = 0; i < NumberOfStrings; i++) {
+ if (TableStrings[i] != NULL) {
+ Size += AsciiStrSize (TableStrings[i]);
+ }
+ }
+ }
+
+ //
+ // Add the size of the terminating double null
+ // If there were any strings added, just add the second null
+ //
+ if (Size == Entry->Length) {
+ Size += 2;
+ } else {
+ Size += 1;
+ }
+
+ //
+ // Initialize the full record
+ //
+ Record = (EFI_SMBIOS_TABLE_HEADER *) AllocateZeroPool (Size);
+ if (Record == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+ CopyMem (Record, Entry, Entry->Length);
+
+ //
+ // Copy the strings to the end of the record
+ //
+ StringPtr = ((CHAR8 *) Record) + Entry->Length;
+ Size = Size - Entry->Length;
+ if (TableStrings != NULL) {
+ for (i = 0; i < NumberOfStrings; i++) {
+ if (TableStrings[i] != NULL) {
+ AsciiStrCpyS (StringPtr, Size, TableStrings[i]);
+ StringPtr += AsciiStrSize (TableStrings[i]);
+ Size = Size - AsciiStrSize (TableStrings[i]);
+ }
+ }
+ }
+
+ *SmbiosHandle = SMBIOS_HANDLE_PI_RESERVED;
+ Status = mSmbios->Add (mSmbios, NULL, SmbiosHandle, Record);
+
+ FreePool (Record);
+ return Status;
+}
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/DxeSmbiosMemoryLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/DxeSmbiosMemoryLib.inf new file mode 100644 index 0000000000..de35f56b10 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/DxeSmbiosMemoryLib.inf @@ -0,0 +1,58 @@ +## @file
+# SmbiosMemory Driver module.
+#
+# Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = DxeSmbiosMemoryLib
+ FILE_GUID = 66BDCD3F-8520-4958-AF30-617E7384DDE2
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_DRIVER
+ LIBRARY_CLASS = SmbiosMemoryLib
+
+[Sources]
+ SmbiosMemory.h
+ DxeSmbiosMemoryLib.c
+ SmbiosType16.c
+ SmbiosType17.c
+ SmbiosType19.c
+ SmbiosType17Strings.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BroxtonSiPkg/BroxtonSiPkg.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+ BaseLib
+ DebugLib
+ PrintLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ IoLib
+ HiiLib
+
+[Guids]
+ gEfiMemorySubClassGuid ## UNDEFINED
+
+[Protocols]
+ gEfiDataHubProtocolGuid ## CONSUMES
+ gEfiHiiDatabaseProtocolGuid ## CONSUMES
+ gEfiHiiStringProtocolGuid ## CONSUMES
+ gMemInfoProtocolGuid
+
+[Depex]
+ gEfiDataHubProtocolGuid AND
+ gEfiHiiDatabaseProtocolGuid AND
+ gMemInfoProtocolGuid
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosMemory.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosMemory.h new file mode 100644 index 0000000000..b62cd67e6e --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosMemory.h @@ -0,0 +1,237 @@ +/** @file
+ Header file for the SMBIOS Memory library.
+ This driver will determine memory configuration information from the chipset
+ and memory and create SMBIOS memory structures appropriately.
+
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _SMBIOS_MEMORY_H_
+#define _SMBIOS_MEMORY_H_
+
+#include <Uefi/UefiBaseType.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/PrintLib.h>
+#include <Library/HobLib.h>
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBus.h>
+#include <SaAccess.h>
+#include <IndustryStandard/SmBios.h>
+
+//
+// Driver Consumed Protocol Prototypes
+//
+#include <Protocol/MemInfo.h>
+
+//
+// Non-static SMBIOS table data to be filled later with a dynamically generated value
+//
+#define TO_BE_FILLED 0
+#define TO_BE_FILLED_STRING " " //< Initial value should not be NULL
+
+//
+// String references in SMBIOS tables. This eliminates the need for pointers.
+//
+#define NO_STRING_AVAILABLE 0
+#define STRING_1 1
+#define STRING_2 2
+#define STRING_3 3
+#define STRING_4 4
+#define STRING_5 5
+#define STRING_6 6
+#define STRING_7 7
+
+//
+// SMBIOS Table values with special meaning
+//
+#define SMBIOS_TYPE16_USE_EXTENDED_MAX_CAPACITY 0x80000000
+
+#define SMBIOS_TYPE17_UNKNOWN_SIZE 0xFFFF
+#define SMBIOS_TYPE17_USE_EXTENDED_SIZE 0x7FFF
+#define SMBIOS_TYPE17_KB_BIT_MASK 0x8000
+#define SMBIOS_TYPE17_NUMBER_OF_STRINGS 6
+
+#define SMBIOS_TYPE19_USE_EXTENDED_ADDRESSES 0xFFFFFFFF
+
+//
+// Memory module type definition in DDR3 SPD Data
+//
+#define DDR_MTYPE_SPD_OFFSET 3 ///< Module type, offset 3, bits (3:0)
+#define DDR_MTYPE_SPD_MASK 0x0F ///< Module Type mask
+#define DDR_MTYPE_RDIMM 0x01 ///< Registered DIMM Memory
+#define DDR_MTYPE_UDIMM 0x02 ///< Unbuffered DIMM Memory
+#define DDR_MTYPE_SODIMM 0x03 ///< Small Outline DIMM Memory
+#define DDR_MTYPE_MICRO_DIMM 0x04 ///< Micro-DIMM Memory
+#define DDR_MTYPE_MINI_RDIMM 0x05 ///< Mini Registered DIMM Memory
+#define DDR_MTYPE_MINI_UDIMM 0x06 ///< Mini Unbuffered DIMM Memory
+
+//
+// Memory device type definition in DDR3 SPD Data
+//
+#define DDR_DTYPE_SPD_OFFSET 2 ///< Device type, offset 2, bits (7:0)
+#define DDR_DTYPE_DDR3 11 ///< DDR3 memory type
+#define DDR_DTYPE_DDR4 12 ///< DDR4 memory type
+#define DDR_DTYPE_LPDDR3 0xF1 ///< LPDDR3 memory type
+
+//
+// Maximum rank memory size supported by the memory controller: 8GB (in terms of KB) for DDR4 and 4 GB for other types
+//
+#define MAX_RANK_CAPACITY (4 * 1024 * 1024)
+#define MAX_RANK_CAPACITY_DDR4 (8 * 1024 * 1024)
+
+//
+// DDR3 and DDR4 SPD Register Bytes
+//
+#define DDR4_SPD_BUFFER_SIZE 384
+#define DDR4_SPD_MANUFACTURER_ID_LSB 320
+#define DDR4_SPD_MANUFACTURER_ID_MSB 321
+#define DDR4_SPD_PART_NO_START_BYTE 329
+#define DDR4_SPD_PART_NO_END_BYTE 348
+#define DDR4_SPD_SERIAL_NO_START_BYTE 325
+#define DDR4_SPD_SERIAL_NO_END_BYTE 328
+#define DDR4_SPD_MEMORY_BUS_WIDTH_BYTE 13
+
+#define DDR3_SPD_BUFFER_SIZE 256
+#define DDR3_SPD_MANUFACTURER_ID_LSB 117
+#define DDR3_SPD_MANUFACTURER_ID_MSB 118
+#define DDR3_SPD_PART_NO_START_BYTE 128
+#define DDR3_SPD_PART_NO_END_BYTE 145
+#define DDR3_SPD_SERIAL_NO_START_BYTE 122
+#define DDR3_SPD_SERIAL_NO_END_BYTE 125
+#define DDR3_SPD_MEMORY_BUS_WIDTH_BYTE 8
+
+#define FREQ_800 0x00
+#define FREQ_1066 0x01
+#define FREQ_1333 0x02
+#define FREQ_1600 0x03
+#define FREQ_1866 0x04
+#define FREQ_2133 0x05
+#define FREQ_2666 0x07
+#define FREQ_3200 0x08
+
+enum {
+ DDRType_DDR3 = 0,
+ DDRType_DDR3L = 1,
+ DDRType_DDR3U = 2,
+ DDRType_DDR3All = 3,
+ DDRType_LPDDR2 = 4,
+ DDRType_LPDDR3 = 5,
+ DDRType_DDR4 = 6
+};
+
+#ifndef MEMORY_ASSET_TAG
+#define MEMORY_ASSET_TAG "9876543210"
+#endif
+//
+// Memory Module Manufacture ID List Structure
+//
+typedef struct {
+ UINT8 Index;
+ UINT8 ManufactureId;
+ CHAR8 *ManufactureName;
+} MEMORY_MODULE_MANUFACTURE_LIST;
+
+#pragma pack(1)
+typedef struct {
+ CHAR8 *DeviceLocator;
+ CHAR8 *BankLocator;
+ CHAR8 *Manufacturer;
+ CHAR8 *SerialNumber;
+ CHAR8 *AssetTag;
+ CHAR8 *PartNumber;
+} SMBIOS_TYPE17_STRING_ARRAY;
+#pragma pack()
+
+//
+// Module-wide global variables
+//
+MEM_INFO_PROTOCOL *mMemInfoHob;
+extern EFI_SMBIOS_PROTOCOL *mSmbios;
+EFI_SMBIOS_HANDLE mSmbiosType16Handle;
+
+extern CHAR8 *DimmToDevLocator[];
+extern CHAR8 *DimmToBankLocator[];
+extern MEMORY_MODULE_MANUFACTURE_LIST MemoryModuleManufactureList[];
+
+//
+// Prototypes
+//
+/**
+ Add an SMBIOS table entry using EFI_SMBIOS_PROTOCOL.
+ Create the full table record using the formatted section plus each non-null string, plus the terminating (double) null.
+
+ @param[in] Entry The data for the fixed portion of the SMBIOS entry.
+ The format of the data is determined by EFI_SMBIOS_TABLE_HEADER.
+ Type. The size of the formatted area is defined by
+ EFI_SMBIOS_TABLE_HEADER. Length and either followed by a
+ double-null (0x0000) or a set of null terminated strings and a null.
+ @param[in] TableStrings Set of string pointers to append onto the full record.
+ If TableStrings is null, no strings are appended. Null strings
+ are skipped.
+ @param[in] NumberOfStrings Number of TableStrings to append, null strings are skipped.
+ @param[in] SmbiosProtocol Instance of Smbios Protocol
+ @param[out] SmbiosHandle A unique handle will be assigned to the SMBIOS record.
+
+ @retval EFI_SUCCESS Table was added.
+ @retval EFI_OUT_OF_RESOURCES Table was not added due to lack of system resources.
+
+**/
+EFI_STATUS
+AddSmbiosEntry (
+ IN EFI_SMBIOS_TABLE_HEADER *Entry,
+ IN CHAR8 **TableStrings,
+ IN UINT8 NumberOfStrings,
+ OUT EFI_SMBIOS_HANDLE *SmbiosHandle
+ );
+
+/**
+ This function installs SMBIOS Table Type 16 (Physical Memory Array).
+
+ @retval EFI_SUCCESS If the data is successfully reported.
+ @retval EFI_OUT_OF_RESOURCES If not able to get resources.
+
+**/
+EFI_STATUS
+InstallSmbiosType16 (
+ );
+
+/**
+ This function installs SMBIOS Table Type 17 (Memory Device).
+ This function installs one table per memory device slot, whether populated or not.
+
+ @retval EFI_SUCCESS If the data is successfully reported.
+ @retval EFI_OUT_OF_RESOURCES If not able to get resources.
+ @retval EFI_INVALID_PARAMETER If a required parameter in a subfunction is NULL.
+
+**/
+EFI_STATUS
+InstallSmbiosType17 (
+ );
+
+/**
+ This function installs SMBIOS Table Type 19 (Physical Memory Array).
+
+ @retval EFI_SUCCESS If the data is successfully reported.
+ @retval EFI_OUT_OF_RESOURCES If not able to get resources.
+
+**/
+EFI_STATUS
+InstallSmbiosType19 (
+ );
+
+#endif
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType16.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType16.c new file mode 100644 index 0000000000..2124543b16 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType16.c @@ -0,0 +1,112 @@ +/** @file
+ This library will determine memory configuration information from the chipset
+ and memory and create SMBIOS memory structures appropriately.
+
+ Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SmbiosMemory.h"
+
+//
+// Physical Memory Array (Type 16) data
+//
+GLOBAL_REMOVE_IF_UNREFERENCED SMBIOS_TABLE_TYPE16 SmbiosTableType16Data = {
+ { EFI_SMBIOS_TYPE_PHYSICAL_MEMORY_ARRAY, sizeof (SMBIOS_TABLE_TYPE16), 0 },
+ MemoryArrayLocationSystemBoard, ///< Location
+ MemoryArrayUseSystemMemory, ///< Use
+ TO_BE_FILLED, ///< MemoryErrorCorrection
+ TO_BE_FILLED, ///< MaximumCapacity
+ 0xFFFE, ///< MemoryErrorInformationHandle
+ TO_BE_FILLED, ///< NumberOfMemoryDevices
+ 0, ///< ExtendedMaximumCapacity
+};
+
+
+/**
+ This function installs SMBIOS Table Type 16 (Physical Memory Array).
+
+ @param[in] SmbiosProtocol Instance of Smbios Protocol.
+
+ @retval EFI_SUCCESS If the data is successfully reported.
+ @retval EFI_OUT_OF_RESOURCES If not able to get resources.
+
+**/
+EFI_STATUS
+InstallSmbiosType16 (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT8 ChannelASlotMap;
+ UINT8 ChannelBSlotMap;
+ UINT8 BitIndex;
+ UINT16 MaxSockets;
+ UINT8 ChannelASlotNum;
+ UINT8 ChannelBSlotNum;
+
+ //
+ // Get Memory size parameters for each rank from the chipset registers
+ //
+ Status = gBS->LocateProtocol (&gMemInfoProtocolGuid, NULL, (VOID **) &mMemInfoHob);
+
+ //
+ // Configure the data for TYPE 16 SMBIOS Structure
+ //
+ //
+ // Create physical array and associated data for all mainboard memory
+ //
+ SmbiosTableType16Data.MemoryErrorCorrection = MemoryErrorCorrectionNone;
+
+ //
+ // Get the Memory DIMM info from policy protocols
+ //
+ ChannelASlotMap = 0x01;
+ ChannelBSlotMap = 0x01;
+ ChannelASlotNum = 0;
+ ChannelBSlotNum = 0;
+
+ for (BitIndex = 0; BitIndex < 8; BitIndex++) {
+ if ((ChannelASlotMap >> BitIndex) & BIT0) {
+ ChannelASlotNum++;
+ }
+
+ if ((ChannelBSlotMap >> BitIndex) & BIT0) {
+ ChannelBSlotNum++;
+ }
+ }
+ MaxSockets = ChannelASlotNum + ChannelBSlotNum;
+ if (mMemInfoHob->MemInfoData.ddrType == 0) {
+ if ((MAX_RANK_CAPACITY_DDR4 * SA_MC_MAX_SIDES * MaxSockets) < SMBIOS_TYPE16_USE_EXTENDED_MAX_CAPACITY) {
+ SmbiosTableType16Data.MaximumCapacity = MAX_RANK_CAPACITY_DDR4 * SA_MC_MAX_SIDES * MaxSockets;
+ } else {
+ SmbiosTableType16Data.MaximumCapacity = SMBIOS_TYPE16_USE_EXTENDED_MAX_CAPACITY;
+ SmbiosTableType16Data.ExtendedMaximumCapacity = ((UINT64) MAX_RANK_CAPACITY_DDR4) * SA_MC_MAX_SIDES * MaxSockets * 1024; // Convert from KB to Byte
+ }
+ } else {
+ if ((MAX_RANK_CAPACITY * SA_MC_MAX_SIDES * MaxSockets) < SMBIOS_TYPE16_USE_EXTENDED_MAX_CAPACITY) {
+ SmbiosTableType16Data.MaximumCapacity = MAX_RANK_CAPACITY * SA_MC_MAX_SIDES * MaxSockets;
+ } else {
+ SmbiosTableType16Data.MaximumCapacity = SMBIOS_TYPE16_USE_EXTENDED_MAX_CAPACITY;
+ SmbiosTableType16Data.ExtendedMaximumCapacity = ((UINT64) MAX_RANK_CAPACITY) * SA_MC_MAX_SIDES * MaxSockets * 1024; // Convert from KB to Byte
+ }
+ }
+ SmbiosTableType16Data.NumberOfMemoryDevices = MaxSockets;
+
+ //
+ // Install SMBIOS Table Type 16
+ //
+ Status = AddSmbiosEntry ((EFI_SMBIOS_TABLE_HEADER *) &SmbiosTableType16Data, NULL, 0, &mSmbiosType16Handle);
+ DEBUG ((DEBUG_INFO, "\nInstall SMBIOS Table Type 16"));
+
+ return Status;
+}
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType17.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType17.c new file mode 100644 index 0000000000..4c73c55593 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType17.c @@ -0,0 +1,384 @@ +/** @file
+ This library will determine memory configuration information from the chipset
+ and memory and create SMBIOS memory structures appropriately.
+
+ Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SmbiosMemory.h"
+
+//
+// Memory Device (Type 17) data
+//
+GLOBAL_REMOVE_IF_UNREFERENCED SMBIOS_TABLE_TYPE17 SmbiosTableType17Data = {
+ { EFI_SMBIOS_TYPE_MEMORY_DEVICE, sizeof (SMBIOS_TABLE_TYPE17), 0 },
+ TO_BE_FILLED, ///< MemoryArrayHandle
+ 0xFFFE, ///< MemoryErrorInformationHandle
+ TO_BE_FILLED, ///< TotalWidth
+ TO_BE_FILLED, ///< DataWidth
+ TO_BE_FILLED, ///< Size
+ TO_BE_FILLED, ///< FormFactor
+ 0, ///< DeviceSet
+ STRING_1, ///< DeviceLocator
+ STRING_2, ///< BankLocator
+ TO_BE_FILLED, ///< MemoryType
+ { ///< TypeDetail
+ 0, ///< Reserved :1;
+ 0, ///< Other :1;
+ 0, ///< Unknown :1;
+ 0, ///< FastPaged :1;
+ 0, ///< StaticColumn :1;
+ 0, ///< PseudoStatic :1;
+ TO_BE_FILLED, ///< Rambus :1;
+ TO_BE_FILLED, ///< Synchronous :1;
+ 0, ///< Cmos :1;
+ 0, ///< Edo :1;
+ 0, ///< WindowDram :1;
+ 0, ///< CacheDram :1;
+ 0, ///< Nonvolatile :1;
+ 0, ///< Registered :1;
+ 0, ///< Unbuffered :1;
+ 0, ///< Reserved1 :1;
+ },
+ TO_BE_FILLED, ///< Speed
+ TO_BE_FILLED, ///< Manufacturer
+ TO_BE_FILLED, ///< SerialNumber
+ TO_BE_FILLED, ///< AssetTag
+ TO_BE_FILLED, ///< PartNumber
+ TO_BE_FILLED, ///< Attributes
+ TO_BE_FILLED, ///< ExtendedSize
+ TO_BE_FILLED, ///< ConfiguredMemoryClockSpeed
+ TO_BE_FILLED, ///< MinimumVoltage
+ TO_BE_FILLED, ///< MaximumVoltage
+ TO_BE_FILLED, ///< ConfiguredVoltage
+};
+GLOBAL_REMOVE_IF_UNREFERENCED SMBIOS_TYPE17_STRING_ARRAY SmbiosTableType17Strings = {
+ TO_BE_FILLED_STRING, ///< DeviceLocator
+ TO_BE_FILLED_STRING, ///< BankLocator
+ TO_BE_FILLED_STRING, ///< Manufacturer
+ TO_BE_FILLED_STRING, ///< SerialNumber
+#ifdef MEMORY_ASSET_TAG ///< AssetTag
+ MEMORY_ASSET_TAG,
+#else
+ "0123456789",
+#endif
+ TO_BE_FILLED_STRING ///< PartNumber
+};
+
+
+//
+// Even SPD Addresses only as we read Words
+//
+const UINT8
+ SpdAddress[] = { 2, 8, 116, 118, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144 };
+
+
+/**
+ This function installs SMBIOS Table Type 17 (Memory Device).
+ This function installs one table per memory device slot, whether populated or not.
+
+ @param[in] SmbiosProtocol Instance of Smbios Protocol.
+
+ @retval EFI_SUCCESS If the data is successfully reported.
+ @retval EFI_OUT_OF_RESOURCES If not able to get resources.
+ @retval EFI_INVALID_PARAMETER If a required parameter in a subfunction is NULL.
+
+**/
+EFI_STATUS
+InstallSmbiosType17 (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT16 Index;
+ UINT32 DimmMemorySizeInMB;
+ UINT8 Dimm;
+ UINT8 *SmbusBuffer;
+ UINTN SmbusBufferSize;
+ UINTN SmbusOffset;
+ CHAR8 *StringBuffer;
+ CHAR8 *StringBufferStart;
+ UINTN StringBufferSize;
+ CHAR8 StringBuffer2[4];
+ UINT8 IndexCounter;
+ UINTN IdListIndex;
+ BOOLEAN SlotPresent;
+ UINT16 MemoryTotalWidth;
+ UINT16 MemoryDataWidth;
+ UINT8 i;
+ BOOLEAN FoundManufacturer;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+ UINTN StrBufferLen;
+
+ Status = EFI_SUCCESS;
+
+ //
+ // StringBuffer should only use around 50 to 60 characters max.
+ // Therefore, allocate around double that, as a saftey margin
+ //
+ StringBufferSize = (sizeof (CHAR8)) * 100;
+ StringBufferStart = AllocateZeroPool (StringBufferSize);
+ if (StringBufferStart == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SmbusBuffer = NULL;
+ SmbusBufferSize = 0x100; //< SPD data section is exactly 256 bytes.
+ SmbusBuffer = AllocatePool (SmbusBufferSize);
+ if (SmbusBuffer == NULL) {
+ FreePool (StringBufferStart);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // Get Memory size parameters for each rank from the chipset registers
+ //
+ Status = gBS->LocateProtocol (&gMemInfoProtocolGuid, NULL, (VOID **) &mMemInfoHob);
+
+ //
+ // Each instance of table type 17 has the same MemoryArrayHandle
+ //
+ SmbiosTableType17Data.MemoryArrayHandle = mSmbiosType16Handle;
+
+ for (Dimm = 0; Dimm < SA_MC_MAX_SOCKETS; Dimm++) {
+ SlotPresent = FALSE;
+ if (mMemInfoHob->MemInfoData.DimmPresent[Dimm]) {
+ SlotPresent = TRUE;
+ }
+ //
+ // Don't create Type 17 tables for sockets that don't exist
+ //
+ if (!SlotPresent) {
+ continue;
+ }
+ //
+ // Generate Memory Device info (Type 17)
+ //
+ ZeroMem (SmbusBuffer, SmbusBufferSize);
+
+ //
+ // Only read the SPD data if the DIMM is populated in the slot.
+ //
+ if (SlotPresent) {
+ for (i = 0; i < sizeof SpdAddress; i++) {
+ SmbusOffset = SpdAddress[i];
+ *(UINT16 *) (SmbusBuffer + SmbusOffset) = *(UINT16 *) (mMemInfoHob->MemInfoData.DimmsSpdData[Dimm] + SmbusOffset);
+ }
+ }
+
+ //
+ // Use SPD data to generate Device Type info
+ //
+ SmbiosTableType17Strings.DeviceLocator = DimmToDevLocator[Dimm];
+ SmbiosTableType17Strings.BankLocator = DimmToBankLocator[Dimm];
+
+ if (SlotPresent) {
+ //
+ // Reset StringBuffer
+ //
+ StringBuffer = StringBufferStart;
+
+ //
+ // Show name for known manufacturer or ID for unknown manufacturer
+ //
+ FoundManufacturer = FALSE;
+
+ //
+ // Calculate index counter
+ // Clearing Bit7 as it is the Parity Bit for Byte 117
+ //
+ IndexCounter = SmbusBuffer[117] & (~0x80);
+
+ //
+ // Convert memory manufacturer ID to string
+ //
+ for (IdListIndex = 0; MemoryModuleManufactureList[IdListIndex].Index != 0xff; IdListIndex++) {
+ if (MemoryModuleManufactureList[IdListIndex].Index == IndexCounter &&
+ MemoryModuleManufactureList[IdListIndex].ManufactureId == SmbusBuffer[118]
+ ) {
+ SmbiosTableType17Strings.Manufacturer = MemoryModuleManufactureList[IdListIndex].ManufactureName;
+ FoundManufacturer = TRUE;
+ break;
+ }
+ }
+ //
+ // Use original data if no conversion information in conversion table
+ //
+ StrBufferLen = StringBufferSize / sizeof (CHAR8);
+
+ if (!(FoundManufacturer)) {
+ AsciiStrCpyS (StringBuffer, StrBufferLen, "");
+ for (Index = 117; Index < 119; Index++) {
+ AsciiValueToString (StringBuffer2, PREFIX_ZERO, SmbusBuffer[Index], 2);
+ AsciiStrCatS (StringBuffer, StrBufferLen, StringBuffer2);
+ }
+ SmbiosTableType17Strings.Manufacturer = StringBuffer;
+ StringBuffer += AsciiStrSize (StringBuffer);
+ }
+
+ AsciiStrCpyS (StringBuffer, StrBufferLen, "");
+ for (Index = 122; Index < 126; Index++) {
+ AsciiValueToString (StringBuffer2, PREFIX_ZERO, SmbusBuffer[Index], 2);
+ AsciiStrCatS (StringBuffer, StrBufferLen, StringBuffer2);
+ }
+ SmbiosTableType17Strings.SerialNumber = StringBuffer;
+ StringBuffer += AsciiStrSize (StringBuffer);
+
+ AsciiStrCpyS (StringBuffer, StrBufferLen, "");
+ for (Index = 128; Index < 146; Index++) {
+ AsciiSPrint (StringBuffer2, 4, "%c", SmbusBuffer[Index]);
+ AsciiStrCatS (StringBuffer, StrBufferLen, StringBuffer2);
+ }
+ SmbiosTableType17Strings.PartNumber = StringBuffer;
+
+ ASSERT ((StringBuffer + AsciiStrSize (StringBuffer)) < (StringBufferStart + StringBufferSize));
+
+ SmbiosTableType17Data.Manufacturer = STRING_3;
+ SmbiosTableType17Data.SerialNumber = STRING_4;
+ SmbiosTableType17Data.AssetTag = STRING_5;
+ SmbiosTableType17Data.PartNumber = STRING_6;
+
+ MemoryDataWidth = 8 * (1 << mMemInfoHob->MemInfoData.BusWidth);
+ MemoryTotalWidth = MemoryDataWidth;
+ SmbiosTableType17Data.TotalWidth = MemoryTotalWidth;
+ SmbiosTableType17Data.DataWidth = MemoryDataWidth;
+
+ DimmMemorySizeInMB = mMemInfoHob->MemInfoData.dimmSize[Dimm];
+
+ if (DimmMemorySizeInMB < SMBIOS_TYPE17_USE_EXTENDED_SIZE) {
+ SmbiosTableType17Data.Size = (UINT16) DimmMemorySizeInMB;
+ SmbiosTableType17Data.ExtendedSize = 0;
+ } else {
+ SmbiosTableType17Data.Size = SMBIOS_TYPE17_USE_EXTENDED_SIZE;
+ SmbiosTableType17Data.ExtendedSize = DimmMemorySizeInMB;
+ }
+
+ switch (SmbusBuffer[DDR_MTYPE_SPD_OFFSET] & DDR_MTYPE_SPD_MASK) {
+ case DDR_MTYPE_SODIMM:
+ SmbiosTableType17Data.FormFactor = MemoryFormFactorSodimm;
+ break;
+
+ case DDR_MTYPE_RDIMM:
+ case DDR_MTYPE_MINI_RDIMM:
+ SmbiosTableType17Data.FormFactor = MemoryFormFactorRimm;
+ break;
+
+ case DDR_MTYPE_UDIMM:
+ case DDR_MTYPE_MICRO_DIMM:
+ case DDR_MTYPE_MINI_UDIMM:
+ default:
+ SmbiosTableType17Data.FormFactor = MemoryFormFactorDimm;
+ }
+
+ //
+ // Memory Type
+ //
+ switch (mMemInfoHob->MemInfoData.ddrType) {
+ case DDRType_DDR3:
+ case DDRType_DDR3L:
+ case DDRType_DDR3U:
+ case DDRType_LPDDR3:
+ SmbiosTableType17Data.MemoryType = MemoryTypeDdr3;
+ break;
+ default:
+ SmbiosTableType17Data.MemoryType = 0x1E;
+ break;
+ }
+
+ if (SmbiosTableType17Data.FormFactor == MemoryFormFactorRimm) {
+ SmbiosTableType17Data.TypeDetail.Rambus = 1;
+ } else {
+ SmbiosTableType17Data.TypeDetail.Rambus = 0;
+ }
+ SmbiosTableType17Data.TypeDetail.Synchronous = 1;
+
+ //
+ // Memory Freq
+ //
+ switch (mMemInfoHob->MemInfoData.ddrFreq){
+ case FREQ_800:
+ SmbiosTableType17Data.Speed = 800;
+ break;
+ case FREQ_1066:
+ SmbiosTableType17Data.Speed = 1066;
+ break;
+ case FREQ_1333:
+ SmbiosTableType17Data.Speed = 1333;
+ break;
+ case FREQ_1600:
+ SmbiosTableType17Data.Speed = 1600;
+ break;
+ case FREQ_1866:
+ SmbiosTableType17Data.Speed = 1866;
+ break;
+ case FREQ_2133:
+ SmbiosTableType17Data.Speed = 2133;
+ break;
+ case FREQ_2666:
+ SmbiosTableType17Data.Speed = 2666;
+ break;
+ case FREQ_3200:
+ SmbiosTableType17Data.Speed = 3200;
+ break;
+ default:
+ SmbiosTableType17Data.Speed = 0;
+ break;
+ }
+ SmbiosTableType17Data.ConfiguredMemoryClockSpeed = SmbiosTableType17Data.Speed;
+ } else {
+ //
+ // Memory is not Populated in this slot.
+ //
+ SmbiosTableType17Strings.DeviceLocator = DimmToDevLocator[Dimm];
+ SmbiosTableType17Strings.BankLocator = DimmToBankLocator[Dimm];
+
+ SmbiosTableType17Strings.Manufacturer = NULL;
+ SmbiosTableType17Strings.SerialNumber = NULL;
+ SmbiosTableType17Strings.PartNumber = NULL;
+
+ SmbiosTableType17Data.Manufacturer = NO_STRING_AVAILABLE;
+ SmbiosTableType17Data.SerialNumber = NO_STRING_AVAILABLE;
+ SmbiosTableType17Data.AssetTag = STRING_3;
+ SmbiosTableType17Data.PartNumber = NO_STRING_AVAILABLE;
+
+ SmbiosTableType17Data.TotalWidth = 0;
+ SmbiosTableType17Data.DataWidth = 0;
+ SmbiosTableType17Data.Size = 0;
+ SmbiosTableType17Data.FormFactor = MemoryFormFactorDimm;
+ SmbiosTableType17Data.MemoryType = MemoryTypeUnknown;
+ SmbiosTableType17Data.TypeDetail.Rambus = 0;
+ SmbiosTableType17Data.TypeDetail.Synchronous = 0;
+ SmbiosTableType17Data.Speed = 0;
+ SmbiosTableType17Data.Attributes = 0;
+ SmbiosTableType17Data.ExtendedSize = 0;
+ }
+
+ //
+ // Generate Memory Device info (Type 17)
+ //
+ Status = AddSmbiosEntry (
+ (EFI_SMBIOS_TABLE_HEADER *) &SmbiosTableType17Data,
+ (CHAR8 **) &SmbiosTableType17Strings,
+ SMBIOS_TYPE17_NUMBER_OF_STRINGS,
+ &SmbiosHandle);
+ if (EFI_ERROR (Status)) {
+ goto CleanAndExit;
+ }
+ }
+CleanAndExit:
+ FreePool (SmbusBuffer);
+ FreePool (StringBufferStart);
+ DEBUG ((DEBUG_INFO, "\nInstall SMBIOS Table Type 17"));
+
+ return Status;
+}
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType17Strings.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType17Strings.c new file mode 100644 index 0000000000..4665febab0 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType17Strings.c @@ -0,0 +1,42 @@ +/** @file
+ This library will determine memory configuration information from the chipset
+ and memory and create SMBIOS memory structures appropriately.
+
+ Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SmbiosMemory.h"
+
+GLOBAL_REMOVE_IF_UNREFERENCED CHAR8 *DimmToDevLocator[] = {
+ "ChannelA-DIMM0",
+ "ChannelA-DIMM1",
+ "ChannelB-DIMM0",
+ "ChannelB-DIMM1"
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED CHAR8 *DimmToBankLocator[] = {
+ "BANK 0",
+ "BANK 1",
+ "BANK 2",
+ "BANK 3"
+};
+
+GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MODULE_MANUFACTURE_LIST MemoryModuleManufactureList[] = {
+ {0, 0x2c, "Micron"},
+ {0, 0xad, "SK Hynix"},
+ {0, 0xce, "Samsung"},
+ {1, 0x4f, "Transcend"},
+ {1, 0x98, "Kingston"},
+ {2, 0xfe, "Elpida"},
+ {0xff, 0xff, 0}
+};
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType19.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType19.c new file mode 100644 index 0000000000..521fa793da --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/DxeSmbiosMemoryLib/SmbiosType19.c @@ -0,0 +1,92 @@ +/** @file
+ This library will determine memory configuration information from the chipset
+ and memory and create SMBIOS memory structures appropriately.
+
+ Copyright (c) 2013 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "SmbiosMemory.h"
+
+//
+// Memory Array Mapped Address (Type 19) data
+//
+GLOBAL_REMOVE_IF_UNREFERENCED SMBIOS_TABLE_TYPE19 SmbiosTableType19Data = {
+ { EFI_SMBIOS_TYPE_MEMORY_ARRAY_MAPPED_ADDRESS, sizeof (SMBIOS_TABLE_TYPE19), 0 },
+ 0, ///< StartingAddress
+ TO_BE_FILLED, ///< EndingAddress
+ TO_BE_FILLED, ///< MemoryArrayHandle
+ TO_BE_FILLED, ///< PartitionWidth
+ 0, ///< ExtendedStartingAddress
+ 0, ///< ExtendedEndingAddress
+};
+
+
+/**
+ This function installs SMBIOS Table Type 19 (Physical Memory Array).
+
+ @retval EFI_SUCCESS If the data is successfully reported.
+ @retval EFI_OUT_OF_RESOURCES If not able to get resources.
+
+**/
+EFI_STATUS
+InstallSmbiosType19 (
+ VOID
+ )
+{
+ EFI_STATUS Status;
+ UINT64 TotalMemorySizeInKB;
+ UINT8 Dimm;
+ BOOLEAN SlotPresent;
+ EFI_SMBIOS_HANDLE SmbiosHandle;
+
+ TotalMemorySizeInKB = 0;
+
+ //
+ // Get Memory size parameters for each rank from the chipset registers
+ //
+ Status = gBS->LocateProtocol (&gMemInfoProtocolGuid, NULL, (VOID **) &mMemInfoHob);
+
+ //
+ // Calculate the TotalMemorySizeInKB by adding the size of all populated sockets
+ //
+ for (Dimm = 0; Dimm < MAX_SOCKETS; Dimm++) {
+ //
+ // Use channel slot map to check whether the Socket is supported in this SKU, some SKU only has 2 Sockets totally
+ //
+ SlotPresent = FALSE;
+ if (mMemInfoHob->MemInfoData.DimmPresent[Dimm]) {
+ SlotPresent = TRUE;
+ }
+ if (SlotPresent) {
+ TotalMemorySizeInKB += LShiftU64 (mMemInfoHob->MemInfoData.dimmSize[Dimm], 10);
+ }
+ }
+
+ if (TotalMemorySizeInKB > SMBIOS_TYPE19_USE_EXTENDED_ADDRESSES) {
+ SmbiosTableType19Data.StartingAddress = SMBIOS_TYPE19_USE_EXTENDED_ADDRESSES;
+ SmbiosTableType19Data.EndingAddress = SMBIOS_TYPE19_USE_EXTENDED_ADDRESSES;
+ SmbiosTableType19Data.ExtendedEndingAddress = TotalMemorySizeInKB - 1;
+ } else {
+ SmbiosTableType19Data.EndingAddress = (UINT32) (TotalMemorySizeInKB - 1);
+ }
+ SmbiosTableType19Data.MemoryArrayHandle = mSmbiosType16Handle;
+ SmbiosTableType19Data.PartitionWidth = MAX_SOCKETS;
+
+ //
+ // Generate Memory Array Mapped Address info (TYPE 19)
+ //
+ Status = AddSmbiosEntry ((EFI_SMBIOS_TABLE_HEADER *) &SmbiosTableType19Data, NULL, 0, &SmbiosHandle);
+ DEBUG ((DEBUG_INFO, "\nInstall SMBIOS Table Type 19"));
+
+ return Status;
+}
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/PeiSaPolicyLib/PeiSaPolicyLib.c b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/PeiSaPolicyLib/PeiSaPolicyLib.c new file mode 100644 index 0000000000..2b92562c0c --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/PeiSaPolicyLib/PeiSaPolicyLib.c @@ -0,0 +1,432 @@ +/** @file
+ This file provides services for Pei SA policy default initialization.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PeiSaPolicyLibrary.h"
+
+//
+// @todo: Remove the duplicate definition of the GUIDs and make it a location function.
+// Because mBxtSaIpBlocks' initializer must be a constant, we need to define those GUID for it.
+//
+#define SA_MISC_CONFIG_GUID { 0xc5c9145f, 0x61fb, 0x4abe, { 0x88, 0x0a, 0xf2, 0x56, 0x89, 0x9f, 0x40, 0xb0}}
+#define GRAPHICS_CONFIG_GUID { 0x0319c56b, 0xc43a, 0x42f1, { 0x80, 0xbe, 0xca, 0x5b, 0xd1, 0xd5, 0xc9, 0x28}}
+#define MEMORY_CONFIG_GUID { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1, 0x97, 0xb8, 0xa1, 0xe4, 0xbf}}
+#define IPU_CONFIG_GUID { 0x67eeefd0, 0x9e42, 0x48c8, { 0xbd, 0xab, 0xfd, 0x0d, 0x23, 0x69, 0x88, 0x0b}}
+#define SA_PRE_MEM_CONFIG_GUID { 0x7200eef0, 0xbe7f, 0x4061, { 0x93, 0xe3, 0x3c, 0xd0, 0x36, 0x7c, 0xe1, 0x51}}
+#if (ENBDT_PF_ENABLE == 1)
+#define HYBRID_GRAPHICS_CONFIG_GUID { 0x0b7e694d, 0xb909, 0x4097, { 0x9c, 0x03, 0x5e, 0x72, 0x84, 0x89, 0xf7, 0x09}}
+#endif
+
+GLOBAL_REMOVE_IF_UNREFERENCED CONFIG_BLOCK_HEADER mBxtSaIpBlocks[] = {
+ // Block GUID Block Size, Revision
+ {SA_MISC_CONFIG_GUID, sizeof (SA_MISC_CONFIG), SA_MISC_CONFIG_REVISION, {0, 0, 0}},
+ {GRAPHICS_CONFIG_GUID, sizeof (GRAPHICS_CONFIG), GRAPHICS_CONFIG_REVISION, {0, 0, 0}},
+ {IPU_CONFIG_GUID, sizeof (IPU_CONFIG), IPU_CONFIG_REVISION, {0, 0, 0}},
+#if (ENBDT_PF_ENABLE == 1)
+ {HYBRID_GRAPHICS_CONFIG_GUID, sizeof (HYBRID_GRAPHICS_CONFIG), HYBRID_GRAPHICS_CONFIG_REVISION, {0, 0, 0}},
+#endif
+ {MEMORY_CONFIG_GUID, sizeof (MEMORY_CONFIGURATION), MEMORY_CONFIG_REVISION, {0, 0, 0}}
+};
+GLOBAL_REMOVE_IF_UNREFERENCED CONFIG_BLOCK_HEADER mBxtSaIpPreMemBlocks[] = {
+ // Block GUID Block Size, Revision
+ {SA_PRE_MEM_CONFIG_GUID, sizeof (SA_PRE_MEM_CONFIG), SA_PRE_MEM_CONFIG_REVISION, { 0, 0, 0}}
+};
+
+//
+// Function call to Load defaults for Individial IP Blocks
+//
+EFI_STATUS
+EFIAPI
+LoadSaMiscDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ SA_MISC_CONFIG *MiscConfig;
+
+ MiscConfig = ConfigBlockPointer;
+
+ DEBUG ((DEBUG_INFO, "MiscConfig->Header.Guid = %g\n", MiscConfig->Header.Guid));
+ DEBUG ((DEBUG_INFO, "MiscConfig->Header.Size = 0x%x\n", MiscConfig->Header.Size));
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EFIAPI
+LoadIpuDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ IPU_CONFIG *IpuPolicy;
+
+ IpuPolicy = ConfigBlockPointer;
+ DEBUG ((DEBUG_INFO, "IpuPolicy->Header.Guid = %g\n", IpuPolicy->Header.Guid));
+ DEBUG ((DEBUG_INFO, "IpuPolicy->Header.Size = 0x%x\n", IpuPolicy->Header.Size));
+
+ IpuPolicy->SaIpuEnable = 1;
+ IpuPolicy->IpuMmAdr = 0xCF000000;
+
+ return EFI_SUCCESS;
+}
+
+
+EFI_STATUS
+EFIAPI
+LoadGraphicsDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ GRAPHICS_CONFIG *GtConfig;
+
+ GtConfig = ConfigBlockPointer;
+
+ //
+ // Initialize the Graphics configuration
+ //
+ GtConfig->GmAdr = 0xA0000000;
+ GtConfig->GttMmAdr = 0xBF000000;
+ GtConfig->EnableRenderStandby = 1;
+ GtConfig->PavpEnable = 1;
+ GtConfig->PmSupport = 1;
+ GtConfig->PavpPr3 = 1;
+ GtConfig->PeiGraphicsPeimInit = 0;
+ //
+ // Initialize the CdClock to 675 Mhz
+ //
+ GtConfig->CdClock = 3;
+
+ return EFI_SUCCESS;
+}
+
+
+#if (ENBDT_PF_ENABLE == 1)
+EFI_STATUS
+EFIAPI
+LoadHybridGraphicsDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ HYBRID_GRAPHICS_CONFIG *HgConfig;
+
+ HgConfig = ConfigBlockPointer;
+
+ //
+ // Initialize the Hybrid Graphics configuration
+ //
+ HgConfig->HgEnabled = 0x0;
+ HgConfig->HgDelayAfterPwrEn = 300;
+ HgConfig->HgDelayAfterHoldReset = 100;
+
+ return EFI_SUCCESS;
+}
+#endif
+
+
+EFI_STATUS
+EFIAPI
+LoadSaPreMemDefault (
+ IN VOID *ConfigBlockPointer
+ )
+{
+ SA_PRE_MEM_CONFIG *SaPreMemConfig;
+
+ SaPreMemConfig = ConfigBlockPointer;
+
+ //
+ // Initialize the Graphics configuration
+ //
+ SaPreMemConfig->GttSize = 3;
+ SaPreMemConfig->IgdDvmt50PreAlloc = 2;
+ SaPreMemConfig->InternalGraphics = 1;
+ SaPreMemConfig->PrimaryDisplay = 0;
+ SaPreMemConfig->ApertureSize = 2;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Initialize default settings for each SA Config block.
+
+ @param[in] ConfigBlockPointer The buffer pointer that will be initialized as specific config block.
+ @param[in] BlockId Request to initialize defaults of specified config block by given Block ID.
+
+ @retval EFI_SUCCESS The given buffer has contained the defaults of requested config block.
+ @retval EFI_NOT_FOUND Block ID is not defined so no default Config block will be initialized.
+
+**/
+EFI_STATUS
+EFIAPI
+LoadConfigBlockDefault (
+ IN VOID *ConfigBlockPointer,
+ IN EFI_GUID BlockGuid
+ )
+{
+ if (CompareGuid (&BlockGuid, &gSaMiscConfigGuid)) {
+ LoadSaMiscDefault (ConfigBlockPointer);
+ } else {
+ if (CompareGuid (&BlockGuid, &gGraphicsConfigGuid)) {
+ LoadGraphicsDefault (ConfigBlockPointer);
+ } else {
+ if (CompareGuid (&BlockGuid, &gIpuConfigGuid)) {
+ LoadIpuDefault (ConfigBlockPointer);
+ } else {
+ if (CompareGuid (&BlockGuid, &gSaPreMemConfigGuid)) {
+ LoadSaPreMemDefault (ConfigBlockPointer);
+ }
+#if (ENBDT_PF_ENABLE == 1)
+ else {
+ if (CompareGuid (&BlockGuid, &gHybridGraphicsConfigGuid)) {
+ LoadHybridGraphicsDefault (ConfigBlockPointer);
+ }
+#endif
+ else {
+ return EFI_NOT_FOUND;
+ }
+
+
+#if (ENBDT_PF_ENABLE == 1)
+ }
+#endif
+ }
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Creates the Pre-Mem Config Blocks for SA Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[in, out] SiSaPolicyPpi The pointer to get SI/SA Policy PPI instance.
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer.
+
+**/
+EFI_STATUS
+EFIAPI
+SaCreatePreMemConfigBlocks(
+ IN OUT SI_SA_POLICY_PPI **SiSaPolicyPpi
+ )
+{
+ UINT32 TotalBlockSize;
+ UINT16 TotalBlockCount;
+ UINT16 BlockCount;
+ VOID *ConfigBlockPointer;
+ EFI_STATUS Status;
+ SI_SA_POLICY_PPI *SaInitPolicy;
+ UINT32 ConfigBlockHdrSize;
+ UINT32 RequiredSize;
+
+ SaInitPolicy = NULL;
+ TotalBlockCount = sizeof (mBxtSaIpPreMemBlocks) / sizeof (CONFIG_BLOCK_HEADER);
+ DEBUG ((DEBUG_INFO, "TotalBlockCount = 0x%x\n", TotalBlockCount));
+
+ TotalBlockSize = 0;
+
+ for (BlockCount = 0; BlockCount < TotalBlockCount; BlockCount++) {
+ TotalBlockSize += (UINT32) mBxtSaIpPreMemBlocks[BlockCount].Size;
+ DEBUG ((DEBUG_INFO, "TotalBlockSize after adding Block[0x%x]= 0x%x\n", BlockCount, TotalBlockSize));
+ }
+ DEBUG ((DEBUG_INFO, "TotalBlockSize Final = 0x%x\n", TotalBlockSize));
+
+ ConfigBlockHdrSize = GetSizeOfConfigBlockTableHeaders ((UINT16) TotalBlockCount);
+
+ RequiredSize = ConfigBlockHdrSize + TotalBlockSize;
+
+ Status = CreateConfigBlockTable ((VOID *) &SaInitPolicy, TotalBlockCount, RequiredSize);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize Policy Revision
+ //
+ SaInitPolicy->TableHeader.Header.Revision = SA_POLICY_PPI_REVISION;
+ //
+ // Initialize ConfigBlockPointer to NULL
+ //
+ ConfigBlockPointer = NULL;
+ //
+ // Loop to identify each config block from mBxtSaIpPreMemBlocks[] Table and add each of them
+ //
+ for (BlockCount = 0; BlockCount < TotalBlockCount; BlockCount++) {
+ ConfigBlockPointer = (VOID *) &mBxtSaIpPreMemBlocks[BlockCount];
+ Status = AddConfigBlock ((VOID *) SaInitPolicy, (VOID *) &ConfigBlockPointer);
+ ASSERT_EFI_ERROR (Status);
+ LoadConfigBlockDefault ((VOID *) ConfigBlockPointer, mBxtSaIpPreMemBlocks[BlockCount].Guid);
+ }
+ //
+ // Assignment for returning SaInitPolicy config block base address
+ //
+ *SiSaPolicyPpi = SaInitPolicy;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Creates the Config Blocks for SA Policy.
+ It allocates and zero out buffer, and fills in the Intel default settings.
+
+ @param[in, out] SiSaPolicyPpi The pointer to get SI/SA Policy PPI instance.
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlocks (
+ IN OUT SI_SA_POLICY_PPI **SiSaPolicyPpi
+ )
+{
+ UINT32 TotalBlockSize;
+ UINT16 TotalBlockCount;
+ UINT16 BlockCount;
+ VOID *ConfigBlockPointer;
+ EFI_STATUS Status;
+ SI_SA_POLICY_PPI *SaInitPolicy;
+ UINT32 ConfigBlockHdrSize;
+ UINT32 RequiredSize;
+
+ SaInitPolicy = NULL;
+ TotalBlockCount = sizeof (mBxtSaIpBlocks) / sizeof (CONFIG_BLOCK_HEADER);
+ DEBUG ((DEBUG_INFO, "TotalBlockCount = 0x%x\n", TotalBlockCount));
+
+ TotalBlockSize = 0;
+
+ for (BlockCount = 0 ; BlockCount < TotalBlockCount; BlockCount++) {
+ TotalBlockSize += (UINT32 )mBxtSaIpBlocks[BlockCount].Size;
+ DEBUG ((DEBUG_INFO, "TotalBlockSize after adding Block[0x%x]= 0x%x\n", BlockCount, TotalBlockSize));
+ }
+ DEBUG ((DEBUG_INFO, "TotalBlockSize Final = 0x%x\n", TotalBlockSize));
+
+ ConfigBlockHdrSize = GetSizeOfConfigBlockTableHeaders ((UINT16) TotalBlockCount);
+
+ RequiredSize = ConfigBlockHdrSize + TotalBlockSize;
+
+ Status = CreateConfigBlockTable ((VOID *) &SaInitPolicy, TotalBlockCount, RequiredSize);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Initialize Policy Revision
+ //
+ SaInitPolicy->TableHeader.Header.Revision = SA_POLICY_PPI_REVISION;
+ //
+ // Initialize ConfigBlockPointer to NULL
+ //
+ ConfigBlockPointer = NULL;
+ //
+ // Loop to identify each config block from mBxtSaIpBlocks[] Table and add each of them
+ //
+ for (BlockCount = 0 ; BlockCount < TotalBlockCount; BlockCount++) {
+ ConfigBlockPointer = (VOID *) &mBxtSaIpBlocks[BlockCount];
+ Status = AddConfigBlock ((VOID *) SaInitPolicy, (VOID *) &ConfigBlockPointer);
+ ASSERT_EFI_ERROR (Status);
+ LoadConfigBlockDefault ((VOID *) ConfigBlockPointer, mBxtSaIpBlocks[BlockCount].Guid);
+ }
+ //
+ // Assignment for returning SaInitPolicy config block base address
+ //
+ *SiSaPolicyPpi = SaInitPolicy;
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Install PPI SiSaPolicyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] SiSaPolicyPpi Pointer of policy structure.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer.
+
+**/
+EFI_STATUS
+EFIAPI
+SiSaInstallPolicyPpi (
+ IN SI_SA_POLICY_PPI *SiSaPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SiSaInstallPolicyPpiDesc;
+
+ SiSaInstallPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ ASSERT (SiSaInstallPolicyPpiDesc != NULL);
+ if (SiSaInstallPolicyPpiDesc == NULL) {
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ //
+ // Initialize the PPI
+ //
+ SiSaInstallPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SiSaInstallPolicyPpiDesc->Guid = &gSiSaPolicyPpiGuid;
+ SiSaInstallPolicyPpiDesc->Ppi = SiSaPolicyPpi;
+
+ //
+ // Install PEI SA Policy PPI
+ //
+ Status = PeiServicesInstallPpi (SiSaInstallPolicyPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
+
+/**
+ SaInstallPreMemPolicyPpi installs Sa Pre Mem PolicyPpi.
+ While installed, RC assumes the Policy is ready and finalized. So please update and override
+ any setting before calling this function.
+
+ @param[in] SaPreMemPolicyPpi The pointer to SA PREMEM Policy PPI instance.
+
+ @retval EFI_SUCCESS The policy is installed.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer.
+
+**/
+EFI_STATUS
+EFIAPI
+SaInstallPreMemPolicyPpi (
+ IN SI_SA_POLICY_PPI *SaPolicyPpi
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PPI_DESCRIPTOR *SaPreMemPolicyPpiDesc;
+
+ SaPreMemPolicyPpiDesc = (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (sizeof (EFI_PEI_PPI_DESCRIPTOR));
+ if (SaPreMemPolicyPpiDesc == NULL) {
+ ASSERT (FALSE);
+ return EFI_OUT_OF_RESOURCES;
+ }
+
+ SaPreMemPolicyPpiDesc->Flags = EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;
+ SaPreMemPolicyPpiDesc->Guid = &gSiSaPreMemPolicyPpiGuid;
+ SaPreMemPolicyPpiDesc->Ppi = SaPolicyPpi;
+
+ //
+ // Install PREMEM Policy PPI
+ //
+ Status = PeiServicesInstallPpi (SaPreMemPolicyPpiDesc);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf new file mode 100644 index 0000000000..54a4d90c0a --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/PeiSaPolicyLib/PeiSaPolicyLib.inf @@ -0,0 +1,47 @@ +## @file
+# Pei SA policy library.
+#
+# Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+#
+# This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php.
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = PeiSaPolicyLib
+ FILE_GUID = B612937D-2674-4e5f-9EAB-3B94CCF31C9E
+ VERSION_STRING = 1.0
+ MODULE_TYPE = PEIM
+ LIBRARY_CLASS = PeiSaPolicyLib
+
+[Sources]
+ PeiSaPolicyLib.c
+ PeiSaPolicyLibrary.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ BroxtonSiPkg/BroxtonSiPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ PeiServicesLib
+ MemoryAllocationLib
+ ConfigBlockLib
+ BaseMemoryLib
+
+[Ppis]
+ gSiSaPolicyPpiGuid ## PRODUCES
+ gSiSaPreMemPolicyPpiGuid ## PRODUCES
+ gSaMiscConfigGuid ## PRODUCES
+ gGraphicsConfigGuid ## PRODUCES
+ gMemoryConfigGuid ## PRODUCES
+ gIpuConfigGuid ## PRODUCES
+ gHybridGraphicsConfigGuid ## PRODUCES
+ gSaPreMemConfigGuid
diff --git a/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/PeiSaPolicyLib/PeiSaPolicyLibrary.h b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/PeiSaPolicyLib/PeiSaPolicyLibrary.h new file mode 100644 index 0000000000..26a6e67968 --- /dev/null +++ b/Silicon/BroxtonSoC/BroxtonSiPkg/NorthCluster/Library/PeiSaPolicyLib/PeiSaPolicyLibrary.h @@ -0,0 +1,70 @@ +/** @file
+ Header file for the Pei SA policy library.
+
+ Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PEI_SA_POLICY_LIBRARY_H_
+#define _PEI_SA_POLICY_LIBRARY_H_
+
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/ConfigBlockLib.h>
+#include <Ppi/SaPolicy.h>
+#include <Library/PeiSaPolicyLib.h>
+
+#define SaIoRead8 IoRead8
+#define SaIoRead16 IoRead16
+#define SaIoRead32 IoRead32
+#define SaIoWrite8 IoWrite8
+#define SaIoWrite16 IoWrite16
+#define SaIoWrite32 IoWrite32
+#define SaCopyMem CopyMem
+#define SaSetMem SetMem
+#define SaLShiftU64 LShiftU64
+#define SaRShiftU64 RShiftU64
+#define SaMultU64x32 MultU64x32
+
+#define RTC_INDEX_REGISTER (0x70)
+#define RTC_TARGET_REGISTER (0x71)
+#define R_PCH_RTC_INDEX_ALT (0x74)
+#define R_PCH_RTC_TARGET_ALT (0x75)
+#define R_PCH_RTC_EXT_INDEX_ALT (0x76)
+#define R_PCH_RTC_EXT_TARGET_ALT (0x77)
+
+#define RTC_INDEX_MASK (0x7F)
+#define RTC_BANK_SIZE (0x80)
+
+#define RTC_SECONDS (0x00)
+#define RTC_MINUTES (0x02)
+#define RTC_HOURS (0x04)
+#define RTC_DAY_OF_MONTH (0x07)
+#define RTC_MONTH (0x08)
+#define RTC_YEAR (0x09)
+#define CMOS_REGA (0x0A)
+#define CMOS_REGB (0x0B)
+#define CMOS_REGC (0x0C)
+#define CMOS_REGD (0x0D)
+
+#define RTC_UPDATE_IN_PROGRESS (0x80)
+#define RTC_HOLD (0x80)
+#define RTC_MODE_24HOUR (0x02)
+#define RTC_CLOCK_DIVIDER (0x20)
+#define RTC_RATE_SELECT (0x06)
+
+#define BCD2BINARY(A) (((((A) >> 4) & 0xF) * 10) + ((A) & 0xF))
+#define CENTURY_OFFSET (2000)
+
+#endif // _PEI_SA_POLICY_LIBRARY_H_
+
|