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-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h35
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h91
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/BiosId.h35
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h219
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h161
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h66
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h139
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/IdccData.h109
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/ItkData.h75
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h37
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/OsSelection.h90
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h44
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h185
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h437
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h284
-rw-r--r--Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h1351
16 files changed, 3358 insertions, 0 deletions
diff --git a/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h b/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h
new file mode 100644
index 0000000000..663b26d4da
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/AcpiTableStorage.h
@@ -0,0 +1,35 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ AcpiTableStorage.h
+
+Abstract:
+
+ GUID for the ACPI Table Storage filename.
+
+ This GUID is defined in the Tiano ACPI Table Storage EPS.
+
+--*/
+
+#ifndef _ACPI_TABLE_STORAGE_H_
+#define _ACPI_TABLE_STORAGE_H_
+
+#define EFI_ACPI_TABLE_STORAGE_GUID \
+ { 0x7e374e25, 0x8e01, 0x4fee, {0x87, 0xf2, 0x39, 0xc, 0x23, 0xc6, 0x6, 0xcd} }
+
+extern EFI_GUID gEfiAcpiTableStorageGuid;
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h b/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h
new file mode 100644
index 0000000000..54df0b5b31
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/AlertStandardFormat.h
@@ -0,0 +1,91 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+ Asf.h
+
+Abstract:
+
+ Alert Standard Format address variable
+
+--*/
+
+#ifndef AlertStandardFormat_h_included
+#define AlertStandardFormat_h_included
+
+
+#pragma pack(1)
+
+//
+// ASF address
+//
+//
+// {3D995FB4-4F05-4073-BE72-A19CFB5DE690}
+//
+#define ALERT_STANDARD_FORMAT_VARIABLE_GUID \
+ {0x3d995fb4, 0x4f05, 0x4073, 0xbe, 0x72, 0xa1, 0x9c, 0xfb, 0x5d, 0xe6, 0x90}
+
+#define ALERT_STANDARD_FORMAT_VARIABLE_NAME (L"ASF")
+#define ASCII_ALERT_STANDARD_FORMAT_VARIABLE_NAME ("ASF")
+
+extern EFI_GUID gAlertStandardFormatGuid;
+extern CHAR16 gAlertStandardFormatName[];
+
+typedef struct {
+ UINT8 SmbusAddr;
+ struct {
+ UINT32 VendorSpecificId;
+ UINT16 SubsystemDeviceId;
+ UINT16 SubsystemVendorId;
+ UINT16 Interface;
+ UINT16 DeviceId;
+ UINT16 VendorId;
+ UINT8 VendorRevision;
+ UINT8 DeviceCapabilities;
+ } Udid;
+ struct {
+ UINT8 SubCommand;
+ UINT8 Version;
+ UINT32 IanaId;
+ UINT8 SpecialCommand;
+ UINT16 SpecialCommandParam;
+ UINT16 BootOptionsBits;
+ UINT16 OemParam;
+ } AsfBootOptions;
+ struct {
+ UINT8 Bus;
+ UINT8 Device;
+ UINT8 Function;
+ UINT16 VendorId;
+ UINT16 DeviceId;
+ UINT16 IderCmdBar;
+ UINT16 IderCtrlBar;
+ UINT8 IderIrq;
+ UINT16 SolBar;
+ UINT8 SolIrq;
+ } PciInfo;
+ struct {
+ UINT8 IamtProvisioningStatus;
+ BOOLEAN IamtIsProvisioned;
+ } IamtInfo;
+ struct {
+ BOOLEAN FlashUpdatingIsAllowed;
+ } MeInfoForEbu;
+ UINT32 EitBPFAddress;
+} EFI_ASF_VARIABLE;
+
+#pragma pack()
+
+#endif
+
diff --git a/Vlv2TbltDevicePkg/Include/Guid/BiosId.h b/Vlv2TbltDevicePkg/Include/Guid/BiosId.h
new file mode 100644
index 0000000000..15914b883e
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/BiosId.h
@@ -0,0 +1,35 @@
+/*++
+
+Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ BiosId.h
+
+Abstract:
+
+ GUIDs used for Bios ID.
+
+--*/
+
+#ifndef _BIOS_ID_H_
+#define _BIOS_ID_H_
+
+
+#define EFI_BIOS_ID_GUID \
+{ 0xC3E36D09, 0x8294, 0x4b97, 0xA8, 0x57, 0xD5, 0x28, 0x8F, 0xE3, 0x3E, 0x28 }
+
+
+extern EFI_GUID gEfiBiosIdGuid;
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h b/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h
new file mode 100644
index 0000000000..11bb98bb74
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/BoardFeatures.h
@@ -0,0 +1,219 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ BoardFeatures.h
+
+Abstract:
+
+ EFI Platform Board Features
+
+
+
+--*/
+
+#ifndef BoardFeatures_h_included
+#define BoardFeatures_h_included
+
+#include <Base.h>
+
+#pragma pack(1)
+
+//
+// Board Features
+//
+#if defined LEGACY_BOARD_FEATURES && LEGACY_BOARD_FEATURES
+#define B_BOARD_FEATURES_CHIPSET_LAN BIT0
+#define B_BOARD_FEATURES_LAN_MARVELL BIT1
+#define B_BOARD_FEATURES_AA_NOT_FOUND BIT2
+#define B_BOARD_FEATURES_SIO_NO_COM1 BIT3
+#define B_BOARD_FEATURES_SIO_COM2 BIT4
+#define B_BOARD_FEATURES_SIO_NO_PARALLEL BIT5
+#define B_BOARD_FEATURES_CHIPSET_VIDEO BIT6
+#define B_BOARD_FEATURES_CHIPSET_VIDEO_OPTION0 BIT7
+#define B_BOARD_FEATURES_VIDEO_SLOT BIT8
+#define B_BOARD_FEATURES_MINI_CARD BIT9
+#define B_BOARD_FEATURES_DISCRETE_1394 BIT10
+#define B_BOARD_FEATURES_LEGACY_FREE BIT11
+#define B_BOARD_FEATURES_USB_HUB BIT12
+#define B_BOARD_FEATURES_TPM BIT13
+#define B_BOARD_FEATURES_VIIV BIT14
+#define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19)
+#define B_BOARD_FEATURES_FORM_FACTOR_PBTX BIT15
+#define B_BOARD_FEATURES_FORM_FACTOR_ATX BIT16
+#define B_BOARD_FEATURES_FORM_FACTOR_BTX BIT17
+#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX BIT18
+#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
+#define B_BOARD_FEATURES_MEMORY_TYPE_DDR1 BIT20
+#define B_BOARD_FEATURES_MEMORY_TYPE_DDR2 BIT21
+#define B_BOARD_FEATURES_MEMORY_SLOT_MASK BIT23 | BIT22
+#define V_BOARD_FEATURES_1_MEMORY_SLOT 0 // BIT22=0, BIT23=0
+#define V_BOARD_FEATURES_2_MEMORY_SLOT BIT22 // BIT22=1, BIT23=0
+#define V_BOARD_FEATURES_3_MEMORY_SLOT BIT23 // BIT22=0, BIT23=1
+#define V_BOARD_FEATURES_4_MEMORY_SLOT BIT23 | BIT22 // BIT22=1, BIT23=1
+#define B_BOARD_FEATURES_ALT_MEM_CLK_RT BIT24
+#define B_BOARD_FEATURES_SLEEP_MASK BIT25
+#define V_BOARD_FEATURES_SLEEP_S1 0 // BIT25=0
+#define V_BOARD_FEATURES_SLEEP_S3 BIT25 // BIT25=1
+#define B_BOARD_FEATURES_3JACK_AUDIO_SOLUTION BIT26 // 0/1= 5/3 Rear Jacks
+#define B_BOARD_FEATURES_DISCRETE_SATA BIT27
+#define B_BOARD_FEATURES_2_SATA BIT28 // 2SATA instead of 4(pre Ich8) or 4 SATA instead of 6(Ich8)
+#define B_BOARD_FEATURES_RVP BIT29 // Board is an RVP board
+#define B_BOARD_FEATURES_PORT80_LPC BIT30 // Port80 PCI(0) or LPC(1)
+#define B_BOARD_FEATURES_LIMITED_CPU_SUPPORT BIT31 // Limited CPU support
+#define B_BOARD_FEATURES_PMP_SUPPORT BIT32 // Support for over-voltaging memory
+#define B_BOARD_FEATURES_HW_WATCHDOG_TIMER BIT33 // Support for the HW-based 555 Watchdog Timer feature
+#define B_BOARD_FEATURES_NO_QRT BIT34 // disable QRT
+#define B_BOARD_FEATURES_VERB_TABLE1 BIT35 // Verb table 1
+#define B_BOARD_FEATURES_VERB_TABLE2 BIT36 // Verb table 2
+#define B_BOARD_FEATURES_VERB_TABLE3 BIT37 // Verb table 3
+#define B_BOARD_FEATURES_VERB_TABLE4 BIT38 // Verb table 4
+#define B_BOARD_FEATURES_VERB_TABLE5 BIT39 // Reserved for Verb table 5
+#define B_BOARD_FEATURES_VERB_TABLE_MASK BIT35 | BIT36 | BIT37 | BIT38 | BIT39
+#define B_BOARD_FEATURES_KENTSFIELD_BLOCK BIT40 // Kentsfield not supported
+#define B_BOARD_FEATURES_KENTSFIELD_WARNING BIT41 // Kentsfield warning
+#define B_BOARD_FEATURES_ESATA_PORT0 BIT42 // E-SATA on Port0
+#define B_BOARD_FEATURES_ESATA_PORT1 BIT43 // E-SATA on Port1
+#define B_BOARD_FEATURES_ESATA_PORT2 BIT44 // E-SATA on Port2
+#define B_BOARD_FEATURES_ESATA_PORT3 BIT45 // E-SATA on Port3
+#define B_BOARD_FEATURES_ESATA_PORT4 BIT46 // E-SATA on Port4
+#define B_BOARD_FEATURES_ESATA_PORT5 BIT47 // E-SATA on Port5
+#define B_BOARD_FEATURES_ECIR BIT48 // Enhanced Consumer IR
+#define B_BOARD_FEATURES_PS2WAKEFROMS5 BIT49 // Wake from S5 via PS2 keyboard
+#define B_BOARD_FEATURES_HDAUDIOLINK BIT50 // HD audio link support
+#define B_BOARD_FEATURES_1_PATA BIT51
+#define B_BOARD_FEATURES_MOBILE BIT52
+#define B_BOARD_FEATURES_NO_FLOPPY BIT53
+#define B_BOARD_FEATURES_DISABLE_UNUSED_FSB BIT54
+
+//
+// Bit 55-58 reserved by PSID support. CPU power requirement below are preliminary.
+// They might be changed.
+// This is not same as 8.6.1 products so be careful.
+//
+#define B_BOARD_FEATURES_CPU_POWER_BITNUM 55
+#define B_BOARD_FEATURES_CPU_POWER_MASK (BIT55 | BIT56 | BIT57 | BIT58)
+#define B_BOARD_FEATURES_CPU_POWER_35W 0 // Theoretically doesn't exist.
+#define B_BOARD_FEATURES_CPU_POWER_40W BIT55 // 0001
+#define B_BOARD_FEATURES_CPU_POWER_45W BIT56 // 0010
+#define B_BOARD_FEATURES_CPU_POWER_50W (BIT55 | BIT56) // 0011
+#define B_BOARD_FEATURES_CPU_POWER_65W BIT57 // 0100 Wolfdale-H/-M
+#define B_BOARD_FEATURES_CPU_POWER_70W (BIT55 | BIT57) // 0101
+#define B_BOARD_FEATURES_CPU_POWER_75W (BIT56 | BIT57) // 0110
+#define B_BOARD_FEATURES_CPU_POWER_80W (BIT55 | BIT56 | BIT57) // 0111
+#define B_BOARD_FEATURES_CPU_POWER_95W BIT58 // 1000 Yorkfield
+#define B_BOARD_FEATURES_CPU_POWER_100W (BIT55 | BIT58) // 1001
+#define B_BOARD_FEATURES_CPU_POWER_105W (BIT56 | BIT58) // 1010
+#define B_BOARD_FEATURES_CPU_POWER_110W (BIT55 | BIT56 | BIT58) // 1011
+#define B_BOARD_FEATURES_CPU_POWER_130W (BIT57 | BIT58) // 1100 XE Yorkfield
+#define B_BOARD_FEATURES_CPU_POWER_135W (BIT55 | BIT57 | BIT58) // 1101
+#define B_BOARD_FEATURES_CPU_POWER_Over135W (BIT56 | BIT57 | BIT58) // 1110 Reserved
+#define B_BOARD_FEATURES_CPU_POWER_140W (BIT55 | BIT56 | BIT57 | BIT58) // 1111 Reserved
+#define B_VV_BOARD_FEATURES BIT59
+#define B_BOARD_FEATURES_IDCC2_SUPPORT BIT60 // Include IDCC2 support
+#define B_BOARD_FEATURES_NO_SATA_PORT2_3 BIT61 // No SATA Port2&3 Connector, used with B_BOARD_FEATURES_2_SATA flag
+#define B_BOARD_FEATURES_FORM_FACTOR_MINI_ITX BIT62
+#define B_BOARD_FEATURES_NPI_QPI_VOLTAGE BIT63
+
+#else
+
+#define B_BOARD_FEATURES_CHIPSET_LAN BIT0
+#define B_BOARD_FEATURES_CHIPSET_VIDEO BIT1
+#define B_BOARD_FEATURES_VIDEO_SLOT BIT2
+#define B_BOARD_FEATURES_AA_NOT_FOUND BIT3
+#define B_BOARD_FEATURES_SIO_NO_COM1 BIT4
+#define B_BOARD_FEATURES_SIO_COM2 BIT5
+#define B_BOARD_FEATURES_SIO_NO_PARALLEL BIT6
+#define B_BOARD_FEATURES_NO_FLOPPY BIT7
+#define B_BOARD_FEATURES_PS2WAKEFROMS5 BIT8 // Wake from S5 via PS2 keyboard
+#define B_BOARD_FEATURES_ECIR BIT9 // Enhanced Consumer IR
+#define B_BOARD_FEATURES_LEGACY_FREE BIT10
+#define B_BOARD_FEATURES_MINI_CARD BIT11
+#define B_BOARD_FEATURES_DISCRETE_1394 BIT12
+#define B_BOARD_FEATURES_USB_HUB BIT13
+#define B_BOARD_FEATURES_TPM BIT14
+#define B_BOARD_FEATURES_FORM_FACTOR_MASK (BIT15|BIT16|BIT17|BIT18|BIT19|BIT20)
+#define B_BOARD_FEATURES_FORM_FACTOR_PBTX BIT15
+#define B_BOARD_FEATURES_FORM_FACTOR_ATX BIT16
+#define B_BOARD_FEATURES_FORM_FACTOR_BTX BIT17
+#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_ATX BIT18
+#define B_BOARD_FEATURES_FORM_FACTOR_MICRO_BTX BIT19
+#define B_BOARD_FEATURES_FORM_FACTOR_MINI_ITX BIT20
+#define B_BOARD_FEATURES_MEMORY_TYPE_DDR2 BIT21
+#define B_BOARD_FEATURES_MEMORY_TYPE_DDR3 BIT22
+#define B_BOARD_FEATURES_MEMORY_SLOT_MASK (BIT24 | BIT23)
+#define V_BOARD_FEATURES_1_MEMORY_SLOT 0 // BIT23=0, BIT24=0
+#define V_BOARD_FEATURES_2_MEMORY_SLOT BIT23 // BIT23=1, BIT24=0
+#define V_BOARD_FEATURES_3_MEMORY_SLOT BIT24 // BIT23=0, BIT24=1
+#define V_BOARD_FEATURES_4_MEMORY_SLOT (BIT24 | BIT23) // BIT23=1, BIT24=1
+#define B_BOARD_FEATURES_2_C0_MEMORY_SLOT BIT25 // 2 Channel 0 memory slot
+#define B_BOARD_FEATURES_SLEEP_MASK BIT26
+#define V_BOARD_FEATURES_SLEEP_S1 0 // BIT26=0
+#define V_BOARD_FEATURES_SLEEP_S3 BIT26 // BIT26=1
+#define B_BOARD_FEATURES_3JACK_AUDIO_SOLUTION BIT27 // 0/1= 5/3 Rear Jacks
+#define B_BOARD_FEATURES_HDAUDIOLINK BIT28 // HD audio link support
+#define B_BOARD_FEATURES_DISCRETE_SATA BIT29
+#define B_BOARD_FEATURES_2_SATA BIT30 // 2SATA instead of 4(pre Ich8) or 4 SATA instead of 6(Ich8)
+#define B_BOARD_FEATURES_NO_SATA_PORT2_3 BIT31 // No SATA Port2&3 Connector, used with B_BOARD_FEATURES_2_SATA flag
+#define B_BOARD_FEATURES_RVP BIT32 // Board is an RVP board
+#define B_BOARD_FEATURES_ESATA_PORT0 BIT33 // E-SATA on Port0
+#define B_BOARD_FEATURES_ESATA_PORT1 BIT34 // E-SATA on Port1
+#define B_BOARD_FEATURES_ESATA_PORT2 BIT35 // E-SATA on Port2
+#define B_BOARD_FEATURES_ESATA_PORT3 BIT36 // E-SATA on Port3
+#define B_BOARD_FEATURES_ESATA_PORT4 BIT37 // E-SATA on Port4
+#define B_BOARD_FEATURES_ESATA_PORT5 BIT38 // E-SATA on Port5
+#define B_BOARD_FEATURES_IDCC2_SUPPORT BIT39 // Include IDCC2 support
+#define B_BOARD_FEATURES_NPI_QPI_VOLTAGE BIT40
+#define B_BOARD_FEATURES_LIMITED_CPU_SUPPORT BIT41 // Limited CPU support
+#define B_BOARD_FEATURES_PMP_SUPPORT BIT42 // Support for over-voltaging memory
+#define B_BOARD_FEATURES_HW_WATCHDOG_TIMER BIT43 // Support for the HW-based 555 Watchdog Timer feature
+#define B_BOARD_FEATURES_LVDS BIT44 // Support for LVDS
+#define B_BOARD_FEATURES_VERB_TABLE_MASK (BIT45|BIT46|BIT47|BIT48) // Verb table
+#define B_BOARD_FEATURES_VERB_TABLE1 BIT45 // Verb table 1
+#define B_BOARD_FEATURES_VERB_TABLE2 BIT46 // Verb table 2
+#define B_BOARD_FEATURES_VERB_TABLE3 BIT47 // Verb table 3
+#define B_BOARD_FEATURES_VERB_TABLE4 BIT48 // Verb table 4
+#define B_BOARD_FEATURES_NO_MINIPCIE BIT49 // Mini PCIe slot
+#define B_BOARD_FEATURES_HDMI_SLOT BIT50 // HDMI slot
+#define B_BOARD_FEATURES_PS2_HIDE BIT51 // PS2 hide
+#define B_BOARD_FEATURES_DVID_SLOT BIT52 // DVID slot
+
+#define B_BOARD_FEATURES_SIO_COM3 BIT53
+#define B_BOARD_FEATURES_SIO_COM4 BIT54
+
+#define B_BOARD_FEATURES_LAN2 BIT55
+#define B_BOARD_FEATURES_PCIe_SLOT BIT56
+#endif
+
+typedef UINT64 EFI_BOARD_FEATURES;
+
+#pragma pack()
+
+//
+// Global ID for the Platform Boot Mode Protocol.
+//
+#define EFI_BOARD_FEATURES_GUID \
+ { 0x94b9e8ae, 0x8877, 0x479a, 0x98, 0x42, 0xf5, 0x97, 0x4b, 0x82, 0xce, 0xd3 }
+
+extern EFI_GUID gEfiBoardFeaturesGuid;
+
+#define BOARD_FEATURES_NAME L"BoardFeatures"
+
+#define EFI_BOARD_ID_GUID \
+ { 0x6b2dd245, 0x3f2, 0x414a, 0x8c, 0x2, 0x9f, 0xfc, 0x23, 0x52, 0xe3, 0x1e }
+#define EFI_BOARD_ID_NAME (L"BoardId")
+
+#endif
+
diff --git a/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h b/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h
new file mode 100644
index 0000000000..31fa3e0511
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/EfiVpdData.h
@@ -0,0 +1,161 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ EfiVpdData.h
+
+Abstract:
+
+ Constants and declarations that are common accross PEI and DXE.
+--*/
+
+#ifndef _EFI_VPD_DATA_H_
+#define _EFI_VPD_DATA_H_
+
+
+#pragma pack(1)
+
+//
+// DMI data
+//
+typedef struct {
+
+ CHAR8 DmiGpnvHeader[4]; // $DMI
+ CHAR8 SystemInfoManufacturer[0x20]; // Structure Type 1 String 1
+ CHAR8 SystemInfoProductName[0x20]; // Structure Type 1 String 2
+ CHAR8 SystemInfoVersion[0x18]; // Structure Type 1 String 3
+ CHAR8 SystemInfoSerialNumber[0x20]; // Structure Type 1 String 4
+ CHAR8 BaseBoardManufacturer[0x20]; // Structure Type 2 String 1
+ CHAR8 BaseBoardProductName[0x20]; // Structure Type 2 String 2
+ CHAR8 BaseBoardVersion[0x18]; // Structure Type 2 String 3
+ CHAR8 BaseBoardSerialNumber[0x20]; // Structure Type 2 String 4
+ CHAR8 ChassisManufacturer[0x20]; // Structure Type 3 String 1
+ UINT8 ChassisType; // Enumerated
+ CHAR8 ChassisVersion[0x18]; // Structure Type 3 String 2
+ CHAR8 ChassisSerialNumber[0x20]; // Structure Type 3 String 3
+ CHAR8 ChassisAssetTag[0x20]; // Structure Type 3 String 4
+ UINT8 MfgAccessKeyWorkspace;
+
+ UINT8 ChecksumFixupPool[0xd]; // Checksum Fix-ups
+ UINT8 SwitchboardData[4]; // 32 switch switchboard
+ UINT8 IntelReserved; // Reserved for Future Use
+} DMI_DATA;
+
+#define DMI_DATA_GUID \
+ { \
+ 0x70e56c5e, 0x280c, 0x44b0, 0xa4, 0x97, 0x09, 0x68, 0x1a, 0xbc, 0x37, 0x5e \
+ }
+
+#define DMI_DATA_NAME (L"DmiData")
+#define ASCII_DMI_DATA_NAME ("DmiData")
+
+extern EFI_GUID gDmiDataGuid;
+extern CHAR16 gDmiDataName[];
+
+//
+// UUID - universally unique system id.
+//
+#define UUID_VARIABLE_GUID \
+ { \
+ 0xd357c710, 0x0ada, 0x4717, 0x8d, 0xba, 0xc6, 0xad, 0xc7, 0xcd, 0x2b, 0x2a \
+ }
+
+#define UUID_VARIABLE_NAME (L"UUID")
+#define ASCII_UUID_VARIABLE_NAME ("UUID")
+
+//
+// UUID data
+//
+typedef struct {
+ UINT32 UuidHigh;
+ UINT32 UuidLow;
+} SYSTEM_1394_UUID;
+
+typedef struct {
+ EFI_GUID SystemUuid; // System Unique ID
+ SYSTEM_1394_UUID System1394Uuid; // Onboard 1394 UUID
+} UUID_DATA;
+
+extern EFI_GUID gUuidVariableGuid;
+extern CHAR16 gUuidVariableName[];
+
+//
+// MB32GUID for Computrace.
+//
+
+#define MB32_GUID \
+ { 0x539D62BA, 0xDE35, 0x453E, 0xBA, 0xB0, 0x85, 0xDB, 0x8D, 0xA2, 0x42, 0xF9 }
+
+#define MB32_VARIABLE_NAME (L"MB32")
+#define ASCII_MB32_VARIABLE_NAME ("MB32")
+
+extern EFI_GUID gMb32Guid;
+extern CHAR16 gMb32VariableName[];
+
+//
+// ACPI OSFR Manufacturer String.
+//
+// {72234213-0FD7-48a1-A59F-B41BC107FBCD}
+//
+#define ACPI_OSFR_MFG_STRING_VARIABLE_GUID \
+ {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd}
+#define ACPI_OSFR_MFG_STRING_VARIABLE_NAME (L"OcurMfg")
+#define ASCII_ACPI_OSFR_MF_STRING_VARIABLE_NAME ("OcurMfg")
+
+extern EFI_GUID gACPIOSFRMfgStringVariableGuid;
+
+
+//
+// ACPI OSFR Model String.
+//
+// {72234213-0FD7-48a1-A59F-B41BC107FBCD}
+//
+#define ACPI_OSFR_MODEL_STRING_VARIABLE_GUID \
+ {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd}
+#define ACPI_OSFR_MODEL_STRING_VARIABLE_NAME (L"OcurModel")
+#define ASCII_ACPI_OSFR_MODEL_STRING_VARIABLE_NAME ("OcurModel")
+
+extern EFI_GUID gACPIOSFRModelStringVariableGuid;
+
+//
+// ACPI OSFR Reference Data Block.
+//
+// {72234213-0FD7-48a1-A59F-B41BC107FBCD}
+//
+#define ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_GUID \
+ {0x72234213, 0xfd7, 0x48a1, 0xa5, 0x9f, 0xb4, 0x1b, 0xc1, 0x7, 0xfb, 0xcd}
+#define ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_NAME (L"OcurRef")
+#define ASCII_ACPI_OSFR_REF_DATA_BLOCK_VARIABLE_NAME ("OcurRef")
+extern EFI_GUID gACPIOSFRRefDataBlockVariableGuid;
+
+//
+// Manufacturing mode GUID
+//
+#define MfgMode_GUID \
+ { 0xEF14FD78, 0x0793, 0x4e2b, 0xAC, 0x6D, 0x06, 0x28, 0x47, 0xE0, 0x17, 0x91 }
+
+#define MFGMODE_VARIABLE_NAME (L"MfgMode")
+#define ASCII_MFGMODE_VARIABLE_NAME ("MfgMode")
+
+typedef struct {
+ UINT8 MfgModeData;
+} MFG_MODE_VAR;
+
+extern EFI_GUID gMfgModeVariableGuid;
+extern CHAR16 gMfgModeVariableName[];
+
+#pragma pack()
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h b/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h
new file mode 100644
index 0000000000..061ded0f7a
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/FirmwareId.h
@@ -0,0 +1,66 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ FirmwareId.h
+
+--*/
+
+#ifndef _FirmwareId_h_GUID_included
+#define _FirmwareId_h_GUID_included
+
+
+#pragma pack(1)
+
+//
+// Firmware ID
+//
+
+#define FIRMWARE_ID_MAX_LENGTH 35
+
+typedef struct {
+ CHAR8 BiosId[8];
+ CHAR8 Separator1;
+ CHAR8 OemId[3];
+ CHAR8 Separator2;
+ CHAR8 BuildId[4];
+ CHAR8 Separator3;
+ CHAR8 Century[2];
+ CHAR8 Year[2];
+ CHAR8 Separator4;
+ CHAR8 Month[2];
+ CHAR8 Date[2];
+ CHAR8 Separator5;
+ CHAR8 Hour[2];
+ CHAR8 Minute[2];
+ CHAR8 Dummy[3];
+} FIRMWARE_ID_DATA;
+
+#define OLD_FIRMWARE_ID_GUID \
+ {0xefc071ae, 0x41b8, 0x4018, 0xaf, 0xa7, 0x31, 0x4b, 0x18, 0x5e, 0x57, 0x8b}
+
+#define FIRMWARE_ID_GUID \
+ {0x5e559c23, 0x1faa, 0x4ae1, 0x8d, 0x4a, 0xc6, 0xcf, 0x02, 0x6c, 0x76, 0x6f}
+
+#define FIRMWARE_ID_NAME L"FirmwareId"
+#define FIRMWARE_ID_NAME_WITH_PASSWORD FIRMWARE_ID_NAME L"H#8,^-!t"
+
+extern EFI_GUID gFirmwareIdGuid;
+extern CHAR16 gFirmwareIdName[];
+
+#pragma pack()
+
+#endif
+
diff --git a/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h b/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h
new file mode 100644
index 0000000000..cfb2228e2c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/HwWatchdogTimerHob.h
@@ -0,0 +1,139 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ HwWatchdogTimerHob.h
+
+Abstract:
+
+ GUID used for Watchdog Timer status in the HOB list.
+
+--*/
+
+#ifndef _EFI_WATCHDOG_TIMER_HOB_GUID_H_
+#define _EFI_WATCHDOG_TIMER_HOB_GUID_H_
+
+#define EFI_WATCHDOG_TIMER_HOB_GUID \
+ { 0x226cd3f, 0x69b5, 0x4150, 0xac, 0xbe, 0xbf, 0xbf, 0x18, 0xe3, 0x3, 0xd5 }
+
+#define EFI_WATCHDOG_TIMER_DEFINITION_HOB_GUID \
+ { 0xd29302b0, 0x11ba, 0x4073, 0xa2, 0x27, 0x53, 0x8d, 0x25, 0x42, 0x70, 0x9f }
+
+typedef enum {
+ HWWD_NONE,
+ HWWD_TIMER_EXPIRED,
+ HWWD_SPONTANEOUS_REBOOT,
+ HWWD_FORCED_TIMEOUT
+} HW_WATCHDOG_TIMEOUT;
+
+typedef struct {
+ HW_WATCHDOG_TIMEOUT TimeoutStatus;
+} HW_WATCHDOG_INFO;
+
+//
+// Watchdog timer action values.
+//
+#define WDT_ACTION_RESET 0x01 // reload/reset timer
+#define WDT_ACTION_QUERY_CURRENT_VALUE 0x04 // get current value // DON'T NEED FOR OVERCLOCK UTILITY
+#define WDT_ACTION_QUERY_COUNTDOWN_PERIOD 0x05 // get countdown period
+#define WDT_ACTION_SET_COUNTDOWN_PERIOD 0x06 // set countdown period
+#define WDT_ACTION_QUERY_RUNNING_STATE 0x08 // query if running
+#define WDT_ACTION_SET_RUNNING_STATE 0x09 // start timer
+#define WDT_ACTION_QUERY_STOPPED_STATE 0x0A // query if stopped
+#define WDT_ACTION_SET_STOPPED_STATE 0x0B // stop timer
+#define WDT_ACTION_QUERY_STATUS 0x20 // is current boot cause by wdt timeout?
+#define WDT_ACTION_SET_STATUS 0x21 // resets wdt status bit
+
+//
+// Watchdog timer instruction values.
+//
+#define WDT_INSTR_VALUE_MASK 0x03 // Mask for just the value
+#define WDT_INSTR_READ_CMP_VALUE 0x00 // Read / compare value
+#define WDT_INSTR_READ_COUNTDOWN 0x01 // read countdown value
+#define WDT_INSTR_WRITE_VALUE 0x02 // Write value
+#define WDT_INSTR_WRITE_COUNTDOWN 0x03 // write countdown value
+#define WDT_INSTR_PRESERVE_REG 0x80 // preserve reg; used in Write Value / Write Countdown
+#define WDT_INSTR_WRITE_VALUE_PRES (0x02 | WDT_INSTR_PRESERVE_REG) // Write value with preserve
+#define WDT_INSTR_WRITE_COUNTDOWN_PRES (0x03 | WDT_INSTR_PRESERVE_REG) // write countdown value with preserve
+
+//
+// The Generic Address Structure is defined in the ACPI Specification and should only be
+// changed to match updated revisions of that specification. The GAS_ADDRESS_SPACE and
+// GAS_ACCESS_SIZE enumerations are also defined by the ACPI Specification.
+//
+typedef enum {
+ GAS_SYSTEM_MEMORY,
+ GAS_SYSTEM_IO,
+ GAS_PCI_CONFIG_SPACE,
+ GAS_EMBEDDED_CONTROLLER,
+ GAS_SMBUS
+} GAS_ADDRESS_SPACE;
+
+typedef enum {
+ GAS_UNDEFINED,
+ GAS_BYTE_ACCESS,
+ GAS_WORD_ACCESS,
+ GAS_DWORD_ACCESS,
+ GAS_QWORD_ACCESS
+} GAS_ACCESS_SIZE;
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 AddressSpaceId;
+ UINT8 RegisterBitWidth;
+ UINT8 RegisterBitOffset;
+ UINT8 AccessSize;
+ UINT64 Address;
+} GENERIC_ADDRESS_STRUCTURE;
+
+//
+// GAS_SYSTEM_MEMORY - When used as the AddressSpaceId, the 64-bit physical memory address
+// of the register. 32-bit platforms must have the high DWORD set to 0.
+// GAS_SYSTEM_IO - The 64-bit I/O address of the register. 32-bit platforms must have
+// the high DWORD set to 0.
+// GAS_PCI_CONFIG_SPACE - PCI Configuration space addresses must be confined to devices on PCI
+// Sepment Group 0, Bus 0. This restriction exists to accommodate access
+// to fixed hardware prior to PCI bus enumeration. The format of addresses
+// are defined as follows:
+// Highest WORD: Reserved and must be -0-
+// ... PCI Device number on bus 0
+// ... PCI Function number
+// Lowest WORD: Offset in the configuration space header.
+//
+
+typedef struct {
+ UINT8 WdAction;
+ UINT8 Flag;
+ UINT16 Res;
+ GENERIC_ADDRESS_STRUCTURE GenericAddressStructures;
+ UINT32 Value;
+ UINT32 Mask;
+} WD_INSTRUCTION;
+
+typedef struct {
+ UINT32 TimerPeriod;
+ UINT32 MaxTimerCount;
+ UINT32 MinTimerCount;
+ UINT16 InstructionCount;
+ WD_INSTRUCTION ActionDefinitions[1];
+} WD_HOB_DEFINITION;
+
+#pragma pack()
+
+extern EFI_GUID gWatchdogTimerHobGuid;
+extern EFI_GUID gWatchdogTimerDefinitionHobGuid;
+
+#endif // _EFI_WATCHDOG_TIMER_HOB_GUID_H_
diff --git a/Vlv2TbltDevicePkg/Include/Guid/IdccData.h b/Vlv2TbltDevicePkg/Include/Guid/IdccData.h
new file mode 100644
index 0000000000..fa8988b364
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/IdccData.h
@@ -0,0 +1,109 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ IdccData.h
+
+Abstract:
+
+--*/
+
+#ifndef _IDCCDATAHUB_GUID_H_
+#define _IDCCDATAHUB_GUID_H_
+
+//
+// This GUID is for the IDCC related data found in the Data Hub.
+//
+#define IDCC_DATA_HUB_GUID \
+ { 0x788e1d9f, 0x1eab, 0x47d2, 0xa2, 0xf3, 0x78, 0xca, 0xe8, 0x7d, 0x60, 0x12 }
+
+extern EFI_GUID gIdccDataHubGuid;
+
+#pragma pack(1)
+
+typedef struct {
+ UINT32 Type;
+ UINT32 RecordLength;
+} EFI_IDCC_DATA_HEADER;
+
+typedef struct {
+ EFI_IDCC_DATA_HEADER IdccHeader;
+ UINT32 Tcontrol;
+} EFI_IDCC_TCONTROL;
+
+typedef struct {
+ UINT32 EntryCount;
+} EFI_IDCC_CLOCK_COMMON;
+
+typedef struct {
+ UINT8 Polarity;
+ UINT8 Percent;
+ UINT32 FpValue;
+} EFI_IDCC_TYPE_2_DATA;
+
+typedef struct {
+ UINT8 SetupVal;
+ UINT32 FpValue;
+} EFI_IDCC_TYPE_3_4_DATA;
+
+typedef struct {
+ EFI_IDCC_DATA_HEADER IdccHeader;
+ UINT32 ProcessorRatio;
+} EFI_IDCC_PROCESSOR_RATIO;
+
+typedef struct {
+ EFI_IDCC_DATA_HEADER IdccHeader;
+ UINT32 BoardFormFactor;
+} EFI_IDCC_BOARD_FORM_FACTOR;
+
+typedef struct {
+ EFI_IDCC_DATA_HEADER IdccHeader;
+ UINT32 ProcessorInfo;
+} EFI_IDCC_PROCESSOR_INFO;
+
+#define EFI_IDCC_PROCESSOR_UNCON (1 << 0) // Bit 0: UnCon CPU
+#define EFI_IDCC_PROCESSOR_UNLOCK (1 << 1) // Bit 1: UnLock CPU
+#define EFI_IDCC_PROCESSOR_CNR (1 << 2) // Bit 2: CNR CPU
+#define EFI_IDCC_PROCESSOR_KNF (1 << 3) // Bit 3: KNF CPU
+
+typedef struct {
+ EFI_IDCC_DATA_HEADER IdccHeader;
+ UINT32 MinFSB;
+ UINT32 MaxFSB;
+ UINT8 StepFSB;
+} EFI_IDCC_FSB_DATA;
+
+#pragma pack()
+
+#define EFI_IDCC_POSITIVE 0
+#define EFI_IDCC_NEGATIVE 1
+
+//
+// Board Form Factor equates.
+//
+#define ATX_FORM_FACTOR 0x00
+#define BTX_FORM_FACTOR 0x01
+
+
+#define EFI_IDCC_TCONTROL_TYPE 1
+#define EFI_IDCC_FSB_TYPE 2
+#define EFI_IDCC_PCI_TYPE 3
+#define EFI_IDCC_PCIE_TYPE 4
+#define EFI_IDCC_PROC_RATIO_TYPE 5
+#define EFI_IDCC_BOARD_FORM_FACTOR_TYPE 6
+#define EFI_IDCC_PROC_INFO_TYPE 7
+#define EFI_IDCC_FSB_DATA_TYPE 8
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Include/Guid/ItkData.h b/Vlv2TbltDevicePkg/Include/Guid/ItkData.h
new file mode 100644
index 0000000000..3e02fd49cc
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/ItkData.h
@@ -0,0 +1,75 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+Module Name:
+
+ ItkData.h
+
+Abstract:
+
+--*/
+
+#ifndef _ITKDATAHUB_GUID_H_
+#define _ITKDATAHUB_GUID_H_
+
+//
+// This GUID is for the ITK related data found in the Data Hub {E7060843-A336-4d5b-9598-13402F5D7375}
+//
+#define ITK_DATA_HUB_GUID \
+ { 0xe7060843, 0xa336, 0x4d5b, 0x95, 0x98, 0x13, 0x40, 0x2f, 0x5d, 0x73, 0x75 }
+
+extern EFI_GUID gItkDataHubGuid;
+
+//
+// This GUID is for the ITK related data found in a Variable {3812723D-7E48-4e29-BC27-F5A39AC94EF1}
+//
+#define ITK_DATA_VAR_GUID \
+ { 0x3812723d, 0x7e48, 0x4e29, 0xbc, 0x27, 0xf5, 0xa3, 0x9a, 0xc9, 0x4e, 0xf1 }
+
+extern EFI_GUID gItkDataVarGuid;
+
+#define ITK_DATA_VAR_NAME L"ItkDataVar"
+
+extern CHAR16 gItkDataVarName[];
+
+#define ITK_BIOS_MOD_VAR_NAME L"ItkBiosModVar"
+
+extern CHAR16 gItkBiosModVarName[];
+
+#pragma pack(1)
+typedef struct {
+ UINT32 Type;
+ UINT32 RecordLength;
+} EFI_ITK_DATA_HEADER;
+
+typedef struct {
+ EFI_ITK_DATA_HEADER ItkHeader;
+ UINT32 HecetaAddress;
+} EFI_ITK_HECETA_ADDRESS;
+
+typedef struct {
+ UINT16 VarEqName;
+ UINT16 VarEqValue;
+} EFI_ITK_VAR_EQ_RECORD;
+
+typedef struct {
+ EFI_ITK_DATA_HEADER ItkHeader;
+ EFI_ITK_VAR_EQ_RECORD VarEqRecord[0x10000];
+} EFI_ITK_VAR_EQ;
+#pragma pack()
+
+#define EFI_ITK_HECETA_ADDRESS_TYPE 1
+#define EFI_ITK_MOBILE_BIOS_TYPE 2
+#define EFI_ITK_VAR_EQ_TYPE 3
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h b/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h
new file mode 100644
index 0000000000..6780b3f924
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/MemoryConfigData.h
@@ -0,0 +1,37 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+
+Module Name:
+
+ MemoryConfigData.h
+
+Abstract:
+
+ GUID used for Memory Configuration Data entries in the HOB list.
+
+--*/
+
+#ifndef _MEMORY_CONFIG_DATA_GUID_H_
+#define _MEMORY_CONFIG_DATA_GUID_H_
+
+#define EFI_MEMORY_CONFIG_DATA_GUID \
+ { \
+ 0x80dbd530, 0xb74c, 0x4f11, 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 \
+ }
+
+extern EFI_GUID gEfiMemoryConfigDataGuid;
+extern CHAR16 EfiMemoryConfigVariable[];
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h b/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h
new file mode 100644
index 0000000000..3e65ae659b
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/OsSelection.h
@@ -0,0 +1,90 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ OsSelection.h
+
+Abstract:
+
+ GUID used for LPSS, SCC and LPE configuration data entries in the HOB list.
+
+--*/
+
+#ifndef _OS_SELECTION_GUID_H_
+#define _OS_SELECTION_GUID_H_
+
+#ifndef ECP_FLAG
+#include <PiPei.h>
+
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#endif
+
+#define ANDROID 1
+
+#define EFI_OS_SELECTION_VARIABLE_GUID \
+ { \
+ 0x86843f56, 0x675d, 0x40a5, 0x95, 0x30, 0xbc, 0x85, 0x83, 0x72, 0xf1, 0x03 \
+ }
+
+extern EFI_GUID gOsSelectionVariableGuid;
+
+#pragma pack(1)
+
+typedef struct {
+ UINT8 LpssPciModeEnabled;
+ //SCC
+ UINT8 LpsseMMCEnabled;
+ UINT8 LpssSdioEnabled;
+ UINT8 LpssSdcardEnabled;
+ UINT8 LpssSdCardSDR25Enabled;
+ UINT8 LpssSdCardDDR50Enabled;
+ UINT8 LpssMipiHsi;
+ UINT8 LpsseMMC45Enabled;
+ UINT8 LpsseMMC45DDR50Enabled;
+ UINT8 LpsseMMC45HS200Enabled;
+ UINT8 LpsseMMC45RetuneTimerValue;
+ UINT8 eMMCBootMode;
+ //LPSS2
+ UINT8 LpssDma1Enabled;
+ UINT8 LpssI2C0Enabled;
+ UINT8 LpssI2C1Enabled;
+ UINT8 LpssI2C2Enabled;
+ UINT8 LpssI2C3Enabled;
+ UINT8 LpssI2C4Enabled;
+ UINT8 LpssI2C5Enabled;
+ UINT8 LpssI2C6Enabled;
+ //LPSS1
+ UINT8 LpssDma0Enabled;
+ UINT8 LpssPwm0Enabled;
+ UINT8 LpssPwm1Enabled;
+ UINT8 LpssHsuart0Enabled;
+ UINT8 LpssHsuart1Enabled;
+ UINT8 LpssSpiEnabled;
+ UINT8 I2CTouchAd;
+} EFI_PLATFORM_LPSS_DATA;
+
+typedef struct _EFI_OS_SELECTION_HOB {
+ UINT8 OsSelection;
+ UINT8 OsSelectionChanged;
+ UINT8 Lpe;
+ UINT8 PchAzalia;
+ EFI_PLATFORM_LPSS_DATA LpssData;
+} EFI_OS_SELECTION_HOB;
+
+#pragma pack()
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h b/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h
new file mode 100644
index 0000000000..775f71081c
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/PciLanInfo.h
@@ -0,0 +1,44 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ PciLanInfo.h
+
+Abstract:
+
+--*/
+
+#ifndef _PCI_LAN_INFO_GUID_H_
+#define _PCI_LAN_INFO_GUID_H_
+
+#pragma pack(1)
+
+//
+// structure used for Pci Lan variable
+//
+typedef struct {
+ UINT8 PciBus;
+ UINT8 PciDevice;
+ UINT8 PciFunction;
+} PCI_LAN_INFO;
+
+#pragma pack()
+
+#define EFI_PCI_LAN_INFO_GUID \
+ {0xd9a1427, 0xe02a, 0x437d, 0x92, 0x6b, 0xaa, 0x52, 0x1f, 0xd7, 0x22, 0xba};
+
+extern EFI_GUID gEfiPciLanInfoGuid;
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h b/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h
new file mode 100644
index 0000000000..ec9db67199
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/PlatformCpuInfo.h
@@ -0,0 +1,185 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+Module Name:
+
+ PlatformCpuInfo.h
+
+Abstract:
+
+ GUID used for Platform CPU Info Data entries in the HOB list.
+
+--*/
+
+#ifndef _PLATFORM_CPU_INFO_GUID_H_
+#define _PLATFORM_CPU_INFO_GUID_H_
+
+#include "CpuType.h"
+#include <Library/CpuIA32.h>
+
+#define EFI_PLATFORM_CPU_INFO_GUID \
+ {\
+ 0xbb9c7ab7, 0xb8d9, 0x4bf3, 0x9c, 0x29, 0x9b, 0xf3, 0x41, 0xe2, 0x17, 0xbc \
+ }
+
+extern EFI_GUID gEfiPlatformCpuInfoGuid;
+extern CHAR16 EfiPlatformCpuInfoVariable[];
+
+//
+// Tri-state for feature capabilities and enable/disable.
+// [0] clear=feature isn't capable
+// [0] set =feature is capable
+// [1] clear=feature is disabled
+// [1] set =feature is enabled
+//
+#define CPU_FEATURES_CAPABLE BIT0
+#define CPU_FEATURES_ENABLE BIT1
+
+#define MAX_CACHE_DESCRIPTORS 64
+#define MAXIMUM_CPU_BRAND_STRING_LENGTH 48
+
+#pragma pack(1)
+
+typedef struct {
+ UINT32 FullCpuId; // [31:0] & 0x0FFF0FFF
+ UINT32 FullFamilyModelId; // [31:0] & 0x0FFF0FF0
+ UINT8 ExtendedFamilyId; // [27:20]
+ UINT8 ExtendedModelId; // [19:16]
+ UINT8 ProcessorType; // [13:11]
+ UINT8 FamilyId; // [11:8]
+ UINT8 Model; // [7:4]
+ UINT8 SteppingId; // [3:0]
+} EFI_CPU_VERSION_INFO; // CPUID.1.EAX
+
+typedef struct {
+ UINT32 L1InstructionCacheSize;
+ UINT32 L1DataCacheSize;
+ UINT32 L2CacheSize;
+ UINT32 L3CacheSize;
+ UINT32 TraceCacheSize;
+ UINT8 CacheDescriptor[MAX_CACHE_DESCRIPTORS];
+} EFI_CPU_CACHE_INFO; // CPUID.2.EAX
+
+typedef struct {
+ UINT8 PhysicalPackages;
+ UINT8 LogicalProcessorsPerPhysicalPackage;
+ UINT8 CoresPerPhysicalPackage;
+ UINT8 ThreadsPerCore;
+} EFI_CPU_PACKAGE_INFO; // CPUID.4.EAX
+
+typedef struct {
+ UINT32 RegEdx; // CPUID.5.EAX
+ UINT8 MaxCState;
+ UINT8 C0SubCStatesMwait; // EDX [3:0]
+ UINT8 C1SubCStatesMwait; // EDX [7:4]
+ UINT8 C2SubCStatesMwait; // EDX [11:8]
+ UINT8 C3SubCStatesMwait; // EDX [15:12]
+ UINT8 C4SubCStatesMwait; // EDX [19:16]
+ UINT8 C5SubCStatesMwait; // EDX [23:20]
+ UINT8 C6SubCStatesMwait; // EDX [27:24]
+ UINT8 C7SubCStatesMwait; // EDX [31:28]
+ UINT8 MonitorMwaitSupport; // ECX [0]
+ UINT8 InterruptsBreakMwait; // ECX [1]
+} EFI_CPU_CSTATE_INFO; // CPUID.5.EAX
+
+typedef struct {
+ UINT8 Turbo; // EAX [1]
+ UINT8 PECI; // EAX [0]
+ UINT8 NumIntThresholds; // EBX [3:0]
+ UINT8 HwCoordinationFeedback; // ECX [0]
+} EFI_CPU_POWER_MANAGEMENT; // CPUID.6.EAX
+
+//
+// IMPORTANT: Each CPU feature enabling entry is assumed a tri-state variable.
+// - Keep the respective feature entry variable as default value (0x00)
+// if the CPU is not capable for the feature.
+// - Use the specially defined programming convention to update the variable
+// to indicate capable, enable or disable.
+// ie. F_CAPABLE for feature available
+// F_ENABLE for feature enable
+// F_DISABLE for feature disable
+//
+typedef struct {
+ EFI_CPUID_REGISTER Regs; // CPUID.1.EAX
+ UINT8 Xapic; // ECX [21]
+ UINT8 SSE4_2; // ECX [20]
+ UINT8 SSE4_1; // ECX [19]
+ UINT8 Dca; // ECX [18]
+ UINT8 SupSSE3; // ECX [9]
+ UINT8 Tm2; // ECX [8]
+ UINT8 Eist; // ECX [7]
+ UINT8 Lt; // ECX [6]
+ UINT8 Vt; // ECX [5]
+ UINT8 Mwait; // ECX [3]
+ UINT8 SSE3; // ECX [0]
+ UINT8 Tcc; // EDX [29]
+ UINT8 Mt; // EDX [28]
+ UINT8 SSE2; // EDX [26]
+ UINT8 SSE; // EDX [25]
+ UINT8 MMX; // EDX [23]
+ EFI_CPUID_REGISTER ExtRegs; // CPUID.80000001.EAX
+ UINT8 ExtLahfSahf64; // ECX [0]
+ UINT8 ExtIntel64; // EDX [29]
+ UINT8 ExtXd; // EDX [20]
+ UINT8 ExtSysCallRet64; // EDX [11]
+ UINT16 Ht; // CPUID.0B.EAX EBX [15:0]
+} EFI_CPU_FEATURES; // CPUID.1.EAX, CPUID.0B.EAX, CPUID.80000001.EAX
+
+typedef struct {
+ UINT8 PhysicalBits;
+ UINT8 VirtualBits;
+} EFI_CPU_ADDRESS_BITS; // CPUID.80000008.EAX
+
+typedef struct {
+ UINT8 PlatformID; // MSR 0x17 [52:50]
+ UINT32 MicrocodeRevision; // MSR 0x8B [63:32]
+ UINT8 MaxEfficiencyRatio; // MSR 0xCE [47:40]
+ UINT8 DdrRatioUnlockCap; // MSR 0xCE [30]
+ UINT8 TdcTdpLimitsTurbo; // MSR 0xCE [29]
+ UINT8 RatioLimitsTurbo; // MSR 0xCE [28]
+ UINT8 PreProduction; // MSR 0xCE [27]
+ UINT8 DcuModeSelect; // MSR 0xCE [26]
+ UINT8 MaxNonTurboRatio; // MSR 0xCE [15:8]
+ UINT8 Emrr; // MSR 0xFE [12]
+ UINT8 Smrr; // MSR 0xFE [11]
+ UINT8 VariableMtrrCount; // MSR 0xFE [7:0]
+ UINT16 PState; // MSR 0x198 [15:0]
+ UINT8 TccActivationTemperature; // MSR 0x1A2 [23:16]
+ UINT8 TemperatureControlOffset; // MSR 0x1A2 [15:8]
+ UINT32 PCIeBar; // MSR 0x300 [39:20]
+ UINT8 PCIeBarSizeMB; // MSR 0x300 [3:1]
+} EFI_MSR_FEATURES;
+
+typedef struct {
+ BOOLEAN IsIntelProcessor;
+ UINT8 BrandString[MAXIMUM_CPU_BRAND_STRING_LENGTH + 1];
+ UINT32 CpuidMaxInputValue;
+ UINT32 CpuidMaxExtInputValue;
+ EFI_CPU_UARCH CpuUarch;
+ EFI_CPU_FAMILY CpuFamily;
+ EFI_CPU_PLATFORM CpuPlatform;
+ EFI_CPU_TYPE CpuType;
+ EFI_CPU_VERSION_INFO CpuVersion;
+ EFI_CPU_CACHE_INFO CpuCache;
+ EFI_CPU_FEATURES CpuFeatures;
+ EFI_CPU_CSTATE_INFO CpuCState;
+ EFI_CPU_PACKAGE_INFO CpuPackage;
+ EFI_CPU_POWER_MANAGEMENT CpuPowerManagement;
+ EFI_CPU_ADDRESS_BITS CpuAddress;
+ EFI_MSR_FEATURES Msr;
+} EFI_PLATFORM_CPU_INFO;
+
+#pragma pack()
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h b/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h
new file mode 100644
index 0000000000..0a73f0d748
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/PlatformInfo.h
@@ -0,0 +1,437 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+
+Module Name:
+
+ PlatformInfo.h
+
+Abstract:
+
+ GUID used for Platform Info Data entries in the HOB list.
+
+--*/
+
+#ifndef _PLATFORM_INFO_GUID_H_
+#define _PLATFORM_INFO_GUID_H_
+
+#ifndef ECP_FLAG
+#include <PiPei.h>
+
+#include <Library/HobLib.h>
+#include <Library/IoLib.h>
+#include <Library/DebugLib.h>
+#include <Library/SmbusLib.h>
+#include <IndustryStandard/SmBus.h>
+#endif
+
+#define PLATFORM_INFO_REVISION = 1 // Revision id for current platform information struct.
+
+//
+// Start::BayLake Board Defines
+//
+#define BOARD_REVISION_DEFAULT = 0xff
+#define UNKNOWN_FABID 0x0F
+#define FAB_ID_MASK 0x0F
+#define BOARD_ID_2 0x01
+#define BOARD_ID_1 0x40
+#define BOARD_ID_0 0x04
+
+#define BOARD_ID_DT_CRB 0x0
+#define BOARD_ID_DT_VLVR 0x1
+#define BOARD_ID_SVP_VLV 0xC
+#define BOARD_ID_SVP_EV_VLV 0xD
+//
+// End::BayLake Board Defines
+//
+
+//
+// Start::Alpine Valley Board Defines
+//
+#define DC_ID_DDR3L 0x00
+#define DC_ID_DDR3 0x04
+#define DC_ID_LPDDR3 0x02
+#define DC_ID_LPDDR2 0x06
+#define DC_ID_DDR4 0x01
+#define DC_ID_DDR3L_ECC 0x05
+#define DC_ID_NO_MEM 0x07
+//
+// End::Alpine Valley Board Defines
+//
+
+#define MAX_FAB_ID_RETRY_COUNT 100
+#define MAX_FAB_ID_CHECK_COUNT 3
+
+#define PLATFORM_INFO_HOB_REVISION 0x1
+
+#define EFI_PLATFORM_INFO_GUID \
+ { \
+ 0x1e2acc41, 0xe26a, 0x483d, 0xaf, 0xc7, 0xa0, 0x56, 0xc3, 0x4e, 0x8, 0x7b \
+ }
+
+extern EFI_GUID gEfiPlatformInfoGuid;
+
+typedef enum {
+ FlavorUnknown = 0,
+
+ //
+ // Mobile
+ //
+ FlavorMobile = 1,
+
+ //
+ // Desktop
+ //
+ FlavorDesktop = 2,
+
+ //
+ // Tablet
+ //
+ FlavorTablet = 3
+} PLATFORM_FLAVOR;
+
+#pragma pack(1)
+
+typedef struct {
+ UINT16 PciResourceIoBase;
+ UINT16 PciResourceIoLimit;
+ UINT32 PciResourceMem32Base;
+ UINT32 PciResourceMem32Limit;
+ UINT64 PciResourceMem64Base;
+ UINT64 PciResourceMem64Limit;
+ UINT64 PciExpressBase;
+ UINT32 PciExpressSize;
+ UINT8 PciHostAddressWidth;
+ UINT8 PciResourceMinSecBus;
+} EFI_PLATFORM_PCI_DATA;
+
+typedef struct {
+ UINT8 CpuAddressWidth;
+ UINT32 CpuFamilyStepping;
+} EFI_PLATFORM_CPU_DATA;
+
+typedef struct {
+ UINT8 SysIoApicEnable;
+ UINT8 SysSioExist;
+} EFI_PLATFORM_SYS_DATA;
+
+typedef struct {
+ UINT32 MemTolm;
+ UINT32 MemMaxTolm;
+ UINT32 MemTsegSize;
+ UINT32 MemTsegBase;
+ UINT32 MemIedSize;
+ UINT32 MemIgdSize;
+ UINT32 MemIgdBase;
+ UINT32 MemIgdGttSize;
+ UINT32 MemIgdGttBase;
+ UINT64 MemMir0;
+ UINT64 MemMir1;
+ UINT32 MemConfigSize;
+ UINT16 MmioSize;
+ UINT8 DdrFreq;
+ UINT8 DdrType;
+ UINT32 MemSize;
+ BOOLEAN EccSupport;
+ UINT8 Reserved[3];
+ UINT16 DimmSize[2];
+} EFI_PLATFORM_MEM_DATA;
+
+
+typedef struct {
+ UINT32 IgdOpRegionAddress; // IGD OpRegion Starting Address
+ UINT8 IgdBootType; // IGD Boot Display Device
+ UINT8 IgdPanelType; // IGD Panel Type CMOs option
+ UINT8 IgdTvFormat; // IGD TV Format CMOS option
+ UINT8 IgdTvMinor; // IGD TV Minor Format CMOS option
+ UINT8 IgdPanelScaling; // IGD Panel Scaling
+ UINT8 IgdBlcConfig; // IGD BLC Configuration
+ UINT8 IgdBiaConfig; // IGD BIA Configuration
+ UINT8 IgdSscConfig; // IGD SSC Configuration
+ UINT8 IgdDvmtMemSize; // IGD DVMT Memory Size
+ UINT8 IgdFunc1Enable; // IGD Function 1 Enable
+ UINT8 IgdHpllVco; // HPLL VCO
+ UINT8 IgdSciSmiMode; // GMCH SMI/SCI mode (0=SCI)
+ UINT8 IgdPAVP; // IGD PAVP data
+} EFI_PLATFORM_IGD_DATA;
+
+typedef enum {
+ BOARD_ID_AV_SVP = 0x0, // Alpine Valley Board
+ BOARD_ID_BL_RVP = 0x2, // BayLake Board (RVP)
+ BOARD_ID_BL_FFRD8 = 0x3, // FFRD8 b'0011
+ BOARD_ID_BL_FFRD = 0x4, // BayLake Board (FFRD)
+ BOARD_ID_BL_RVP_DDR3L = 0x5, // BayLake Board (RVP DDR3L)
+ BOARD_ID_BL_STHI = 0x7, // PPV- STHI Board
+ BOARD_ID_BB_RVP = 0x20, // Bayley Bay Board
+ BOARD_ID_BS_RVP = 0x30, // Bakersport Board
+ BOARD_ID_CVH = 0x90, // Crestview Hills
+ BOARD_ID_MINNOW2 = 0xA0 // Minnow2
+
+} BOARD_ID_LIST;
+
+typedef enum {
+ FAB1 = 0,
+ FAB2 = 1,
+ FAB3 = 2
+} FAB_ID_LIST;
+
+typedef enum {
+ PR0 = 0, // FFRD PR0
+ PR05 = 1, // FFRD PR0.3 and PR 0.5
+ PR1 = 2, // FFRD PR1
+ PR11 = 3 // FFRD PR1.1
+} FFRD_ID_LIST;
+
+
+//
+// VLV2 GPIO GROUP OFFSET
+//
+#define GPIO_SCORE_OFFSET 0x0000
+#define GPIO_NCORE_OFFSET 0x1000
+#define GPIO_SSUS_OFFSET 0x2000
+
+//
+// GPIO Initialization Data Structure for BayLake.
+// SC = SCORE, SS= SSUS
+// Note: NC doesn't support GPIO functionality in IO access mode, only support in MMIO access mode.
+//
+
+//
+// IO space
+//
+typedef struct{
+ UINT32 Use_Sel_SC0;
+ UINT32 Use_Sel_SC1;
+ UINT32 Use_Sel_SC2;
+ UINT32 Use_Sel_SS;
+
+ UINT32 Io_Sel_SC0;
+ UINT32 Io_Sel_SC1;
+ UINT32 Io_Sel_SC2;
+ UINT32 Io_Sel_SS;
+
+ UINT32 GP_Lvl_SC0;
+ UINT32 GP_Lvl_SC1;
+ UINT32 GP_Lvl_SC2;
+ UINT32 GP_Lvl_SS;
+
+ UINT32 TPE_SC0;
+ UINT32 TPE_SS;
+
+ UINT32 TNE_SC0;
+ UINT32 TNE_SS;
+
+ UINT32 TS_SC0;
+ UINT32 TS_SS;
+
+ UINT32 WE_SS;
+} CFIO_INIT_STRUCT;
+
+
+
+//
+// CFIO PAD configuration Registers
+//
+//
+// Memory space
+//
+typedef union {
+ UINT32 dw;
+ struct {
+ UINT32 Func_Pin_Mux:3; // 0:2 Function of CFIO selection
+ UINT32 ipslew:2; // 3:4 Pad (P) Slew Rate Controls PAD slew rate check Width
+ UINT32 inslew:2; // 5:6 Pad (N) Slew Rate Controls PAD slew rate
+ UINT32 Pull_assign:2; // 7:8 Pull assignment
+ UINT32 Pull_strength:2; // 9:10 Pull strength
+ UINT32 Bypass_flop:1; // 11 Bypass flop
+ UINT32 Filter_en:1; // 12 Filter Enable
+ UINT32 Hist_ctrl:2; // 13:14 hysteresis control
+ UINT32 Hist_enb:1; // 15 Hysteresis enable, active low
+ UINT32 Delay_line:6; // 16:21 Delay line values - Delay values for input or output
+ UINT32 Reserved:3; // 22:24 Reserved
+ UINT32 TPE:1; // 25 Trigger Positive Edge Enable
+ UINT32 TNE:1; // 26 Trigger Negative Edge Enable
+ UINT32 Reserved2:3; // 27:29 Reserved
+ UINT32 i1p5sel:1; // 30
+ UINT32 IODEN:1; // 31 : Open Drain enable. Active high
+ } r;
+} PAD_CONF0;
+
+typedef union{
+ UINT32 dw;
+ struct {
+ UINT32 instr:16; // 0:15 Pad (N) strength.
+ UINT32 ipstr:16; // 16:31 Pad (P) strength.
+ }r;
+} PAD_CONF1;
+
+typedef union{
+ UINT32 dw;
+ struct {
+ UINT32 pad_val:1; // 0 These registers are implemented as dual read/write with dedicated storage each.
+ UINT32 ioutenb:1; // 1 output enable
+ UINT32 iinenb:1; // 2 input enable
+ UINT32 Reserved:29; // 3:31 Reserved
+ }r;
+} PAD_VAL;
+
+typedef union{
+ UINT32 GPI;
+ struct {
+ UINT32 ihbpen:1; // 0 Pad high by pass enable
+ UINT32 ihbpinen:1; // 1 Pad high by pass input
+ UINT32 instaticen:1; // 2 TBD
+ UINT32 ipstaticen:1; // 3 TBD
+ UINT32 Overide_strap_pin :1; // 4 DFX indicates if it wants to override the strap pin value on this pad, if exists.
+ UINT32 Overide_strap_pin_val:1; // 5 In case DFX need to override strap pin value and it exist for the specific pad, this value will be used.
+ UINT32 TestMode_Pin_Mux:3; // 6:9 DFX Pin Muxing
+ }r;
+} PAD_DFT;
+
+//
+// GPIO_USAGE value need to matche the PAD_VAL input/output enable bits.
+//
+typedef enum {
+ Native = 0xFF, // Native, no need to set PAD_VALUE
+ GPI = 2, // GPI, input only in PAD_VALUE
+ GPO = 4, // GPO, output only in PAD_VALUE
+ GPIO = 0, // GPIO, input & output
+ TRISTS = 6, // Tri-State
+ GPIO_NONE
+} GPIO_USAGE;
+
+typedef enum {
+ LO = 0,
+ HI = 1,
+ NA = 0xFF
+} GPO_D4;
+
+typedef enum {
+ F0 = 0,
+ F1 = 1,
+ F2 = 2,
+ F3 = 3,
+ F4 = 4,
+ F5 = 5,
+ F6 = 6,
+ F7 = 7
+} GPIO_FUNC_NUM;
+
+//
+// Mapping to CONF0 bit 27:24
+// Note: Assume "Direct Irq En" is not set, unless specially notified.
+//
+typedef enum {
+ TRIG_ = 0,
+ TRIG_Edge_High = /*BIT3 |*/ BIT1, // Positive Edge (Rasing)
+ TRIG_Edge_Low = /*BIT3 |*/ BIT2, // Negative Edge (Falling)
+ TRIG_Edge_Both = /*BIT3 |*/ BIT2 | BIT1, // Both Edge
+ TRIG_Level_High= /*BIT3 |*/ BIT1 | BIT0, // Level High
+ TRIG_Level_Low = /*BIT3 |*/ BIT2 | BIT0, // Level Low
+} INT_TYPE;
+
+typedef enum {
+ P_20K_H, // Pull Up 20K
+ P_20K_L, // Pull Down 20K
+ P_10K_H, // Pull Up 10K
+ P_10K_L, // Pull Down 10K
+ P_2K_H, // Pull Up 2K
+ P_2K_L, // Pull Down 2K
+ P_NONE // Pull None
+} PULL_TYPE;
+
+#ifdef EFI_DEBUG
+ #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) {pad_name, usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
+#else
+ #define GPIO_INIT_ITEM(pad_name, usage, gpod4, func, int_cap, int_type, pull, offset) { usage, gpod4, func, /*int_cap,*/ TRIG_##int_type, P_##pull, offset}
+#endif
+
+//
+// GPIO CONF & PAD Initialization Data Structure for BayLake GPIOs bits.
+// NC = NCORE, SC = SCORE, SS= SSUS
+//
+typedef struct {
+
+#ifdef EFI_DEBUG
+ char pad_name[32];// GPIO Pin Name for debug purpose
+#endif
+
+ GPIO_USAGE usage; // GPIO pin used as Native mode or GPI/GPO/GPIO mode
+ GPO_D4 gpod4; // GPO default value
+ GPIO_FUNC_NUM func; // Function Number (F0~F7)
+ INT_TYPE int_type; // Edge or Level trigger, low or high active
+ PULL_TYPE pull; // Pull Up or Down
+ UINT8 offset; // Equal with (PCONF0 register offset >> 4 bits)
+} GPIO_CONF_PAD_INIT;
+
+//
+//typedef UINT64 BOARD_FEATURES
+//
+typedef struct _EFI_PLATFORM_INFO_HOB {
+ UINT16 PlatformType; // Platform Type
+ UINT8 BoardId; // Board ID
+ UINT8 BoardRev; // Board Revision
+ PLATFORM_FLAVOR PlatformFlavor; // Platform Flavor
+ UINT8 DDRDaughterCardCh0Id;// DDR daughter card channel 0 id
+ UINT8 DDRDaughterCardCh1Id;// DDR daughter card channel 1 id
+ UINT8 ECOId; // ECO applied on platform
+ UINT16 IohSku;
+ UINT8 IohRevision;
+ UINT16 IchSku;
+ UINT8 IchRevision;
+ EFI_PLATFORM_PCI_DATA PciData;
+ EFI_PLATFORM_CPU_DATA CpuData;
+ EFI_PLATFORM_MEM_DATA MemData;
+ EFI_PLATFORM_SYS_DATA SysData;
+ EFI_PLATFORM_IGD_DATA IgdData;
+ UINT8 RevisonId; // Structure Revision ID
+ EFI_PHYSICAL_ADDRESS PlatformCfioData;
+ EFI_PHYSICAL_ADDRESS PlatformGpioData_NC;
+ EFI_PHYSICAL_ADDRESS PlatformGpioData_SC;
+ EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS;
+ EFI_PHYSICAL_ADDRESS PlatformGpioData_NC_TRI;
+ EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_TRI;
+ EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_TRI;
+ EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1;
+ EFI_PHYSICAL_ADDRESS PlatformGpioData_SC_PR1_1;
+ EFI_PHYSICAL_ADDRESS PlatformGpioData_SUS_PR1_1;
+
+ UINT8 CfioEnabled;
+ UINT32 SsidSvid;
+ UINT16 AudioSubsystemDeviceId;
+ UINT64 AcpiOemId;
+ UINT64 AcpiOemTableId;
+ UINT16 MemCfgID;
+} EFI_PLATFORM_INFO_HOB;
+
+#pragma pack()
+
+EFI_STATUS
+GetPlatformInfoHob (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO_HOB **PlatformInfoHob
+ );
+
+
+EFI_STATUS
+InstallPlatformClocksNotify (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+EFI_STATUS
+InstallPlatformSysCtrlGPIONotify (
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ );
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h b/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h
new file mode 100644
index 0000000000..b058e3ceb5
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/SensorInfoVariable.h
@@ -0,0 +1,284 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+ This program and the accompanying materials are licensed and made available under
+ the terms and conditions of the BSD License that accompanies this distribution.
+ The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php.
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+
+Module Name:
+
+ SensorInfoVariable.h
+
+Abstract:
+
+ GUID used for Sensor Info variable.
+
+--*/
+
+
+//
+// Module: SensorInfoVariable.h
+//
+// Description: Provides structure and literal definitions for the
+// Sensor Information Variable. The BIOS will provide
+// this variable to runtime applications via the EFI
+// GetVariable function.
+//
+// Notes: 1. When defining and initializing the variable within the
+// BIOS, the module will define the structure using the
+// typedef macros in a block. For an ATX board using a
+// single Heceta 6P, which has 4 temperature sensors, 6
+// voltage sensors, 4 fan speed sensors and 3 fan speed
+// controllers, this block would be declared as follows:
+//
+// TYPEDEF_TEMP_SENSOR_SECTION(4);
+// TYPEDEF_VOLT_SENSOR_SECTION(6);
+// TYPEDEF_FAN_SENSOR_SECTION(4);
+// TYPEDEF_FAN_CONTROLLER_SENSOR(3);
+// TYPEDEF_SENSOR_INFO_VAR;
+//
+// 2. When crafting code to access the variable, the module
+// will also need to invoke the typedef macros in a
+// block but, since it cannot declare a structure for the
+// overall variable (because array lengths will vary), it
+// cannot use TYPEDEF_SENSOR_INFO_VAR. The block will
+// typically be used as follows:
+//
+// TYPEDEF_TEMP_SENSOR_SECTION(1);
+// TYPEDEF_VOLT_SENSOR_SECTION(1);
+// TYPEDEF_FAN_SENSOR_SECTION(1);
+// TYPEDEF_FAN_CONTROLLER_SENSOR(1);
+//
+// The structure buffer should instead be declared as a
+// BYTE array. Pointers to the various sections can then
+// be built using the XXXX_SECTION_LEN macros...
+//
+
+
+#ifndef _SENSOR_INFO_VAR_GUID_H_
+#define _SENSOR_INFO_VAR_GUID_H_
+
+#define SENSOR_INFO_VAR_GUID \
+ { \
+ 0xE59E7B4D, 0x06DC, 0x44AB, 0xB3, 0x6D, 0x5E, 0xD7, 0x78, 0x9C, 0x53, 0x0A \
+ }
+
+extern EFI_GUID gEfiSensorInfoVarGuid;
+extern CHAR16 gEfiSensorInfoVarName[];
+extern CHAR16 gEfiSensorInfoVarNameWithPassword[];
+
+#define SENSOR_INFO_VAR_NAME L"SensorInfoVar"
+#define SENSOR_INFO_VAR_NAME_WITH_PASSWORD SENSOR_INFO_VAR_NAME L"S4k?A^7!"
+
+//
+// Sensor/Controller usage definitions
+//
+
+#define UNKNOWN_OTHER 0
+
+//
+// Temperature Sensors
+//
+#define CPU_CORE_TEMPERATURE 1
+#define CPU_DIE_TEMPERATURE 2
+#define ICH_TEMPERATURE 3
+#define MCH_TEMPERATURE 4
+#define VR_TEMPERATURE 5
+#define MEMORY_TEMPERATURE 6
+#define MOTHERBOARD_AMBIENT_TEMPERATURE 7
+#define SYSTEM_AMBIENT_AIR_TEMPERATURE 8
+#define CPU_INLET_AIR_TEMPERATURE 9
+#define SYSTEM_INLET_AIR_TEMPERATURE 10
+#define SYSTEM_OUTLET_AIR_TEMPERATURE 11
+#define PSU_HOTSPOT_TEMPERATURE 12
+#define PSU_INLET_AIR_TEMPERATURE 13
+#define PSU_OUTLET_AIR_TEMPERATURE 14
+#define DRIVE_TEMPERATURE 15
+#define GPU_TEMPERATURE 16
+#define IOH_TEMPERATURE 17
+
+#define LAST_TEMPERATURE 17
+
+//
+// Voltage Sensors
+//
+#define PLUS_12_VOLTS 1
+#define NEG_12_VOLTS 2
+#define PLUS_5_VOLTS 3
+#define PLUS_5_VOLT_BACKUP 4
+#define NEG_5_VOLTS 5
+#define PLUS_3P3_VOLTS 6
+#define PLUS_2P5_VOLTS 7
+#define PLUS_1P5_VOLTS 8
+#define CPU_1_VCCP_VOLTAGE 9
+#define CPU_2_VCCP_VOLTAGE 10
+#define CPU_3_VCCP_VOLTAGE 11
+#define CPU_4_VCCP_VOLTAGE 12
+#define PSU_INPUT_VOLTAGE 13
+#define MCH_VCC_VOLTAGE 14
+#define PLUS_3P3_VOLT_STANDBY 15
+#define CPU_VTT_VOLTAGE 16
+#define PLUS_1P8_VOLTS 17
+
+#define LAST_VOLTAGE 17
+
+//
+// Fan Speed Sensors and Controllers.
+//
+#define CPU_COOLING_FAN 1
+#define SYSTEM_COOLING_FAN 2
+#define MCH_COOLING_FAN 3
+#define VR_COOLING_FAN 4
+#define CHASSIS_COOLING_FAN 5
+#define CHASSIS_INLET_FAN 6
+#define CHASSIS_OUTLET_FAN 7
+#define PSU_COOLING_FAN 8
+#define PSU_INLET_FAN 9
+#define PSU_OUTLET_FAN 10
+#define DRIVE_COOLING_FAN 11
+#define GPU_COOLING_FAN 12
+#define AUX_COOLING_FAN 13
+#define IOH_COOLING_FAN 14
+
+#define LAST_FAN 14
+
+//
+// Fan Type Definitions
+//
+#define FAN_TYPE_UNKNOWN 0
+#define FAN_3WIRE_PULSE 1
+#define FAN_3WIRE_VOLTAGE 2
+#define FAN_4WIRE 3
+
+#pragma pack(1)
+
+//
+// TEMP_SENSOR_INFO - Structure providing info for a temperature sensor.
+//
+typedef struct _TEMP_SENSOR_INFO
+{
+ UINT8 byDevice; // Device index
+ UINT8 byIndex; // Physical sensor index
+ UINT8 byUsage; // Usage indicator
+ UINT8 bRelative; // Relative vs. Absolute readings
+
+} TEMP_SENSOR_INFO, *P_TEMP_SENSOR_INFO;
+
+//
+// TYPEDEF_TEMP_SENSOR_SECTION - Macro that can be used to typedef the
+// TEMP_SENSOR_SECTION structure, which provides information about all
+// temperature sensors.
+//
+#define TYPEDEF_TEMP_SENSOR_SECTION(count) \
+typedef struct _TEMP_SENSOR_SECTION \
+{ \
+ UINT8 byCount; \
+ TEMP_SENSOR_INFO stSensor[count]; \
+ \
+} TEMP_SENSOR_SECTION, *P_TEMP_SENSOR_SECTION
+
+//
+// VOLT_SENSOR_INFO - Structure providing info for a voltage sensor.
+//
+typedef struct _VOLT_SENSOR_INFO
+{
+ UINT8 byDevice; // Device index
+ UINT8 byIndex; // Physical sensor index
+ UINT8 byUsage; // Usage indicator
+
+} VOLT_SENSOR_INFO, *P_VOLT_SENSOR_INFO;
+
+//
+// TYPEDEF_VOLT_SENSOR_SECTION - Macro that can be used to typedef the
+// VOLT_SENSOR_SECTION structure, which provides information about all
+// voltage sensors.
+//
+#define TYPEDEF_VOLT_SENSOR_SECTION(count) \
+typedef struct _VOLT_SENSOR_SECTION \
+{ \
+ UINT8 byCount; \
+ VOLT_SENSOR_INFO stSensor[count]; \
+ \
+} VOLT_SENSOR_SECTION, *P_VOLT_SENSOR_SECTION
+
+//
+// FAN_SENSOR_INFO - Structure providing info for a fan speed sensor.
+//
+typedef struct _FAN_SENSOR_INFO
+{
+ UINT8 byDevice; // Device index
+ UINT8 byIndex; // Physical sensor index
+ UINT8 byUsage; // Usage indicator
+ UINT8 byType; // Fan type
+ UINT8 byController; // Associated Fan Controller
+
+} FAN_SENSOR_INFO, *P_FAN_SENSOR_INFO;
+
+//
+// TYPEDEF_FAN_SENSOR_SECTION - Macro that can be used to typedef the
+// FAN_SENSOR_SECTION structure, which provides information about all fan
+// speed sensors.
+//
+#define TYPEDEF_FAN_SENSOR_SECTION(count) \
+typedef struct _FAN_SENSOR_SECTION \
+{ \
+ UINT8 byCount; \
+ FAN_SENSOR_INFO stSensor[count]; \
+ \
+} FAN_SENSOR_SECTION, *P_FAN_SENSOR_SECTION
+
+//
+// FAN_CONTROLLER_INFO - Structure providing info for a fan speed controller.
+//
+#define MAX_ASSOC_FANS 4
+#define ASSOC_UNUSED 0xFF
+
+typedef struct _FAN_CONTROLLER_INFO
+{
+ UINT8 byDevice; // Device index
+ UINT8 byIndex; // Physical Controller Index
+ UINT8 byUsage; // Usage Indicator
+ UINT8 byFan[MAX_ASSOC_FANS]; // Associated Fan Sensors
+
+} FAN_CONTROLLER_INFO, *P_FAN_CONTROLLER_INFO;
+
+//
+// TYPEDEF_FAN_CONTROLLER_SECTION - Macro that can be used to typedef the
+// FAN_CONTROLLER_SECTION structure, which provides information about all
+// fan speed controllers.
+//
+#define TYPEDEF_FAN_CONTROLLER_SECTION(count) \
+typedef struct _FAN_CONTROLLER_SECTION \
+{ \
+ UINT8 byCount; \
+ FAN_CONTROLLER_INFO stController[count]; \
+ \
+} FAN_CONTROLLER_SECTION, *P_FAN_CONTROLLER_SECTION
+
+//
+// TYPEDEF_SENSOR_INFO_VAR - Macro that can be used to typedef the
+// SENSOR_INFO_VAR structure, which provides information about all sensors
+// and fan speed controllers. The other TYPEDEF macros must be invoked
+// before using this one...
+//
+#define TYPEDEF_SENSOR_INFO_VAR \
+typedef struct _SENSOR_INFO_VAR \
+{ \
+ TEMP_SENSOR_SECTION stTemps; \
+ VOLT_SENSOR_SECTION stVolts; \
+ FAN_SENSOR_SECTION stFans; \
+ FAN_CONTROLLER_SECTION stCtrls; \
+ \
+} SENSOR_INFO_VAR, *P_SENSOR_INFO_VAR
+
+#pragma pack()
+
+#endif
diff --git a/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h b/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
new file mode 100644
index 0000000000..eb0a1760b0
--- /dev/null
+++ b/Vlv2TbltDevicePkg/Include/Guid/SetupVariable.h
@@ -0,0 +1,1351 @@
+/*++
+
+ Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
+
+
+ This program and the accompanying materials are licensed and made available under
+
+ the terms and conditions of the BSD License that accompanies this distribution.
+
+ The full text of the license may be found at
+
+ http://opensource.org/licenses/bsd-license.php.
+
+
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+
+
+
+Module Name:
+
+ SetupVariable.h
+
+Abstract:
+
+ Driver configuration include file
+
+
+--*/
+
+#ifndef _SETUP_VARIABLE_H
+#define _SETUP_VARIABLE_H
+
+//
+// ---------------------------------------------------------------------------
+//
+// Driver Configuration
+//
+// ---------------------------------------------------------------------------
+//
+
+//
+// {EC87D643-EBA4-4bb5-A1E5-3F3E36B20DA9}
+//
+#define SYSTEM_CONFIGURATION_GUID\
+ { \
+ 0xec87d643, 0xeba4, 0x4bb5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 \
+ }
+
+#define ROOT_SECURITY_GUID\
+ { \
+ 0xd387d688, 0xeba4, 0x45b5, 0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0x37 \
+ }
+
+//
+// {6936B3BD-4350-46d9-8940-1FA20961AEB1}
+//
+#define SYSTEM_ROOT_MAIN_GUID\
+ { \
+ 0x6936b3bd, 0x4350, 0x46d9, 0x89, 0x40, 0x1f, 0xa2, 0x9, 0x61, 0xae, 0xb1 \
+ }
+
+//
+// {21FEE8DB-0D29-477e-B5A9-96EB343BA99C}
+//
+#define ADDITIONAL_SYSTEM_INFO_GUID\
+ { \
+ 0x21fee8db, 0xd29, 0x477e, 0xb5, 0xa9, 0x96, 0xeb, 0x34, 0x3b, 0xa9, 0x9c \
+ }
+
+#define SETUP_GUID { 0xEC87D643, 0xEBA4, 0x4BB5, 0xA1, 0xE5, 0x3F, 0x3E, 0x36, 0xB2, 0x0D, 0xA9 }
+
+// {1B838190-4625-4ead-ABC9-CD5E6AF18FE0}
+#define EFI_HII_EXPORT_DATABASE_GUID { 0x1b838190, 0x4625, 0x4ead, 0xab, 0xc9, 0xcd, 0x5e, 0x6a, 0xf1, 0x8f, 0xe0 }
+
+#define PASSWORD_MAX_SIZE 20
+
+#define MAX_CUSTOM_VID_TABLE_STATES 6
+//
+// Overclocking Source Defines
+//
+#define OVERCLOCK_SOURCE_BIOS 0
+#define OVERCLOCK_SOURCE_OS 1
+
+#define PCH_PCIE_MAX_ROOT_PORTS 4
+
+#pragma pack(1)
+
+// NOTE: When you add anything to this structure,
+// you MUST add it to the very bottom!!!!
+// You must make sure the structure size is able to divide by 32!
+typedef struct {
+
+ //
+ // Floppy
+ //
+ UINT8 Floppy;
+ UINT8 FloppyLockHide;
+
+ UINT8 FloppyWriteProtect;
+ UINT8 FloppyWriteProtectLockHide;
+
+ //
+ // System ports
+ //
+ UINT8 Serial;
+ UINT8 SerialLockHide;
+
+ UINT8 Serial2;
+ UINT8 Serial2LockHide;
+
+ UINT8 Parallel;
+ UINT8 ParallelLockHide;
+
+ UINT8 ParallelMode;
+ UINT8 ParallelModeLockHide;
+
+ UINT8 AllUsb;
+ UINT8 UsbPortsLockHide;
+
+ UINT8 Usb2;
+ UINT8 Usb2LockHide;
+
+ UINT8 UsbLegacy;
+ UINT8 UsbLegacyLockHide;
+
+ UINT8 Audio;
+ UINT8 AudioLockHide;
+
+ UINT8 Lan;
+ UINT8 LanLockHide;
+
+ //
+ // Keyboard
+ //
+ UINT8 Numlock;
+ UINT8 NumlockLockHide;
+
+ //
+ // ECIR
+ //
+ UINT8 ECIR;
+ UINT8 ECIRLockHide;
+
+ //
+ // Power State
+ //
+ UINT8 PowerState;
+ UINT8 PowerStateLockHide;
+
+ //
+ // Wake on RTC variables
+ //
+ UINT8 WakeOnRtcS5;
+ UINT8 WakeOnRtcS5LockHide;
+ UINT8 RTCWakeupDate;
+ UINT8 RTCWakeupDateLockHide;
+ UINT8 RTCWakeupTimeHour;
+ UINT8 RTCWakeupHourLockHide;
+ UINT8 RTCWakeupTimeMinute;
+ UINT8 RTCWakeupMinuteLockHide;
+ UINT8 RTCWakeupTimeSecond;
+ UINT8 RTCWakeupSecondLockHide;
+
+ //
+ // Wake On Lan
+ //
+ UINT8 WakeOnLanS5;
+ UINT8 WakeOnLanS5LockHide;
+
+ //Spread spectrum
+ UINT8 SpreadSpectrum;
+
+ //
+ // Boot Order
+ //
+ UINT8 BootOrder[8];
+ UINT8 BootOrderLockHide;
+
+ //
+ // Hard Drive Boot Order
+ //
+ UINT8 HardDriveBootOrder[8];
+ UINT8 HardDriveBootOrderLockHide;
+
+ //
+ // CD Drive Boot Order
+ //
+ UINT8 CdDriveBootOrder[4];
+ UINT8 CdDriveBootOrderLockHide;
+
+ //
+ // FDD Drive Boot Order
+ //
+ UINT8 FddDriveBootOrder[4];
+ UINT8 FddDriveBootOrderLockHide;
+
+ //
+ // Drive Boot Order
+ //
+ UINT8 DriveBootOrder[16];
+ UINT8 DriveBootOrderLockHide;
+
+ //
+ // Boot Menu Type
+ //
+ UINT8 BootMenuType;
+ UINT8 BootMenuTypeLockHide;
+
+ //
+ // Boot from Removable Devices
+ //
+ UINT8 BootFloppy;
+ UINT8 BootFloppyLockHide;
+
+ //
+ // Boot from Optical Devices
+ //
+ UINT8 BootCd;
+ UINT8 BootCdLockHide;
+
+ //
+ // Boot from Network
+ //
+ UINT8 BootNetwork;
+ UINT8 BootNetworkLockHide;
+
+ //
+ // Boot USB
+ //
+ UINT8 BootUsb;
+ UINT8 BootUsbLockHide;
+
+ //
+ // USB Zip Emulation Type
+ //
+ UINT8 UsbZipEmulation;
+ UINT8 UsbZipEmulationLockHide;
+
+ //
+ // USB Devices Boot First in Boot Order
+ //
+ UINT8 UsbDevicesBootFirst;
+ UINT8 UsbDevicesBootFirstLockHide;
+
+ //
+ // USB Boot Device SETUP Emulation
+ //
+ UINT8 UsbSetupDeviceEmulation;
+ UINT8 UsbSetupDeviceEmulationLockHide;
+
+ //
+ // BIOS INT13 Emulation for USB Mass Devices
+ //
+ UINT8 UsbBIOSINT13DeviceEmulation;
+ UINT8 UsbBIOSINT13DeviceEmulationLockHide;
+
+ //
+ // BIOS INT13 Emulation Size for USB Mass Devices
+ //
+ UINT16 UsbBIOSINT13DeviceEmulationSize;
+ UINT8 UsbBIOSINT13DeviceEmulationSizeLockHide;
+
+ //
+ // Dummy place holder to prevent VFR compiler problem.
+ //
+ UINT16 DummyDataForVfrBug; // Don't change or use.
+
+ //
+ // Language Select
+ //
+ UINT8 LanguageSelect;
+
+ //
+ // SATA Type (Ide, Ahci, Raid)
+ //
+ UINT8 SataType;
+ UINT8 SataTypeLockHide;
+ UINT8 SataTestMode;
+
+ //
+ // Fixed Disk Boot Sector (Fdbs)
+ //
+ UINT8 Fdbs;
+ UINT8 FdbsLockHide;
+
+ //
+ // DisplaySetupPrompt
+ //
+ UINT8 DisplaySetupPrompt;
+ UINT8 DisplaySetupPromptLockHide;
+
+ //
+ // ASF
+ //
+ UINT8 Asf;
+ UINT8 AsfLockHide;
+
+ //
+ // Event Logging
+ //
+ UINT8 EventLogging;
+ UINT8 EventLoggingLockHide;
+
+ //
+ // Clear Event Log
+ //
+ UINT8 ClearEvents;
+ UINT8 ClearEventsLockHide;
+
+ //
+ // Expansion Card Text
+ //
+ UINT8 ExpansionCardText;
+ UINT8 ExpansionCardTextLockHide;
+
+ //
+ // Video Adaptor
+ //
+ UINT8 PrimaryVideoAdaptor;
+ UINT8 PrimaryVideoAdaptorLockHide;
+
+ //
+ // Chassis intrusion
+ //
+ UINT8 IntruderDetection;
+ UINT8 IntruderDetectionLockHide;
+
+ //
+ // User Access Level
+ //
+ UINT8 UserPasswordLevel;
+ UINT8 UserPasswordLevelLockHide;
+
+ //
+ // Maximum FSB Automatic/Disable
+ //
+ UINT8 MaxFsb;
+ UINT8 MaxFsbLockHide;
+
+ //
+ // Hard Disk Pre-delay
+ //
+ UINT8 HddPredelay;
+ UINT8 HddPredelayLockHide;
+
+ //
+ // S.M.A.R.T. Mode
+ //
+ UINT8 SmartMode;
+ UINT8 SmartModeLockHide;
+
+ //
+ // ACPI Suspend State
+ //
+ UINT8 AcpiSuspendState;
+ UINT8 AcpiSuspendStateLockHide;
+
+ //
+ // PCI Latency Timer
+ //
+ UINT8 PciLatency;
+ UINT8 PciLatencyLockHide;
+
+ //
+ // Fan Control
+ //
+ UINT8 FanControl;
+ UINT8 FanControlLockHide;
+
+ //
+ // CPU Fan Control
+ //
+ UINT8 CpuFanControl;
+ UINT8 CpuFanControlLockHide;
+
+ //
+ // Lowest Fan Speed
+ //
+ UINT8 LowestFanSpeed;
+ UINT8 LowestFanSpeedLockHide;
+
+ //
+ // Processor (CPU)
+ //
+ UINT8 CpuFlavor;
+
+ UINT8 CpuidMaxValue;
+ UINT8 CpuidMaxValueLockHide;
+
+ UINT8 ExecuteDisableBit;
+ UINT8 ExecuteDisableBitLockHide;
+
+ //
+ // EIST or GV3 setup option
+ //
+ UINT8 ProcessorEistEnable;
+ UINT8 ProcessorEistEnableLockHide;
+
+ //
+ // C1E Enable
+ //
+ UINT8 ProcessorC1eEnable;
+ UINT8 ProcessorC1eEnableLockHide;
+
+ //
+ // Enabling CPU C-States of processor
+ //
+ UINT8 ProcessorCcxEnable;
+ UINT8 ProcessorCcxEnableLockHide;
+
+ //
+ // Package C-State Limit
+ //
+ UINT8 PackageCState;
+ UINT8 PackageCStateLockHide;
+
+ //
+ // Enable/Disable NHM C3(ACPI C2) report to OS
+ //
+ UINT8 OSC2Report;
+ UINT8 OSC2ReportLockHide;
+
+ //
+ // Enable/Disable NHM C6(ACPI C3) report to OS
+ //
+ UINT8 C6Enable;
+ UINT8 C6EnableLockHide;
+
+ //
+ // Enable/Disable NHM C7(ACPI C3) report to OS
+ //
+ UINT8 C7Enable;
+ UINT8 C7EnableLockHide;
+
+ //
+ // EIST/PSD Function select option
+ //
+ UINT8 ProcessorEistPsdFunc;
+ UINT8 ProcessorEistPsdFuncLockHide;
+
+ //
+ //
+ //
+ UINT8 CPU00;
+ UINT8 CPU01;
+
+ //
+ //
+ //
+ UINT8 CPU02;
+ UINT8 CPU03;
+
+ //
+ //
+ //
+ UINT8 CPU04;
+ UINT8 CPU05;
+
+ //
+ //
+ //
+ UINT8 CPU06;
+ UINT8 CPU07;
+
+ //
+ //
+ //
+ UINT8 CPU08;
+ UINT8 CPU09;
+
+ //
+ //
+ //
+ UINT8 CPU10;
+ UINT8 CPU11;
+
+ //
+ //
+ //
+ UINT8 CPU12;
+ UINT8 CPU13;
+
+ //
+ //
+ //
+ UINT8 CPU14;
+ UINT8 CPU15;
+
+ //
+ //
+ //
+ UINT8 CPU16;
+ UINT8 CPU17;
+
+ //
+ //
+ //
+ UINT8 CPU18;
+ UINT8 CPU19;
+
+ //
+ //
+ //
+ UINT8 CPU20;
+ UINT8 CPU21;
+
+ //
+ //
+ //
+ UINT8 CPU22;
+ UINT8 CPU23;
+
+ //
+ //
+ //
+ UINT8 CPU24;
+ UINT8 CPU25;
+
+ //
+ //
+ //
+ UINT8 CPU26;
+ UINT8 CPU27;
+
+ //
+ //
+ //
+ UINT8 CPU28;
+ UINT8 CPU29;
+
+ //
+ //
+ //
+ UINT8 CPU30;
+ UINT8 CPU31;
+
+ //
+ //
+ //
+ UINT8 CPU32;
+ UINT8 CPU33;
+
+ //
+ //
+ //
+ UINT8 CPU34;
+ UINT8 CPU35;
+
+ //
+ //
+ //
+ UINT8 CPU36;
+ UINT8 CPU37;
+
+ //
+ //
+ //
+ UINT8 CPU38;
+ UINT8 CPU39;
+
+ //
+ //
+ //
+ UINT16 CPU40;
+ UINT8 CPU41;
+
+ //
+ //
+ //
+ UINT8 CPU42;
+ UINT8 CPU43;
+
+ //
+ //
+ //
+ UINT16 CPU44;
+ UINT8 CPU45;
+
+ //
+ //
+ //
+ UINT8 CPU46;
+ UINT8 CPU47;
+
+ //
+ //
+ //
+ UINT8 CPU48;
+ UINT8 CPU49;
+
+ //
+ //
+ //
+ UINT8 CPU50;
+ UINT8 CPU51;
+
+ //
+ //
+ //
+ UINT8 CPU52;
+ UINT8 CPU53;
+
+ //
+ //
+ //
+ UINT8 CPU54;
+ UINT8 CPU55;
+
+ //
+ //
+ //
+ UINT8 CPU56;
+ UINT8 CPU57;
+
+ //
+ //
+ //
+ UINT8 CPU58;
+ UINT8 CPU59;
+
+ //
+ //
+ //
+ UINT8 CPU60;
+ UINT8 CPU61;
+
+ //
+ //
+ //
+ UINT8 CPU62;
+ UINT8 CPU63;
+
+ //
+ //
+ //
+ UINT8 CPU64;
+ UINT8 CPU65;
+
+ //
+ //
+ //
+ UINT8 CPU66;
+ UINT8 CPU67;
+
+ //
+ //
+ //
+ UINT16 CPU68;
+ UINT8 CPU69;
+
+ //
+ //
+ //
+ UINT16 CPU70;
+
+ //
+ //
+ //
+ UINT8 CPU71;
+
+ //
+ //
+ //
+ UINT8 MEM00;
+ UINT8 MEM01;
+
+ //
+ //
+ //
+ UINT8 MEM02;
+ UINT8 MEM03;
+
+ UINT16 MEM04;
+ UINT8 MEM05;
+
+ UINT8 MEM06;
+ UINT8 MEM07;
+
+ UINT8 MEM08;
+ UINT8 MEM09;
+
+ UINT8 MEM10;
+ UINT8 MEM11;
+
+ UINT8 MEM12;
+ UINT8 MEM13;
+
+ UINT8 MEM14;
+ UINT8 MEM15;
+
+ UINT8 MEM16;
+ UINT8 MEM17;
+
+ UINT16 MEM18;
+ UINT8 MEM19;
+
+ UINT8 MEM20;
+ UINT8 MEM21;
+
+ UINT8 MEM22;
+ UINT8 MEM23;
+
+ UINT8 MEM24;
+ UINT8 MEM25;
+
+ UINT8 MEM26;
+ UINT8 MEM27;
+
+ UINT8 MEM28;
+ UINT8 MEM29;
+
+ UINT8 MEM30;
+ UINT8 MEM31;
+
+ UINT8 MEM32;
+ UINT8 MEM33;
+
+ UINT8 MEM34;
+ UINT8 MEM35;
+
+ //
+ //
+ //
+ UINT8 MEM36;
+ UINT8 MEM37;
+ UINT8 MEM38;
+ UINT8 MEM39;
+
+ //
+ //
+ //
+ UINT8 MEM40;
+ UINT8 MEM41;
+ UINT8 MEM42;
+ UINT8 MEM43;
+ UINT8 MEM44;
+ UINT8 MEM45;
+ UINT8 MEM46;
+ UINT8 MEM47;
+
+
+ //
+ // Port 80 decode 0/1 - PCI/LPC
+ UINT8 Port80Route;
+ UINT8 Port80RouteLockHide;
+
+ //
+ // ECC Event Logging
+ //
+ UINT8 EccEventLogging;
+ UINT8 EccEventLoggingLockHide;
+
+ //
+ // TPM Enable/Disable
+ //
+ UINT8 ETpm;
+
+ //
+ // TPM question 0 = Disabled, 1 = Enabled
+ //
+ UINT8 ETpmClear;
+
+ //
+ // Secondary SATA Controller question 0 = Disabled, 1 = Enabled
+ //
+ UINT8 ExtSata;
+ UINT8 ExtSataLockHide;
+
+ //
+ // Mode selection for Secondary SATA Controller (0=IDE, 1=RAID)
+ //
+ UINT8 ExtSataMode;
+ UINT8 ExtSataModeLockHide;
+
+ //
+ // LT Technology 0/1 -> Disable/Enable
+ //
+ UINT8 LtTechnology;
+ UINT8 LtTechnologyLockHide;
+
+ //
+ // HPET Support 0/1 -> Disable/Enable
+ //
+ UINT8 Hpet;
+ UINT8 HpetLockHide;
+
+ //
+ // ICH Function Level Reset enable/disable
+ //
+ UINT8 FlrCapability;
+ UINT8 FlrCapabilityLockHide;
+
+ // VT-d Option
+ UINT8 VTdSupport;
+ UINT8 VTdSupportLockHide;
+
+ UINT8 InterruptRemap;
+ UINT8 InterruptRemapLockHide;
+
+ UINT8 Isoc;
+ UINT8 IsocLockHide;
+
+ UINT8 CoherencySupport;
+ UINT8 CoherencySupportLockHide;
+
+ UINT8 ATS;
+ UINT8 ATSLockHide;
+
+ UINT8 PassThroughDma;
+ UINT8 PassThroughDmaLockHide;
+
+ //
+ // IGD option
+ //
+ UINT8 GraphicsDriverMemorySize;
+ UINT8 GraphicsDriverMemorySizeLockHide;
+
+
+ //
+ // Discrete SATA Type (Ide, Raid, Ahci)
+ //
+ UINT8 ExtSataMode2;
+ UINT8 ExtSataMode2LockHide;
+
+ UINT8 ProcessorReserve00;
+ UINT8 ProcessorReserve01;
+
+ //
+ // IGD Aperture Size question
+ //
+ UINT8 IgdApertureSize;
+ UINT8 IgdApertureSizeLockHide;
+
+ //
+ // Boot Display Device
+ //
+ UINT8 BootDisplayDevice;
+ UINT8 BootDisplayDeviceLockHide;
+
+
+ //
+ // System fan speed duty cycle
+ //
+ UINT8 SystemFanDuty;
+ UINT8 SystemFanDutyLockHide;
+
+
+ //
+ // S3 state LED indicator
+ //
+ UINT8 S3StateIndicator;
+ UINT8 S3StateIndicatorLockHide;
+
+ //
+ // S1 state LED indicator
+ //
+ UINT8 S1StateIndicator;
+ UINT8 S1StateIndicatorLockHide;
+
+ //
+ // PS/2 Wake from S5
+ //
+ UINT8 WakeOnS5Keyboard;
+ UINT8 WakeOnS5KeyboardLockHide;
+
+
+ //
+ // SATA Controller question 0 = Disabled, 1 = Enabled
+ //
+ UINT8 Sata;
+ UINT8 SataLockHide;
+
+ //
+ // PS2 port
+ //
+ UINT8 PS2;
+
+ //
+ // No VideoBeep
+ //
+ UINT8 NoVideoBeepEnable;
+
+ //
+ // Integrated Graphics Device
+ //
+ UINT8 Igd;
+
+ //
+ // Video Device select order
+ //
+ UINT8 VideoSelectOrder[8];
+
+ // Flash update sleep delay
+ UINT8 FlashSleepDelay;
+ UINT8 FlashSleepDelayLockHide;
+
+ //
+ // Boot Display Device2
+ //
+ UINT8 BootDisplayDevice2;
+ UINT8 BootDisplayDevice2LockHide;
+
+ //
+ // Flat Panel
+ //
+ UINT8 EdpInterfaceType;
+ UINT8 EdpInterfaceTypeLockHide;
+
+ UINT8 LvdsInterfaceType;
+ UINT8 LvdsInterfaceTypeLockHide;
+
+ UINT8 ColorDepth;
+ UINT8 ColorDepthLockHide;
+
+ UINT8 EdidConfiguration;
+ UINT8 EdidConfigurationLockHide;
+
+ UINT8 PwmReserved;
+ UINT8 MaxInverterPWMLockHide;
+
+ UINT8 PreDefinedEdidConfiguration;
+ UINT8 PreDefinedEdidConfigurationLockHide;
+
+ UINT16 ScreenBrightnessResponseTime;
+ UINT8 ScreenBrightnessResponseTimeLockHide;
+
+ UINT8 Serial3;
+ UINT8 Serial3LockHide;
+
+ UINT8 Serial4;
+ UINT8 Serial4LockHide;
+
+ UINT8 CurrentSetupProfile;
+ UINT8 CurrentSetupProfileLockHide;
+
+ //
+ // FSC system Variable
+ //
+ UINT8 CPUFanUsage;
+ UINT8 CPUFanUsageLockHide;
+ UINT16 CPUUnderSpeedthreshold;
+ UINT8 CPUUnderSpeedthresholdLockHide;
+ UINT8 CPUFanControlMode;
+ UINT8 CPUFanControlModeLockHide;
+ UINT16 Voltage12UnderVolts;
+ UINT8 Voltage12UnderVoltsLockHide;
+ UINT16 Voltage12OverVolts;
+ UINT8 Voltage12OverVoltsLockHide;
+ UINT16 Voltage5UnderVolts;
+ UINT8 Voltage5UnderVoltsLockHide;
+ UINT16 Voltage5OverVolts;
+ UINT8 Voltage5OverVoltsLockHide;
+ UINT16 Voltage3p3UnderVolts;
+ UINT8 Voltage3p3UnderVoltsLockHide;
+ UINT16 Voltage3p3OverVolts;
+ UINT8 Voltage3p3OverVoltsLockHide;
+ UINT16 Voltage2p5UnderVolts;
+ UINT8 Voltage2p5UnderVoltsLockHide;
+ UINT16 Voltage2p5OverVolts;
+ UINT8 Voltage2p5OverVoltsLockHide;
+ UINT16 VoltageVccpUnderVolts;
+ UINT8 VoltageVccpUnderVoltsLockHide;
+ UINT16 VoltageVccpOverVolts;
+ UINT8 VoltageVccpOverVoltsLockHide;
+ UINT16 Voltage5BackupUnderVolts;
+ UINT8 Voltage5BackupUnderVoltsLockHide;
+ UINT16 Voltage5BackupOverVolts;
+ UINT8 Voltage5BackupOverVoltsLockHide;
+ UINT16 VS3p3StbyUnderVolt;
+ UINT8 VS3p3StbyUnderVoltLockHide;
+ UINT16 VS3p3StbyOverVolt;
+ UINT8 VS3p3StbyOverVoltLockHide;
+ UINT8 CPUFanMinDutyCycle;
+ UINT8 CPUFanMinDutyCycleLockHide;
+ UINT8 CPUFanMaxDutyCycle;
+ UINT8 CPUFanMaxDutyCycleLockHide;
+ UINT8 CPUFanOnDutyCycle;
+ UINT8 CPUFanOnDutyCycleLockHide;
+ UINT16 CpuOverTemp;
+ UINT8 CpuOverTempLockHide;
+ UINT16 CpuControlTemp;
+ UINT8 CpuControlTempLockHide;
+ UINT16 CpuAllOnTemp;
+ UINT8 CpuAllOnTempLockHide;
+ UINT8 CpuResponsiveness;
+ UINT8 CpuResponsivenessLockHide;
+ UINT8 CpuDamping;
+ UINT8 CpuDampingLockHide;
+ UINT16 PchOverTemp;
+ UINT8 PchOverTempLockHide;
+ UINT16 PchControlTemp;
+ UINT8 PchControlTempLockHide;
+ UINT16 PchAllOnTemp;
+ UINT8 PchAllOnTempLockHide;
+ UINT8 PchResponsiveness;
+ UINT8 PchResponsivenessLockHide;
+ UINT8 PchDamping;
+ UINT8 PchDampingLockHide;
+ UINT16 MemoryOverTemp;
+ UINT8 MemoryOverTempLockHide;
+ UINT16 MemoryControlTemp;
+ UINT8 MemoryControlTempLockHide;
+ UINT16 MemoryAllOnTemp;
+ UINT8 MemoryAllOnTempLockHide;
+ UINT8 MemoryResponsiveness;
+ UINT8 MemoryResponsivenessLockHide;
+ UINT8 MemoryDamping;
+ UINT8 MemoryDampingLockHide;
+ UINT16 VROverTemp;
+ UINT8 VROverTempLockHide;
+ UINT16 VRControlTemp;
+ UINT8 VRControlTempLockHide;
+ UINT16 VRAllOnTemp;
+ UINT8 VRAllOnTempLockHide;
+ UINT8 VRResponsiveness;
+ UINT8 VRResponsivenessLockHide;
+ UINT8 VRDamping;
+ UINT8 VRDampingLockHide;
+
+ UINT8 LvdsBrightnessSteps;
+ UINT8 LvdsBrightnessStepsLockHide;
+ UINT8 EdpDataRate;
+ UINT8 EdpDataRateLockHide;
+ UINT16 LvdsPowerOnToBacklightEnableDelayTime;
+ UINT8 LvdsPowerOnToBacklightEnableDelayTimeLockHide;
+ UINT16 LvdsPowerOnDelayTime;
+ UINT8 LvdsPowerOnDelayTimeLockHide;
+ UINT16 LvdsBacklightOffToPowerDownDelayTime;
+ UINT8 LvdsBacklightOffToPowerDownDelayTimeLockHide;
+ UINT16 LvdsPowerDownDelayTime;
+ UINT8 LvdsPowerDownDelayTimeLockHide;
+ UINT16 LvdsPowerCycleDelayTime;
+ UINT8 LvdsPowerCycleDelayTimeLockHide;
+
+ UINT8 IgdFlatPanel;
+ UINT8 IgdFlatPanelLockHide;
+ UINT8 Lan2;
+ UINT8 Lan2LockHide;
+
+ UINT8 SwapMode;
+ UINT8 SwapModeLockHide;
+
+ UINT8 Sata0HotPlugCap;
+ UINT8 Sata0HotPlugCapLockHide;
+ UINT8 Sata1HotPlugCap;
+ UINT8 Sata1HotPlugCapLockHide;
+
+ UINT8 UsbCharging;
+ UINT8 UsbChargingLockHide;
+
+ UINT8 Cstates;
+ UINT8 EnableC4;
+ UINT8 EnableC6;
+
+ UINT8 FastBoot;
+ UINT8 EfiNetworkSupport;
+ UINT8 PxeRom;
+
+ //Add for PpmPlatformPlicy
+ UINT8 PPM00;
+ UINT8 PPM01;
+ UINT8 PPM02;
+ UINT8 PPM03;
+ UINT8 PPM04;
+ UINT8 PPM05;
+ UINT8 PPM06;
+ UINT8 PPM07;
+ UINT8 PPM08;
+ UINT8 PPM09;
+ UINT8 PPM10;
+ UINT8 QuietBoot;
+ UINT8 LegacyUSBBooting;
+
+ UINT8 PwmReserved02;
+ //
+ // Thermal Policy Values
+ //
+ UINT8 EnableDigitalThermalSensor;
+ UINT8 PassiveThermalTripPoint;
+ UINT8 PassiveTc1Value;
+ UINT8 PassiveTc2Value;
+ UINT8 PassiveTspValue;
+ UINT8 DisableActiveTripPoints;
+ UINT8 CriticalThermalTripPoint;
+ UINT8 IchPciExp[4];
+ UINT8 DeepStandby;
+ UINT8 AlsEnable;
+ UINT8 IgdLcdIBia;
+ UINT8 LogBootTime;
+
+
+ UINT8 PcieRootPortIOApic[4];
+ UINT8 IffsEnable;
+ UINT8 IffsOnS3RtcWake;
+ UINT8 IffsS3WakeTimerMin;
+ UINT8 IffsOnS3CritBattWake;
+ UINT8 IffsCritBattWakeThreshold;
+ UINT8 ScramblerSupport;
+ UINT8 SecureBoot;
+ UINT8 SecureBootCustomMode;
+ UINT8 SecureBootUserPhysicalPresent;
+ UINT8 CoreFreMultipSelect;
+ UINT8 MaxCState;
+ UINT8 PanelScaling;
+ UINT8 IgdLcdIGmchBlc;
+ UINT8 GfxBoost;
+ UINT8 IgdThermal;
+ UINT8 SEC00;
+ UINT8 SEC01;
+ UINT8 SEC02;
+ UINT8 SEC03;
+ UINT8 MeasuredBootEnable;
+ UINT8 UseProductKey;
+ //Image Signal Processor PCI Device Configuration
+ //
+ UINT8 ISPDevSel;
+ UINT8 ISPEn;
+ // Passwords
+ UINT16 UserPassword[PASSWORD_MAX_SIZE];
+ UINT16 AdminPassword[PASSWORD_MAX_SIZE];
+ UINT8 Tdt;
+ UINT8 Recovery;
+ UINT8 Suspend;
+ UINT8 TdtState;
+ UINT8 TdtEnrolled;
+ UINT8 PBAEnable;
+
+ UINT8 HpetBootTime;
+ UINT8 UsbDebug;
+ UINT8 Lpe;
+ //
+ // LPSS Configuration
+ //
+ UINT8 LpssPciModeEnabled;
+ //Scc
+ UINT8 LpsseMMCEnabled;
+ UINT8 LpssSdioEnabled;
+ UINT8 LpssSdcardEnabled;
+ UINT8 LpssSdCardSDR25Enabled;
+ UINT8 LpssSdCardDDR50Enabled;
+ UINT8 LpssMipiHsi;
+ UINT8 LpsseMMC45Enabled;
+ UINT8 LpsseMMC45DDR50Enabled;
+ UINT8 LpsseMMC45HS200Enabled;
+ UINT8 LpsseMMC45RetuneTimerValue;
+ UINT8 eMMCBootMode;
+
+ //LPSS2
+ UINT8 LpssDma1Enabled;
+ UINT8 LpssI2C0Enabled;
+ UINT8 LpssI2C1Enabled;
+ UINT8 LpssI2C2Enabled;
+ UINT8 LpssI2C3Enabled;
+ UINT8 LpssI2C4Enabled;
+ UINT8 LpssI2C5Enabled;
+ UINT8 LpssI2C6Enabled;
+ //LPSS1
+ UINT8 LpssDma0Enabled;
+ UINT8 LpssPwm0Enabled;
+ UINT8 LpssPwm1Enabled;
+ UINT8 LpssHsuart0Enabled;
+ UINT8 LpssHsuart1Enabled;
+ UINT8 LpssSpiEnabled;
+ UINT8 I2CTouchAd;
+
+ UINT8 GTTSize;
+ //
+ // DVMT5.0 Graphic memory setting
+ //
+ UINT8 IgdDvmt50PreAlloc;
+ UINT8 IgdDvmt50TotalAlloc;
+ UINT8 IgdTurboEnabled;
+
+ //
+ // Usb Config
+ //
+ UINT8 UsbAutoMode; // PCH controller Auto mode
+ UINT8 UsbXhciSupport;
+ UINT8 Hsic0;
+ UINT8 PchUsb30Mode;
+ UINT8 PchUsb30Streams;
+ UINT8 PchUsb20;
+ UINT8 PchUsbPerPortCtl;
+ UINT8 PchUsbPort[8];
+ UINT8 PchUsbRmh;
+ UINT8 PchUsbOtg;
+ UINT8 PchUsbVbusOn; //OTG VBUS control
+ UINT8 PchFSAOn; //FSA control
+ UINT8 EhciPllCfgEnable;
+
+
+ //Gbe
+ UINT8 PcieRootPortSpeed[PCH_PCIE_MAX_ROOT_PORTS];
+ UINT8 SlpLanLowDc;
+
+ UINT8 ISCT00;
+ UINT8 ISCT01;
+ UINT8 ISCT02;
+ UINT8 ISCT03;
+ UINT8 ISCT04;
+ UINT8 ISCT05;
+ UINT8 ISCT06;
+ UINT8 ISCT07;
+ //
+ // Azalia Configuration
+ //
+ UINT8 PchAzalia;
+ UINT8 AzaliaVCiEnable;
+ UINT8 AzaliaDs;
+ UINT8 AzaliaPme;
+ UINT8 HdmiCodec;
+
+ UINT8 UartInterface;
+ UINT8 PcuUart1;
+ //UINT8 PcuUart2;//for A0
+ UINT8 StateAfterG3;
+ UINT8 EnableClockSpreadSpec;
+ UINT8 GraphicReserve00;
+ UINT8 GOPEnable;
+ UINT8 GOPBrightnessLevel; //Gop Brightness level
+ UINT8 PavpMode;
+ UINT8 SEC04;
+ UINT8 SEC05;
+ UINT8 SEC06;
+ UINT8 SEC07;
+
+ UINT8 HdmiCodecPortB;
+ UINT8 HdmiCodecPortC;
+ UINT8 HdmiCodecPortD;
+ UINT8 LidStatus;
+ UINT8 Reserved00;
+ UINT8 Reserved01;
+ UINT16 Reserved02;
+ UINT16 Reserved03;
+ UINT16 Reserved04;
+ UINT16 Reserved05;
+ UINT16 Reserved06;
+ UINT16 Reserved07;
+ UINT16 Reserved08;
+ UINT16 Reserved09;
+ UINT16 Reserved0A;
+ UINT16 Reserved0B;
+ UINT16 Reserved0C;
+ UINT16 Reserved0D;
+ UINT8 Reserved0E;
+ UINT8 Reserved0F;
+ UINT32 Reserved10;
+ UINT32 Reserved11;
+ UINT32 Reserved12;
+ UINT32 Reserved13;
+ UINT32 Reserved14;
+ UINT8 Reserved15;
+ UINT8 Reserved16;
+ UINT8 Reserved17;
+ UINT8 Reserved18;
+ UINT8 Reserved19;
+ UINT8 Reserved1A;
+ UINT8 Reserved1B;
+ UINT8 Reserved1C;
+ UINT8 Reserved1D;
+ UINT8 Reserved1E;
+ UINT8 Reserved1F;
+ UINT8 Reserved20;
+ UINT8 PmicEnable;
+ UINT8 IdleReserve;
+ UINT8 TSEGSizeSel;
+ UINT8 ACPIMemDbg;
+ UINT8 ExISupport;
+ UINT8 BatteryChargingSolution; //0-non ULPMC 1-ULPMC
+ UINT8 PnpSettings;
+ UINT8 CfioPnpSettings;
+ UINT8 PchEhciDebug;
+ UINT8 CRIDSettings;
+ UINT8 ULPMCFWLock;
+ UINT8 SpiRwProtect;
+ UINT8 GraphicReserve02;
+ UINT8 PDMConfig;
+ UINT16 LmMemSize;
+ UINT8 PunitBIOSConfig;
+ UINT8 LpssSdioMode;
+ UINT8 ENDBG2;
+ UINT8 WittEnable;
+ UINT8 UtsEnable;
+ UINT8 TristateLpc;
+ UINT8 GraphicReserve05;
+ UINT8 UsbXhciLpmSupport;
+ UINT8 EnableAESNI;
+ UINT8 SecureErase;
+
+ UINT8 MmioSize;
+
+
+ UINT8 SAR1;
+
+ UINT8 DisableCodec262;
+ UINT8 ReservedO;
+ UINT8 PcieDynamicGating; // Need PMC enable it first from PMC 0x3_12 MCU 318.
+
+ UINT8 MipiDsi;
+
+ //Added flow control item for UART1 and UART2
+ UINT8 LpssHsuart0FlowControlEnabled;
+ UINT8 LpssHsuart1FlowControlEnabled;
+
+ UINT8 SdCardRemovable; // ACPI reporting MMC/SD media as: removable/non-removable
+
+ UINT8 GpioWakeCapability;
+
+} SYSTEM_CONFIGURATION;
+#pragma pack()
+
+#ifndef PLATFORM_SETUP_VARIABLE_NAME
+#define PLATFORM_SETUP_VARIABLE_NAME L"Setup"
+#endif
+
+#pragma pack(1)
+typedef struct{
+ // Passwords
+ UINT16 UserPassword[PASSWORD_MAX_SIZE];
+ UINT16 AdminPassword[PASSWORD_MAX_SIZE];
+ UINT16 DummyDataForVfrBug; // Don't change or use
+
+} SYSTEM_PASSWORDS;
+#pragma pack()
+
+//
+// #defines for Drive Presence
+//
+#define EFI_HDD_PRESENT 0x01
+#define EFI_HDD_NOT_PRESENT 0x00
+#define EFI_CD_PRESENT 0x02
+#define EFI_CD_NOT_PRESENT 0x00
+
+#define EFI_HDD_WARNING_ON 0x01
+#define EFI_CD_WARNING_ON 0x02
+#define EFI_SMART_WARNING_ON 0x04
+#define EFI_HDD_WARNING_OFF 0x00
+#define EFI_CD_WARNING_OFF 0x00
+#define EFI_SMART_WARNING_OFF 0x00
+
+#ifndef VFRCOMPILE
+extern EFI_GUID gEfiSetupVariableGuid;
+#endif
+
+#define SETUP_DATA SYSTEM_CONFIGURATION
+
+#endif // #ifndef _SETUP_VARIABLE
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-03 05:49:20 +0000