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2016-12-20MdeModulePkg/NonDiscoverableDeviceRegistrationLib: Fix coding style issuesDandan Bi
1. Fix issues in comments 2. Fix Guid/protocol format Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-12-20MdeModulePkg/SataControllerDxe: Fix coding style issueDandan Bi
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-20MdeModulePkg/TerminalDxe: Initialize variable after declarationDandan Bi
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-20MdeModulePkg/EmmcDxe: Avoid Non-Boolean type used as BooleanDandan Bi
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-12-20MdeModulePkg/EbcDxe: Make variable name follow rulesDandan Bi
For variable name, it should contain lower case characters. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-20MdeModulePkg/CapsuleApp: Fix Guid format issuesDandan Bi
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-20IntelSiliconPkg: Fix format issuesDandan Bi
1. Fix doxygen formt 2. Fix Guid format Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-20SecurityPkg/FmpAuthenticationLib: Fix Guid format issuesDandan Bi
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-20IntelSiliconPkg: 0468303 caused to breaking the SMBIOS tables generation codeChan, Amy
Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Chiu, Chasel <chasel.chiu@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chan, Amy <amy.chan@intel.com> System test: Smbios tables are correctly published on an intel internal platform. .../DxeSmbiosDataHobLib/DxeSmbiosDataHobLib.c | 134 +++------------------ 1 file changed, 14 insertions(+), 120 deletions(-)
2016-12-20UefiCpuPkg/ArchitecturalMsr.h: Remove non-Ascii charactersHao Wu
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-12-20BaseTools: Correct bin wrappers for GenDepex.py pathYonghong Zhu
The WindowsLike and PosixLike bin wrappers for GenDepex.py do not use correct path. GenDepex.py is not in a GenDepex directory. Instead, it is in the AutoGen directory. Fixes: https://bugzilla.tianocore.org/show_bug.cgi?id=292 Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-12-19ShellBinPkg: New Shell binaries for IA32 and X64Ruiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-12-19FatBinPkg: New EnhancedFatDxe binaries for IA32, X64, EBC and IPFRuiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-12-19UefiCpuPkg/PiSmmCpu: Add SMM Comm Buffer Paging Protection.Jiewen Yao
This patch sets the normal OS buffer EfiLoaderCode/Data, EfiBootServicesCode/Data, EfiConventionalMemory, EfiACPIReclaimMemory to be not present after SmmReadyToLock. To access these region in OS runtime phase is not a good solution. Previously, we did similar check in SmmMemLib to help SMI handler do the check. But if SMI handler forgets the check, it can still access these OS region and bring risk. So here we enforce the policy to prevent it happening. Cc: Jeff Fan <jeff.fan@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-19UefiCpuPkg/SmmCpuFeaturesLibStm: Add STM library instanceMichael Kinney
Add a new instances of the SmmCpuFeaturesLib that is used by platforms to enable the SMI Transfer Monitor(STM) feature. This new instance is in the same directory as the default SmmCpuFeaturesLib instance in order to share source files. The DSC file is updated to build both SmmCpuFeatureLib instances and to build two versions of the PiSmmCpuDxeSmm module using each of the SmmCpuFeatureLib instances. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-19UefiCpuPkg/SmmCpuFeaturesLib: Split into two filesMichael Kinney
Split the default implementation of the SmmCpuFeaturesLib into two files to prepare for the addition of the STM specific SmmCpuFeaturesLib implementation. The STM specific implementation installs a different SMI entry handler and initialize the MSEG specific MSR at the end of SmmCpuFeaturesInitializeProcessor(). This patch does not introduce any functional changes to the default implementation of the SmmCpuFeaturesLib. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-19UefiCpuPkg: Add STM GUIDs, Protocols, and PCDsMichael Kinney
* Add GUIDed HOB that described MSEG region in SMRAM * Add SM Monitor Init Protocol * Add PCD to configure size of SMM exception stack * Add PCD to configure MSEG region size if it is not described by the gMsegSmramGuid GUIDed HOB. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-19UefiCpuPkg/Include: Update MSEG structure commentsMichael Kinney
Add comments to describe fields of MSEG_HEADER and add define values for the MonitorFeatures field. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-19MdeModulePkg/NonDiscoverablePciDevice: Make variable definition follow ruleDandan Bi
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-12-19MdeModulePkg/NonDiscoverablePciDeviceDxe: Add comments for functionsDandan Bi
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-12-19MdeModulePkg/NonDiscoverablePciDeviceDxe: Fix VS2010/2012 build failureDandan Bi
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-12-19NetworkPkg: Replace ASSERT with error return code in PXE and HTTP boot driver.Fu Siyuan
This patch remove the ASSERT when receive a DHCP packet large than the maximum cache buffer size. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com> Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
2016-12-19MdeModulePkg: Replace ASSERT with error return code in PXE driver.Fu Siyuan
This patch remove the ASSERT when receive a DHCP packet large than the maximum cache buffer size. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Fu Siyuan <siyuan.fu@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com> Reviewed-by: Wu Jiaxin <jiaxin.wu@intel.com>
2016-12-18Omap35xxPkg/PciEmulation: port to new non-discoverable device infrastructureArd Biesheuvel
Move to the new non-discoverable device protocols for wiring the PCI based EHCI controller driver to the non-discoverable EHCI controller found on the OMAP 3530. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-12-16SecurityPkg: Tcg2Dxe: Report correct FinalEventLog sizeZhang, Chao B
Update debug log to report correct FinalEventLog size. Cc: Yao Jiewen <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Chao Zhang <chao.b.zhang@intel.com> Reviewed-by: Yao Jiewen <jiewen.yao@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
2016-12-16UefiCpuPkg/Cpuid.h: Update CPUID definitions with SDM (Sep.2016)Hao Wu
https://bugzilla.tianocore.org/show_bug.cgi?id=176 Update CPUID leaf and sub-leaf indexes and structures as described by Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A, September 2016, CPUID instruction. Summary of incompatible changes: 1. Field name changes in CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Bit 12 has been renamed from 'PQM' to 'RDT_M' and bit 15 has been renamed from 'PQE' to 'RDT_A'. 2. Stucture and filed name changes for 'CPUID Platform QoS Monitoring Information' related definitions Definition 'CPUID_PLATFORM_QOS_MONITORING' has been renamed to 'CPUID_INTEL_RDT_MONITORING'. Definition 'CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_MONITORING_ENUMERATION_SUB_LEAF'. Definition 'CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_MONITORING_L3_CACHE_SUB_LEAF'. 3. Stucture and filed name changes for 'CPUID Platform QoS Enforcement Information' related definitions Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION'. Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION_ENUMERATION_SUB_LEAF'. Definition 'CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF' has been renamed to 'CPUID_INTEL_RDT_ALLOCATION_L3_CACHE_SUB_LEAF'. This commit also updates the relating codes in UefiCpuPkg/Application/Cpuid to reflect the changes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-12-16UefiCpuPkg/Include: Add Goldmont MSR header file with SDM (Sep.2016)Hao Wu
https://bugzilla.tianocore.org/show_bug.cgi?id=176 Add the MSR header file of Goldmont processor according to Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.5. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-12-16UefiCpuPkg/Include: Update Skylake MSR header file with SDM (Sep.2016)Hao Wu
https://bugzilla.tianocore.org/show_bug.cgi?id=176 Update the MSR header file of Skylake processor according to Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR), Section 35.15. Summary of incompatible changes: 1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS has been renamed to IA32_PERF_GLOBAL_STATUS Typo 'STAUS' has been fixed in SDM. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-12-16UefiCpuPkg/Include: Update MSR header files with SDM (Sep.2016)Hao Wu
https://bugzilla.tianocore.org/show_bug.cgi?id=176 Update MSR header files of processors (excluding Goldmont and Skylake processors) according to Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3, September 2016, Chapter 35 Model-Specific-Registers (MSR). Summary of incompatible changes: General: 1. MSR (address 38EH) IA32_PERF_GLOBAL_STAUS in processor-specific header files has been removed or renamed to IA32_PERF_GLOBAL_STATUS Typo 'STAUS' has been fixed in SDM. If the MSR definition is the same with architectural MSR, we remove it. Otherwise, we rename the MSR. 2. MSRs (address starting from 400H) MSR_MC{X}_{XXX} (like MSR_MC4_STATUS) in processor-specific header files have been removed or renamed to IA32_MC{X}_{XXX} (like IA32_MC4_STATUS) Register name change from 'MSR_MC{X}_{XXX}' to 'IA32_MC{X}_{XXX}' in SDM. If the MSR definition is the same with architectural MSR, we remove it. Otherwise, we rename the MSR. Please note that for those MSRs still have name like 'MSR_MC{X}_{XXX}' in SDM are still kept in processor-specific header files. HaswellMsr.h: 1. MSR (address C80H) IA32_DEBUG_FEATURE has been removed Register name change from 'IA32_DEBUG_FEATURE' to 'IA32_DEBUG_INTERFACE' in SDM. Since the MSR definition is the same with architectural MSR, we remove it. SandyBridgeMsr.h: 1. MSR (address 391H) MSR_UNC_PERF_GLOBAL_CTRL, name change for bit fields 0:3 Bit description change from 'Core {X} select' to 'Slice {X} select' for bit 0:3 in SDM. SilvermontMsr.h: 1. MSR (address 2AH) MSR_EBL_CR_POWERON, structure definition changed Bit description for this MSR is totally changed in SDM, we modify the structure definition to align with it. XeonDMsr.h: 1. MSRs (address 630H to 632H) MSR_PKG_C8_RESIDENCY, MSR_PKG_C9_RESIDENCY and MSR_PKG_C10_RESIDENCY have been removed Those 3 MSRs are not defined for this processor in SDM, we remove them. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-12-16ShellPkg/setvar: Correct typo in setvar help messageRuiyu Ni
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
2016-12-16UefiCpuPkg/PiSmmCpuDxeSmm: Fix .S & .asm build failureFeng Tian
Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-15MdeModulePkg/NonDiscoverablePciDeviceDxe: add support for non-coherent DMAArd Biesheuvel
Add support for non-coherent DMA, either by performing explicit cache maintenance when DMA mappings are aligned to the CPU's DMA buffer alignment, or by bounce buffering via uncached mappings otherwise. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Tested-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
2016-12-14MdeModulePkg/CapsuleApp: Fix GUID/protocol format issuesDandan Bi
Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14MdeModulePkg: Add missing info string for PCDsDandan Bi
Some Pcds are added to the dec file, but miss to add the prompt&&help info to the uni file, now add them. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14MdeModulePkg: Make the comments align with the functionDandan Bi
Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14UefiCpuPkg/Capsule: Fix coding style issuesDandan Bi
Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14UefiCpuPkg/MicrocodeUpdateDxe: Fix coding style issues in INF fileDandan Bi
1. Add MicrocodeUpdate.h to the [Sources] section. 2. Fix the incorrect Guid/Protocol format issues. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14UefiCpuPkg: Add info string to UNI file for PcdCpuSmmStaticPageTableDandan Bi
Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14UefiCpuPkg: Make the comments align with the functionsDandan Bi
Cc: Jeff Fan <jeff.fan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
2016-12-14SignedCapsulePkg/IniParsingLib: Update struct nameDandan Bi
1. Change _SECTION_ITEM to _INI_SECTION_ITEM 2. Change _COMMENT_LINE to _INI_COMMENT_LINE Because _SECTION_ITEM and _COMMENT_LINE are duplicated with the one defined in IntelFrameworkModulePkg\Universal\ FirmwareVolume\UpdateDriverDxe\UpdateDriver.h Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14SignedCapsulePkg/SystemFirmwareUpdate: Add source file to INF fileDandan Bi
Add SystemFirmwareDxe.h to [Sources] section of INF file. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14SignedCapsulePkg/RecoveryModuleLoadPei: Add source file to INF fileDandan Bi
Add RecoveryModuleLoadPei.h to [Sources] section of INF file. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14SignedCapsulePkg/EdkiiSystemCapsuleLib: Fix coding style issues in INF fileDandan Bi
Fix incorrect Guid/Pcd format issues in INF file. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14SecurityPkg/OpalPasswordDxe: Make comments align with the functionDandan Bi
Cc: Eric Dong <eric.dong@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
2016-12-14SecurityPkg/FmpAuthenticationLibRsa2048Sha256: Fix Guid/pcd format issuesDandan Bi
Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14SecurityPkg/FmpAuthenticationLibPkcs7: Fix incorrect Guid formatDandan Bi
Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14Security:Add info string to UNI file for PcdPkcs7CertBufferDandan Bi
Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-12-14ShellPkg/UefiShellNetwork2CommandsLib: Fix incorrect Protocol formatDandan Bi
Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
2016-12-14ShellPkg/UefiShellNetwork1CommandsLib: Fix incorrect Protocol formatDandan Bi
Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
2016-12-14ShellPkg/UefiShellDebug1CommandsLib: Fix coding style issuesDandan Bi
Cc: Ruiyu Ni <ruiyu.ni@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Dandan Bi <dandan.bi@intel.com> Reviewed-by: Jaben Carsey <jaben.carsey@intel.com>
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