| Age | Commit message (Collapse) | Author |
|---|
|
ARM Generic Interrupt Controller is incorrectly named as
"ARM General Interrupt Controller" in ArmJuno.dsc,
ArmVExpress-CTA15-A7.dsc and ArmVExpress-FVP-AArch64.dsc.
This patch corrects the comment by changing "General" to "Generic".
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Evan Lloyd <Evan.Lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The default timeout value for the delay during which the splash screen
is shown and the BDS menu can be entered is still at 30 seconds, which
is rather long. Reduce it to 5 seconds instead.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Rename the variable holding the Styx PPTT table to mStyxPpttTable.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Table 13 of UEFI Specification 2.7A describes Timeout global
variable as NV (non-volatile), however
gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut
is defined in [PcdsFixedAtBuild.common] section of
Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc.
This prevents the timeout value from being persistent across
resets and power cycles, see BdsEntry() code in
MdeModulePkg/Universal/BdsDxe/BdsEntry.c:
//
// Initialize L"Timeout" EFI global variable.
//
BootTimeOut = PcdGet16 (PcdPlatformBootTimeOut);
This patch fixes the above issue by mapping PcdPlatformBootTimeOut
to global NV variable "Timeout" as a PcdsDynamicHii PCD.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
Reviewed-by: Evan Lloyd <Evan.Lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
Add a ACPI Processor Properties Topology Table (PPTT) to the SynQuacer
builds. This information is used by the OS to tune the scheduler.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Replace the PMU compatible string "arm,armv8-pmuv3" with the more
precise "arm,cortex-a53-pmu", potentially making more event types
available.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
As reported by Kojima-san, the PHY reference clock value we use in our
ACPI and DT descriptions is out of sync with the hardware. Replace
125 MHz with 250 MHz throughout.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The FVP_PLATFORM_TIMER_COUNT is the sum of the memory
mapped platform timers and the watchdog timers.
The watchdog timers can be disabled by setting the
FVP_WATCHDOG_COUNT (defined by PcdWatchdogCount)
to zero.
On the VExpress platform, if the FVP_WATCHDOG_COUNT is
set to zero, the FVP_PLATFORM_TIMER_COUNT is 1 as
VExpress has one memory mapped timer.
The code however incorrectly sets the platform timer
offset to zero in the GTDT. This causes the OS to read
the platform timer information from an invalid offset,
and may crash.
Updated the GTDT table to set the platform timer offset
to zero only when the FVP_PLATFORM_TIMER_COUNT is zero.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Reviewed-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
The correct load order for the NOR Flash driver and Runtime Variables
to work is as below:
1. Arm CPU Architecture Protocol Dxe
2. NOR Flash Dxe
3. Runtime Variable Dxe
NvVarStoreFormattedLib was recently introduced to resolve the dependency
order. This patch propagates the necessary changes for ARM VExpress
CTA15+A7 platform and also fixes the "Firmware Volume for Variable Store
is corrupted" error seen when the Flash is erased (or not formatted).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
The correct load order for the NOR Flash driver and Runtime Variables
to work is as below:
1. Arm CPU Architecture Protocol Dxe
2. NOR Flash Dxe
3. Runtime Variable Dxe
NvVarStoreFormattedLib was recently introduced to resolve the dependency
order. This patch propagates the necessary changes for ARM FVP platform
and also fixes the "Firmware Volume for Variable Store is corrupted" error
seen when the Flash is erased (or not formatted).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
The correct load order for the NOR Flash driver and Runtime Variables
to work is as below:
1. Arm CPU Architecture Protocol Dxe
2. NOR Flash Dxe
3. Runtime Variable Dxe
NvVarStoreFormattedLib was recently introduced to resolve the dependency
order. This patch propagates the necessary changes for ARM Juno platform
and also fixes the "Firmware Volume for Variable Store is corrupted" error
seen when the Flash is erased (or not formatted).
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Alexei Fedorov <alexei.fedorov@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
This change adds the HDLCD platform lib for the Juno plaform. This
library will be instantiated as a LcdPlatformLib to link with
LcdGraphicsOutputDxe for the Juno platform.
HDLCD platform library depends on the Arm SCMI DXE driver for
communication with the SCP for clock setting. Therefore this change also
enables building of Arm SCMI DXE driver for the Juno platform.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
This change adds a new Mailbox Transport Layer library for the Juno
platform. This library is required for ArmScmiDxe driver communication
with the SCP.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
This change adds LcdPlatformLib implementation for Arm Mali
DP500/DP500/DP650 display processors for models (with DP550 support).
NOTE: Versions for actual hardware are liable to require extra handling
for clock input changes, etc.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The framebuffer memory is set with flag
EFI_MEMORY_WC (uncached, unbuffered) which causes framebuffer memory
with eXecute bit set. Framebuffer memory having executable bit
set is a security hazard. This fix adds EFI_MEMORY_XP flag to avoid this.
Unfortunately function gDS->SetMemorySpaceAttributes() causes assertion due
to unsupported EFI_MEMORY_XP type. Therefore this fix replaces
gDS->SetMemorySpaceAttributes() with Cpu->SetMemoryAttributes().
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
This change uses two PCDs, PcdArmLcdFrameBufferBase and
PcdArmLcdFrameBufferSize introduced in correspondiong EDK2 patch to
reserve framebuffer in DRAM if these values are defined in platform
specific DSC file, avoiding the need to allocate dynamically.
This allows the framebuffer to appear as "I/O memory" outside of the
normal RAM map, which is similar to the "VRAM" case.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
As per the UEFI specification(2.7) section 12.9, the GOP framebuffer
memory can be accessed in the pre-boot and the post boot phase (by OS)
Therefore the memory type EfiBootServicesData which may no longer exist
after ExitBootServices is incorrect for the framebuffer memory
allocation. Change EfiBootServicesData with EfiReservedMemoryType
so that allocated memory can be accessed in the post boot phase.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Current HDLCD and PL111 platform libraries do not support display modes
with PixelBlueGreenRedReserved8BitPerColor format, i.e. because of
historical confusion, they do not support the UEFI default
PixelBlueGreenRedReserved8BitPerColor
LcdPlatformLib for PL111, LcdPlatformQueryMode function returns the
pixel format as PixelRedGreenBlueReserved8BitPerColor which is wrong,
because that does not match the display controller's pixel format which
is set to BGR in PL111Lcd GOP driver.
Also it is not possible to configure pixel format as RGB/BGR for the
display modes for a platform at build time.
This change adds PcdGopPixelFormat to configure pixel format as
PixelRedGreenBlueReserved8BitPerColor or
PixelBlueGreenRedReserved8BitPerColor or
PixelBitMask.
With this change, pixel format can be selected in the platform specific
.dsc file for all supported display modes.
Support for PixelBitMask is not implemented in PL111 or HDLCD
GOP driver, hence HDLCD and PL111 platform libraries will return error
EFI_UNSUPPORTED if PcdGopPixelFormat is set to PixelBitMask.
Indeed, it is not clear what selecting PixelBitMask might mean, but
the option is allowed as it might suit a custom platform.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The LcdPlatformGetTimings interface function takes similar sets of
multiple parameters for horizontal and vertical timings which can be
aggregated in a common data type. This change defines a structure
SCAN_TIMINGS for this which can be used to describe both horizontal and
vertical scan timings, and accordingly redefines the
LcdPlatformGetTiming interface, greatly reducing the amount of data
passed about.
Similarly the mode definition tables are also changed to use this data
type and thus enable pass through access.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Because of copy/paste effects, HdLcdArmVExpress.c contained a
table entry "LCD_BPP Bpp;" specifying the Bits per Pixel for each mode.
However, all modes are LCD_BITS_PER_PIXEL_24.
This change removes the table entry and related use of the field.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
None of the ArmPlatformSys* functions returns EFI_TIMEOUT. Hence checking
this in the do {} while loop in LcdPlatformSetMode is wrong. Therefore
remove this comparision and as a result remove the do {} while loop.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
This change replaces PcdGet32 with FixedPcdGet32 for the PCDs which
are defined as fixed PCDs.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
This minor change removes some unecessary initializations and variables
in PL111LcdArmVExpress.c and redudant return status checks in
HdLcdArmVExpress.c
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
This change adds some debug assertions e.g to catch NULL pointer errors
missing in PL11Lcd and HdLcd platform libraries.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
PCD PcdPL111LcdMaxMode is not used in HDLCD platform library.
Presence of this PCD in HDLCD is probably due to copy/paste code
from PL111 Lcd platform library. This change removes it from
the HdLcdArmVExpressLib.inf file.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
There is no functional modification in this change.
In this change some comments in HDLCD and PL111LCD platform library
code are modified and a few new comments are added. This is to
prevent mixing formatting changes with functional changes.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
There is no functional modification in this change
As preparation for further work, the formatting is corrected to meet
the EDKII coding standard.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
This change fixes incorrect MODULE_TYPE of HDLCD and PL111
LcdPlatformLibs. Currently set MODUL_TYPE DXE_DRIVER is incorrect
for these platform libraries. Hence set this to type BASE.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Girish Pathak <girish.pathak@arm.com>
Signed-off-by: Evan Lloyd <evan.lloyd@arm.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Turn off PcdHiiOsRuntimeSupport to fix hanging issue while enter
shell with some mellanox net cards.The option ROM of card loads an
empty interface to the gEfiHiiConfigAccessProtocolGuid.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ming Huang <huangming23@huawei.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Change DmaLib from NonCoherentDmaLib to CoherentDmaLib for support
cache consistency.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Wang Yue <wangyue41@huawei.com>
Signed-off-by: Ming Huang <ming.huang@linaro.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Sm750Dxe is a generic PCIe device driver for SM750 VGA device and it
is not necessary to maintain two different binary images for D03 and
D05 respectively.
This patch depends on another patch of unifying Sm750Dxe driver in
edk2-non-osi.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Signed-off-by: Yi Li <phoenix.liyi@huawei.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
The receive buffers of the NETSEC driver are owned by the driver itself
(as opposed to the protocol client in the case of the transmit path),
and so the descriptors and the buffers (which are of a fixed size) are
allocated in one go. The idea is that the 'buffer' member of the
descriptor should point to a DMA aligned offset into the same allocation,
but the code in pfdep_alloc_pkt_buf() calculates the value incorrectly,
resulting in corruption of the descriptor metadata if the pool allocation
happens to be DMA aligned.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Recently added installation of gEdkiiNvVarStoreFormattedGuid
introduced bug in the error path. gBS->UninstallProtocolInterface
takes an actual handle as an argument (not the pointer). Fix this
and on the occasion fix indentation of multiline call.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
We need to set PcdShellLibAutoInitialize to FALSE for
TftpDynamicCommand, or else we will get initialization failure when
loading TftpDynamicCommand module, for EFI Shell has not been started
at this moment.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Add a ACPI PPTT table describing the cache topology of the Seattle SoC.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
As MvFvbDxe driver is ready, we can now link NvVarStoreFormattedLib
into VariableRuntimeDxe via NULL class resolution for all
Armada7k8k platforms.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
Recent changes in the EDK2 mainline resulted in breaking
RTC functionality of Armada platforms.
The RealTimeClockLib instance calls gDS->SetMemorySpaceAttributes()
in the LibRtcInitialize() public function. This DXE service depends
on the CPU Arch Protocol. Add it to the depex.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
Recent changes in the EDK2 mainline resulted in breaking of compilation
and booting of Armada platforms. This patch adjust the MvFvbDxe driver
by:
* installation of gEdkiiNvVarStoreFormattedGuid in order to signal
NvVarStoreFormattedLib to the generic variable runtime driver
* making explicit dependency to ArmPkg/Drivers/CpuDxe drivers in order
to enable successful calling of gDS->SetMemorySpaceAttributes
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
This adds SMBIOS tables to the DeveloperBox platform describing the
BIOS, system, enclosure, CPUs, caches, PCIe slots and system memory,
which almost amounts to the mandatory minimum as given by the SMBIOS
spec. Only the type 17 structures currently lack detailed information
about the DIMMs: the SPDs are on a I2C bus that is only accessible by
the SCP, and it currently does not share this information.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Add a DT description of the size and geometry of the various levels
of caches that are present in the SynQuacer SoC.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
On the SynQuacer Evalution Board, PCIe RC #0 is not clocked if no card
is inserted into the PCIe slot, and so any attempt to access the device
registers will lock up the system.
So let's check the presence detect pin directly in the _STA implementation
of PCI0. This needs to be done before the config space check, because that
access itself will lock the system if no card is inserted.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
|
|
We have a couple of workarounds available for the ECAM ghosting issue
that affects the Synopsys Designware PCIe RCs. First of all, we can be
optimistic and hope that the silicon gets fixed at some point. Then,
there is a SCP firmware hack that hides these ghosts by remapping the
ECAM region using the SMMU sitting between the CPU and the PCIe RC
slave interface. Finally, we have a workaround involving stage 2
translation tables that may be enabled at will using a DIP switch on
the board.
Instead of adding elaborate logic to infer which of these situations we
may find ourselves in, let's just test for the symptom directly in the
_STA method implementation of the PNP0A08 devices, and deactivate the
device if the ECAM space does not appear sane.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
|
|
Expose a separate ACPI description of the SynQuacer eMMC controller
when both ACPI and eMMC support have been enabled in the HII menu.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
|
|
Create a HII menu option to choose between device tree and ACPI platform
descriptions. Note that the option is only active if PCIe compatibility
mode is enabled.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Add the ACPI tables describing various parts of the SynQuacer SoC and
its peripherals, and the drivers to expose them to the EvalBoard and
DeveloperBox platforms.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
|
|
The ACPI/Linux code does not cope very well with I/O BAR windows that
involve type translation and address translation. In particular, the
secondary I/O window we implement on SynQuacer:
I/O 0x10000 ... 0x1ffff -> 0x77f00000
is misinterpreted by Linux, and results in the MMIO range starting at
0x77f10000 to be mapped for I/O port access to this range.
This can be mitigated by using the same bus range for I/O port access
on both RCs., i.e., [0x0 ... 0xffff]. This configuration can be represented
using both DT and ACPI, and will work as expected in Linux.
Now that the generic PCI host bridge driver has gained support for address
translation, we can actually support this configuration seamlessly in UEFI
as well, by applying an offset to the second I/O window to make it appear
adjacent to the first one in the CPU view of the I/O space.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Fix the static B/D/F specifiers that refer to the pair of x1 PCIe slots
on the DeveloperBox PCB. The current configuration caused user-configurable
settings for slots 1/2 to apply to the incorrect one.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Add description of SBSA watchdogs to ACPI GTDT on D05.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Chenhui Sun <sunchenhui@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
Hi1616 GIC does not fully support GICv2 legacy mode, and SBSA watchdog
interrupts 400 and 496 cannot be signaled to CPU, so we switch to pure
GICv3 mode.
For other Hisilicon platforms, we suppose they don't need V2 legacy
mode either if they have GICv3. D03 also works for this patch. If the
platforms only have GICv2, this change will have no impact on them.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: gongchengya <gongchengya1@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
|
Timer is always working on Hisilicon D0x, even system enters WFI/WFE,
and there is no other low power status, so we set "always-on" flag in
ACPI GTDT.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jason Zhang <zhangjinsong2@huawei.com>
Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
