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2016-09-08UefiCpuPkg/NehalemMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/IvyBridgeMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/HaswellMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/HaswellEMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/CoreMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/Core2Msr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/BroadwellMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/AtomMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-08UefiCpuPkg/ArchitecturalMsr.h: add MSR reference from SDM in commentJeff Fan
Cc: Michael Kinney <michael.d.kinney@intel.com> Cc: Feng Tian <feng.tian@intel.com> Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jeff Fan <jeff.fan@intel.com> Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>
2016-09-07ArmPkg/DefaultExceptionHandlerLib AARCH64: add minimal backtrace to crash dumpArd Biesheuvel
When dumping the CPU state after an unhandled fault, walk the stack frames and decode the return addresses so we can show a minimal backtrace. Unfortunately, we do not have sufficient information to show the function names, but at least we can see the modules and the return addresses inside the modules. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-07BaseTools/tools_def AARCH64: enable frame pointers for DEBUG buildsArd Biesheuvel
Enable frame pointers on DEBUG builds so we can support backtraces in crash dumps. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-07ArmPlatformPkg/PrePi: fix secondary stack baseMichael Zimmermann
this bug was introduced by: d2fa09a ArmPlatformPkg/PrePi: switch to ASM_FUNC() asm macro Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com> Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
2016-09-07Vlv2TbltDevicePkg/dec: Correct wrong default value.Jiewen Yao
The default PcdPeiIchEhciControllerMemoryBaseAddress value 0xFD000000 conflict with the default TXE SECUMA MMIO address. So we update to 0xFC000000 to avoid conflict. Cc: David Wei <david.wei@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: David Wei <david.wei@intel.com>
2016-09-07Vlv2TbltDevicePkg/PlatformInitPei: Support USB initJiewen Yao
In order to support recovery in PEI phase, a platform need initialize USB controller. This logic is missing in current PchInitPeim. We removed MultiPlatformInfoInit() because it is already done in PlatformEarlyInitEntry(). We also initialize XhciMemBaseAddr to 0, or it is garbage value. Cc: David Wei <david.wei@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: David Wei <david.wei@intel.com>
2016-09-07NetworkPkg/DnsDxe: Handle CNAME type responded from the name serverJiaxin Wu
v2: * Code refine. * For DnsCache, the minimum value of TTL is selected between CNAME and A/AAAA record. According RFC 1034 - 3.6.2, if the query name is an alias, the name server will include the CNAME record in the response and restart the query at the domain name specified in the data field of the CNAME record. RFC also provides one example server action when A query received: Suppose a name server was processing a query with for USCISIC.ARPA, asking for type A information, and had the following resource records: USC-ISIC.ARPA IN CNAME C.ISI.EDU C.ISI.EDU IN A 10.0.0.52 Both of these RRs would be returned in the response to the type A query. Currently, DnsDxe driver doesn't handle the CNAME type response, which will cause any exception result. The driver need continue the packet parsing while CNAME type record parsed. So, this patch is used to handle it correctly. Cc: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Cc: Ye Ting <ting.ye@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com> Tested-by: Hegde Nagaraj P <nagaraj-p.hegde@hpe.com>
2016-09-06ArmPkg/CompilerIntrinsicsLib: use Clang-compatible 'weak' attributeArd Biesheuvel
Clang does not like separate definitions for the __alias__ and the __weak__ attributes, so merge the definitions into one. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-06ArmVirtPkg/FdtPciHostBridgeLib: enable 64-bit PCI DMAArd Biesheuvel
Now that the PCI root bridge driver and various host controller drivers have been fixed, remove the 4 GB limit on PCI DMA allocation for QEMU's ECAM PCI host bridge. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-09-06MdeModulePkg/PciHostBridgeDxe: restrict 64-bit DMA to devices that support itArd Biesheuvel
Currently, the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute is completely ignored by the PCI host bridge driver, which means that, on an implementation that supports DMA above 4 GB, allocations above 4 GB may be provided to devices that have not expressed support for it. So in addition to checking 'RootBridge->DmaAbove4G' to establish whether the root bridge itself supports DMA above 4 GB, we must also take into account the operation type (EfiPciOperationBusMaster{Read|Write|CommonBuffer}64), and the EFI_PCI_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute, when mapping and allocating DMA memory, respectively. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Ruiyu Ni <Ruiyu.ni@intel.com>
2016-09-06MdeModulePkg/XhciDxe: enable 64-bit PCI DMAArd Biesheuvel
PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-06MdeModulePkg/SdMmcPciHcDxe: enable 64-bit PCI DMAArd Biesheuvel
PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-06MdeModulePkg/NvmExpressDxe: enable 64-bit PCI DMAArd Biesheuvel
PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-06MdeModulePkg/EhciDxe: enable 64-bit PCI DMAArd Biesheuvel
PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-06MdeModulePkg/AtaAtapiPassThru: enable 64-bit PCI DMAArd Biesheuvel
PCI controller drivers must set the EFI_PCI_IO_ATTRIBUTE_DUAL_ADDRESS_CYCLE attribute if the controller supports 64-bit DMA addressing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Feng Tian <feng.tian@Intel.com>
2016-09-06NetworkPkg/IpSecDxe: Generate SPI randomly and correct IKE_SPI_BASE valueJiaxin Wu
This path made the following update: * Generate SPI randomly. * Correct IKE_SPI_BASE value according RFC 4302/4303. Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Ye Ting <ting.ye@intel.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
2016-09-06MdeModulePkg: Support classless IP for DHCPv4 TransmitReceive()Jiaxin Wu
The IP address should not be treated as classful one if DHCP options contain a classless IP with its true subnet mask. Otherwise, DHCPv4 TransmitReceive() will failed. This real subnet mask will be parsed and recorded in DhcpSb->Netmask. So, we need check it before get the IP's corresponding subnet mask. Cc: Santhapur Naveen <naveens@amiindia.co.in> Cc: Ye Ting <ting.ye@intel.com> Cc: Fu Siyuan <siyuan.fu@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com> Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
2016-09-06MdeModulePkg NvmExpressDxe: Set the non-blocking I/O feature support bitHao Wu
Since current codes in NvmExpressDxe already support the non-blocking I/O feature for EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL interface, the relative bit in the 'Attributes' field of EFI_NVM_EXPRESS_PASS_THRU_MODE should be set to reflect this. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-09-06MdeModulePkg NvmExpressDxe: Fix 'Event' won't be signaled for Admin cmdsHao Wu
This commit fixes the issue that the caller event passed to EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.PassThru() will not be signaled for NVME Admin commands. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-09-06MdeModulePkg NvmExpressDxe: Add NamespaceId validity check in PassThruHao Wu
According to the UEFI spec, EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.PassThru() should return EFI_INVALID_PARAMETER if the input 'NamespaceId' is invalid for the NVM Express controller. This commit adds check in PassThru() to follow this rule. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-09-06MdeModulePkg NvmExpressDxe: Add check for command packet in PassThruHao Wu
This commit adds serveral checks for the 'Packet' parameter passed to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.PassThru() API: The check for the 'TransferLength' field in EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET to make sure the value will not exceed the maximum data transfer size allowed by a controller. The check for the 'TransferBuffer' and 'TransferLength' fields in EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET when the Opcode of an NVME command indicates a data transfer between controller and host. The check for the 'MetadataLength' field in EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET to make sure the value is not 0 when the corresponding 'MetadataBuffer' field has a non-NULL value. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-09-06MdeModulePkg NvmExpressDxe: Add check on the attributes of NVME controllerHao Wu
According to UEFI spec, an EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL with neither EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_LOGICAL nor EFI_NVM_EXPRESS_PASS_THRU_ATTRIBUTES_PHYSICAL set in the Attributes field is an illegal configuration. This commit adds this check in the PassThru API to follow the spec. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-09-06MdeModulePkg NvmExpressDxe: Add buffer alignment check in PassThru APIHao Wu
According to the UEFI spec, the 'TransferBuffer' and 'MetadataBuffer' used in a data transfer should be aligned on the boundary specified by the IoAlign field in the EFI_NVM_EXPRESS_PASS_THRU_MODE structure. This commit adds this check to follow the spec. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-09-06MdeModulePkg NvmExpressDxe: Refine GetNextNamespace API to follow specHao Wu
According to the UEFI spec, EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() should return EFI_NOT_FOUND when the value pointed to by NamespaceId is the namespace ID of the last namespace on the NVM Express controller. This commit modifies the check for NamespaceId to follow this rule. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-09-06MdeModulePkg NvmExpressDxe: Refine GetNameSpace API to follow specHao Wu
According to the UEFI spec, EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() should return EFI_NOT_FOUND when the input DevicePath is a device path node type that the NVM Express Pass Thru driver supports, but there is not a valid translation from DevicePath to a namespace ID. Current code will return EFI_SUCCESS. This commit adds additional check in the GetNameSpace API to make sure correct status is returned. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-09-06MdeModulePkg NvmExpressDxe: Refine BuildDevicePath API to follow specHao Wu
According to the UEFI spec, EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() should return EFI_NOT_FOUND when the input NamespaceId is not valid. However, current code returns EFI_DEVICE_ERROR instead. This commit modifies the check for input NamespaceId to return the correct status. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-09-06MdeModulePkg NvmExpressDxe: Avoid crashing 'Mode' during OpenProtocolHao Wu
The gBS->OpenProtocol() calls to open EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL in NvmExpress.c will crash the data in 'Mode' field of 'Private->Passthru'. The third parameter of gBS->OpenProtocol() is an output parameter that stores the address where a pointer to the corresponding Protocol Interface. The current code mistakenly pass '&Private->Passthru' (a pointer of the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL) as the third parameter. This will crash the data in 'Mode' filed. Cc: Feng Tian <feng.tian@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Feng Tian <feng.tian@intel.com>
2016-09-05ArmPkg/CompilerIntrinsicsLib ARM: make memset() weak againArd Biesheuvel
After the recent update of CompilerIntrinsicsLib, our memset() is no longer emitted as a weak symbol. On ARM, this may cause problems when combining this library with another library that supplies memset() [e.g., CryptoPkg/IntrinsicLib], due to the fact that the object also supplies the __aeabi_memXXX entry points, which can only be satisfied by this object. So make our memset() weak again, to let the other implementation take precedence. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
2016-09-05ArmVirtPkg/FdtPciPcdProducerLib: zero init local var to please GCC 4.8Ard Biesheuvel
GCC 4.8 in RELEASE mode complains about GetPciIoTranslation () potentially not assigning IoTranslation, but does not notice that it returns failure in this case, which means IoTranslation is never referenced *unless* it has been assigned. So simply set IoTranslation to zero to help the compiler. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com>
2016-09-05MdeModulePkg PiDxeS3BootScriptLib: Support multiple PCI segmentStar Zeng
Support multiple PCI segment for PCI_CONFIG2 opcodes. PiDxeS3BootScriptLib needs to be updated to consume PciSegmentLib instead of PciLib. That means platforms need to add PciSegmentLib declaration like below in platform dsc if the PciSegmentLib was not declared in platform dsc before. PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf For platforms only have one segment, MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf is recommended to be used and declared in platform dsc for PiDxeS3BootScriptLib to have equivalent functionality with before. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Laszlo Ersek <lersek@redhat.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-09-05MdeModulePkg PiDxeS3BootScriptLib: Remove the trailing white spacesStar Zeng
Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Amy Chan <amy.chan@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com> Tested-by: Laszlo Ersek <lersek@redhat.com>
2016-09-05SecurityPkg/SecurityPkg.dsc: Declare PciSegmentLibStar Zeng
PiDxeS3BootScriptLib will be updated to consume PciSegmentLib instead of PciLib to support multiple PCI segment. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Chao Zhang <chao.b.zhang@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-09-05QuarkSocPkg/QuarkSocPkg.dsc: Declare PciSegmentLibStar Zeng
PiDxeS3BootScriptLib will be updated to consume PciSegmentLib instead of PciLib to support multiple PCI segment. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Kelly Steele <kelly.steele@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-09-05QuarkPlatformPkg: Declare PciSegmentLib in platform dscStar Zeng
PiDxeS3BootScriptLib will be updated to consume PciSegmentLib instead of PciLib to support multiple PCI segment. That means platforms need to add PciSegmentLib declaration in platform dsc if the PciSegmentLib was not declared in platform dsc before. For platforms only have one segment, MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf is recommended to be used and declared in platform dsc for PiDxeS3BootScriptLib to have equivalent functionality with before. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: Kelly Steele <kelly.steele@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-09-05Vlv2TbltDevicePkg: Declare PciSegmentLib in platform dscStar Zeng
PiDxeS3BootScriptLib will be updated to consume PciSegmentLib instead of PciLib to support multiple PCI segment. That means platforms need to add PciSegmentLib declaration in platform dsc if the PciSegmentLib was not declared in platform dsc before. For platforms only have one segment, MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf is recommended to be used and declared in platform dsc for PiDxeS3BootScriptLib to have equivalent functionality with before. Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Michael D Kinney <michael.d.kinney@intel.com> Cc: Amy Chan <amy.chan@intel.com> Cc: David Wei <david.wei@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> Reviewed-by: David Wei <david.wei@intel.com> Reviewed-by: Michael Kinney <michael.d.kinney@intel.com>
2016-09-04BaseTools: Change source files to DOS formatYonghong Zhu
Cc: Liming Gao <liming.gao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com> Reviewed-by: Liming Gao <liming.gao@intel.com>
2016-09-03IntelSiliconPkg: Rename IGD structures to make it consistentMudusuru, Giri P
Renamed INTEL_IGD_* to IGD_* and IGD_OPREGION_VBT to IGD_OPREGION_MBOX4 to make it consistent with file name and other mailbox naming. Cc: Jiewen Yao <jiewen.yao@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Giri P Mudusuru <giri.p.mudusuru@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
2016-09-02ArmVirtPkg: remove now unused PciHostBridgeDxeArd Biesheuvel
This code is now no longer used, so remove it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65
2016-09-02ArmVirtPkg/FdtPciHostBridgeLib: add MMIO64 supportArd Biesheuvel
If the pci-host-ecam-generic DT node describes a 64-bit MMIO region, account for it in the PCI_ROOT_BRIDGE description that we return to the generic PciHostBridgeDxe implementation, which will be able to allocate BARs from it without any further changes. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65
2016-09-02ArmVirtPkg/ArmVirtQemu: switch to generic PciHostBridgeDxeArd Biesheuvel
Wire up the FdtPciHostBridgeLib introduced in the previous patch to the generic PciHostBridgeDxe implementation, and drop the special ArmVirtPkg version. The former's dependency on gEfiCpuIo2ProtocolGuid is satisfied by adding ArmPciCpuIo2Dxe.inf as well, and adding the PCD gArmTokenSpaceGuid.PcdPciIoTranslation as a dynamic PCD. In terms of functionality, no changes are intended. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65
2016-09-02ArmVirtPkg: implement FdtPciHostBridgeLibArd Biesheuvel
Implement PciHostBridgeLib for DT platforms that expose a PCI root bridge via a pci-host-ecam-generic DT node. The DT parsing logic is copied from the PciHostBridgeDxe implementation in ArmVirtPkg, with the one notable difference that we don't set some of the legacy PCI attributes for IDE and VGA I/O ranges. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65
2016-09-02ArmVirtPkg/FdtPciPcdProducerLib: add handling of PcdPciIoTranslationArd Biesheuvel
Add handling of the PcdPciIoTranslation PCD, so that modules that include this library via NULL resolution are guaranteed that it will be set before they reference it. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Ref: https://tianocore.acgmultimedia.com/show_bug.cgi?id=65
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