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It should start from the last '\x' position + 1 to find next '\x'
character.
Cc: Liming Gao <liming.gao@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Yonghong Zhu <yonghong.zhu@intel.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>
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Add SecureBoot NULL pointer check before reference it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chao Zhang <chao.b.zhang@intel.com>
Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
Reviewed-by: Qiu Shumin <shumin.qiu@intel.com>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Tested-by: Gary Lin <glin@suse.com>
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The patch re-factors the code without functionality impact.
Next patch will add code to support OVMF above Xen.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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Change PciHostBridgeDxe driver to not install the
PciHostBridgeResourceAllocation protocol and let
PciRootBridgeIo.Configuration() return the correct PCI resource
assignment information when the ResourceAssigned is TRUE.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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Some platform doesn't require PciBus driver to assign resource
to PCI devices which causes PciRootBridgeIo.Configuration() cannot
return correct resource information to caller.
When resource assignment by PciBus is not mandatory, only light
version of PCI bus enumeration is performed, which only collects
the device resource consumption and publishes the PciIo instance.
The corresponding logic is in PciEnumeratorLight() in PciBus driver.
But PciEnumeratorLight() still depends on
PciRootBridgeIo.Configuration() returns the starting bus number in
order to search down to find all PCI devices under the root bridge.
When ResourceAssigned in PCI_ROOT_BRIDGE returned by
PciHostBridgeGetRootBridges() is TRUE, PciHostBridge driver treats
the Bus/Io/Mem/MemAbove4G/PMem/PMemAbove4G as the resource that are
*actually assigned* to the root bridge, instead of the resource that
*can be assigned* to the root bridge.
So that PciRootBridgeIo.Configuration() can return the correct
information.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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In order to match the previous commit, Base must be strictly larger than
Limit if some type of aperture is not available on a PCI root bridge.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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When the aperture base equals to aperture limit, the old code treats
the aperture as non-existent. It's not correct because it indicates
a range starting with base and the length is 1.
The new code corrects the comparing bug.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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To support UEFI Secure Boot and the Linux persistent store with UEFI
variables, set PcdMaxVariableSize to 0x2000 bytes as is done in OvmfPkg.
For reference, the related Ovmf commits: 8cee3de7 2d441ca9
Also increase the maximum size for Authenticated variables in order to
handle a larger Signature List size as is done in OvmfPkg. Related Ovmf
commit: f5404a3e
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Linn Crosetto <linn@hpe.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
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Pass the serial port baudrate, register stride, input clock rate and
ID from coreboot to CorebootPayloadPkg.
Change-Id: I37111d23216e4effa2909337af7e8a6de36b61f7
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
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Skip non-bridge devices which are not enabled either for memory or I/O
access.
Change-Id: I1a39c69a8556b6b9cefd1a2bb191f7e0744ddfb0
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
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Remove trailing white space from PciEnumeratorSupport.c.
Change-Id: Ia2f354151d46c09b140e2b42609d76fbbf8333f9
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
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Ensure communication between the host and the UEFI system running
CorebootPayloadPkg. In cases where the host has flow control enabled
and the serial connection is providing the flow control signals, the
host will not be able to send data to the UEFI system because DTR and
RTS are not present. The host may also discard all output data from
the UEFI system because DTR is not present. By setting DTR and RTS
in the UART initialization code this case works properly.
Change-Id: I393f57104d111472cafcae01d4e43d4ea837be3b
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
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Remove trailing white space.
Change-Id: I73c3a3e1e55eec20b09443de1966573c97fa74f8
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
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Copy MdeModulePkg/Library/BaseSerialPortLib16550 revision
89ecd4cf8078aa946083cdcbf9af81ff29f8d9f5.
Change-Id: Ie2fd0123bdd7aaba4335afdb1cb017f3690455c6
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
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Now that the LAN9118-specific MMIO accessors provide the required
delays, remove the redundant stalls.
Stalls in delay loops are kept, as these give time for work to happen
beyond synchronisation of the device register file.
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Migrate the existing code to use the new LAN9118 MMIO wrappers, ensuring
that timing requirements are respected.
The newly redundant stalls will be removed in a subsequent patch.
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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As described in the LAN9118 datasheet, delays are necessary after some
reads and writes in order to ensure subsequent reads do not see stale
data.
This patch adds helpers to provide these delays automatically, by
performing dummy reads of the BYTE_TEST register (as recommended in the
LAN9118 datasheet). This approach allows the device register file itself
to provide the required delay, avoiding issues with early write
acknowledgement, or re-ordering of MMIO accesses aganist other
instructions (e.g. the delay loop).
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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Commit a4626006bbf86113 ("EmbeddedPkg/Lan9118Dxe: use MemoryFence")
replaced some stalls with memory fences, on the presumption that these
were erroneously being used to order memory accesses. However, this was
not the case.
LAN9118 devices require a timing delay between state-changing
reads/writes and subsequent reads, as updates to the register file are
asynchronous and the effects of state-changes are not immediately
visible to subsequent reads.
This delay cannot be ensured through the use of memory barriers, which
only enforce observable ordering, and not timing. Thus, converting these
stalls to memory fences was erroneous, and may result in stale values
being read.
This reverts commit a4626006bbf86113453aeb7920895e66cdd04737.
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Ryan Harkin <ryan.harkin@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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When we split a block entry into a table entry, the UXN/PXN/XN permission
attributes are inherited both by the new table entry and by the new block
entries at the next level down. Unlike the NS bit, which only affects the
next level of lookup, the XN table bits supersede the permissions of the
final translation, and setting the permissions at multiple levels is not
only redundant, it also prevents us from lifting XN restrictions on a
subregion of the original block entry by simply clearing the appropriate
bits at the lowest level.
So drop the code that sets the UXN/PXN/XN bits on the table entries.
Reported-by: "Oliyil Kunnil, Vishal" <vishalo@qti.qualcomm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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DmaMap () only allows uncached mappings to be used for creating consistent
mappings with operation type MapOperationBusMasterCommonBuffer. However,
if the buffer passed to DmaMap () happens to be aligned to the CWG, there
is no need for a bounce buffer, and we perform the cache maintenance
directly without ever checking if the memory attributes of the buffer
adhere to the API.
So add some debug code that asserts that the operation type and the memory
attributes are consistent.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ryan Harkin <ryan.harkin@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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In the DmaMap () operation, if the region to be mapped happens to be
aligned to the Cache Writeback Granule (CWG) (whose value is typically
64 or 128 bytes and 2 KB maximum), we remap the memory as uncached.
Since remapping memory occurs at page granularity, while the buffer and the
CWG may be much smaller, there is no telling what other memory we affect
by doing this, especially since the operation is not reverted in DmaUnmap().
So remove the remapping call.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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DmaMap () operations of type MapOperationBusMasterCommonBuffer should
return a mapping that is coherent between the CPU and the device. For
this reason, the API only allows DmaMap () to be called with this operation
type if the memory to be mapped was allocated by DmaAllocateBuffer (),
which in this implementation guarantees the coherency by using uncached
mappings on the CPU side.
This means that, if we encounter a cached mapping in DmaMap () with this
operation type, the code is either broken, or someone is violating the
API, but simply proceeding with a double buffer makes no sense at all,
and can only cause problems.
So instead, actively reject this operation type for cached memory mappings.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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Comparing a GCD attribute field directly against EFI_MEMORY_UC and
EFI_MEMORY_WT is incorrect, since it may have other bits set as well
which are not related to the cacheability of the region. So instead,
test explicitly against the flags EFI_MEMORY_WB and EFI_MEMORY_WT,
which must be set if the region may be mapped with cacheable attributes.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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We manage to use both an AND operation with 'gCacheAlignment - 1' and a
modulo operation with 'gCacheAlignment' in the same compound if statement.
Since gCacheAlignment is a global of which the compiler cannot guarantee
that it is a power of two, simply use the AND version in both cases.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The allocation function UncachedAllocatePages () may return NULL, in
which case our implementation of DmaAllocateBuffer () should return
EFI_OUT_OF_RESOURCES rather than silently ignoring the NULL value and
returning EFI_SUCCESS.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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The patch aligns to the IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe
driver not flush the UART in Reset() and SetAttributes() function.
It was found the flush causes hang on certain PCI serial devices.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Jin <eric.jin@intel.com>
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The RamDiskDxe driver originally uses a variable-length HII varstore to
retrieve the HII checkbox status of each registered RAM disk.
However, HII does not support the variable-length varstore feature.
Therefore, only the checkbox status for the first 8 RAM disks are tracked
for the following definition of HII varstore structure considering the
alignment:
typedef struct {
UINT64 Size;
UINT8 RamDiskList[0];
} RAM_DISK_CONFIGURATION;
This commit uses the private data of each registered RAM disks to track
the HII checkbox status instead to resolve the issue.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
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The RamDiskDxe driver in MdeModulePkg now will use EFI_ACPI_TABLE_PROTOCOL
and EFI_ACPI_SDT_PROTOCOL during reporting RAM disks to NVDIMM Firmware
Interface Table (NFIT).
A Pcd 'PcdInstallAcpiSdtProtocol' controls whether the
EFI_ACPI_SDT_PROTOCOL will be produced. Its default value is set to FALSE
in MdeModulePkg. To make the NFIT reporting feature working properly under
OVMF, the patch will set the Pcd to TRUE in OVMF DSC files.
Also, the RamDiskDxe driver will sometimes report a NVDIMM Root Device
using ASL code which is put in a Secondary System Description Table (SSDT)
according to the ACPI 6.1 spec.
Locating the SSDT requires modifying the [Rule.Common.DXE_DRIVER] field in
OVMF FDF files.
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
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The RamDiskDxe now will report RAM disks with reserved memory type to NFIT
in the ACPI table.
This commit will also make sure that an NVDIMM root device exists in the
\SB scope before reporting any RAM disk to NFIT.
To properly report the NVDIMM root device, one will need to append the
following content in the [Rule.Common.DXE_DRIVER] field in platform FDF
files:
RAW ACPI Optional |.acpi
RAW ASL Optional |.aml
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Hao Wu <hao.a.wu@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Samer El-Haj-Mahmoud <elhaj@hpe.com>
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Replace : with ; which was changes accidentally.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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This adds a partial stack dump (256 bytes at either side of the stack
pointer) to the CPU state dumping routine that is invoked when taking an
unexpected exception. Since dereferencing the stack pointer may itself
fault, ensure that we don't enter the dumping routine recursively.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
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The default exception handler, which is essentially the one that is invoked
for unexpected exceptions, ends with an ASSERT (FALSE), to ensure that
execution halts after dumping the CPU state. However, ASSERTs are compiled
out in RELEASE builds, and since we simply return to wherever the ELR is
pointing, we will not make any progress in case of synchronous aborts, and
the same exception will be taken again immediately, resulting in the string
'Exception at 0x....' to be printed over and over again.
So use an explicit deadloop instead.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Leif Lindholm <leif.lindholm@linaro.org>
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It's done by producing EFI_ERASE_BLOCK_PROTOCOL protocol instance.
Cc: Hao Wu <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Hao Wu <hao.a.wu@intel.com>
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when there's no volume label 'Info' can be NULL
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Zimmermann <sigmaepsilon92@gmail.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
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For Pyrite SSC device, it may not supports Active Key, So
add check logic before enable it.
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
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This patch is used to cleanup unused structure
definition.
Cc: Zhang Chao B <chao.b.zhang@intel.com>
Cc: Ye Ting <ting.ye@intel.com>
Cc: Fu Siyuan <siyuan.fu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ye Ting <ting.ye@intel.com>
Reviewed-by: Fu Siyuan <siyuan.fu@intel.com>
Reviewed-by: Chao Zhang <chao.b.zhang@intel.com>
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Before switch to a bus mode, we need check if the SD device supports
this bus mode.
Cc: Wu, Hao A <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
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Enhance the code to reset tuning circuit when tuning error case happens.
Cc: Wu, Hao A <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
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The original code is using ADMA mode to do clock tuning procedure. It
may have problem on some SD/MMC host controllers as there is no way to
know when to send next tuning cmd.
Update it to PIO mode to strictly follow SD Host Controller Simplified
Specification 3.0 Figure 2-29. By this way, if the Buffer Read Ready
interrupt is set, we could know it's ok to send the next clock tuning
cmd.
Cc: Wu, Hao A <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
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The original code has a bug to calculate which clock freq should be
used when the target clock freq is larger than the BaseClock Freq
provided by the system.
Cc: Wu, Hao A <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
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Check if the card is identified/initialized correctly. if not, break
the following cmd execution through PassThru()/ResetDevice().
Cc: Wu, Hao A <hao.a.wu@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
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This library instance is no longer referenced.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ruiyu Ni <ruiyu.ni@Intel.com>
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Based on OvmfPkg commit 79c098b6d25d.
Unlike in OVMF, no USE_OLD_BDS fallback is introduced; I think that
ArmVirtPkg is less widely used by non-developers than OvmfPkg.
ArmVirtXen is not modified, as it uses PlatformIntelBdsLib from
ArmPlatformPkg.
About this patch:
- DxeServicesLib and SortLib are resolved generally (they have broad
client module type lists).
- ReportStatusCodeLib is resolved for UEFI_APPLICATION modules.
- GenericBdsLib and PlatformBdsLib are replaced with UefiBootManagerLib
and PlatformBootManagerLib, and resolved from under MdeModulePkg and
ArmVirtPkg, respectively.
- QemuBootOrderLib is pointed to the QemuNewBootOrderLib instance.
- FileExplorerLib no longer depends on SECURE_BOOT_ENABLE, it is nedeed by
BootMaintenanceManagerUiLib, which we link into UiApp.
- PcdBootManagerMenuFile carries the FILE_GUID of
"MdeModulePkg/Application/UiApp/UiApp.inf". The default PCD value from
"MdeModulePkg/MdeModulePkg.dec" points to
"MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf",
which, according to the commit that introduced it (a382952f8255), only
'provides a very simple UI showing all the boot options recorded by
"BootOrder" and user can select any of them to boot'.
- Include the new core BDS driver, and include the boot manager
application, with the usual main menu entries.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Fixes: https://github.com/tianocore/edk2/issues/83
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ruiyu Ni <ruiyu.ni@Intel.com>
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UefiBootManagerLib does not provide these functions, we have to implement
them. (EnableQuietBoot() puts up the nice TianoCore logo.)
OvmfPkg commits 817fb3ac2a78 and 8e8fd3037788 have extracted these
functions already,
- from "IntelFrameworkModulePkg/Library/GenericBdsLib/BdsConsole.c"
- to "OvmfPkg/Library/PlatformBootManagerLib/QuietBoot.c".
Copy the latter file, with minimal changes.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ruiyu Ni <ruiyu.ni@Intel.com>
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QemuBootOrderLib can only filter out and reorder boot options; it cannot
create boot options. It relies on Platform BDS to auto-generate all
possible boot options first (for example, for new virtual devices that
have been configured since the last run of the virtual machine). Then it
will decide, case-by-case, whether each of those auto-generated boot
options should be preserved (and at what position), or removed.
Thus far, the only implementation of SetBootOrderFromQemu(), used in
connection with IntelFrameworkModulePkg BDS, has expected said complete
boot option list as an input parameter:
BdsEntry() [IntelFrameworkModulePkg/Universal/BdsDxe/BdsEntry.c]
// create empty list
InitializeListHead (
&BootOptionList
)
PlatformBdsPolicyBehavior( [ArmVirtPkg/Library/PlatformIntelBdsLib/IntelBdsPlatform.c]
BootOptionList
)
BdsLibConnectAll()
BdsLibEnumerateAllBootOption(
BootOptionList
)
// at this point, BootOptionList starts with the preexistent boot
// options, and ends with the auto-generated options
SetBootOrderFromQemu( [OvmfPkg/Library/QemuBootOrderLib/QemuBootOrderLib.c]
BootOptionList
)
// write out changed boot order to UEFI variables
// The "BootOrder" variable may have changed. Refresh BootOptionList
// from it, and return it to BdsEntry().
With MdeModulePkg BDS, a BootOptionList is not propagated from BdsEntry()
to SetBootOrderFromQemu() and back. All processing is based directly on
the underlying "BootOrder" and "Boot####" variables.
In OvmfPkg, commit d27ec22d1189 introduced a new instance of
QemuBootOrderLib, called QemuNewBootOrderLib. It is based on
UefiBootManagerLib, and rather than taking a complete BootOptionList as a
parameter, it expects that the "BootOrder" and "Boot####" variables are
complete in the above sense.
Rebase the boot order manipulation to UefiBootManagerLib and
QemuNewBootOrderLib, while keeping the requirement satisfied, like this:
BdsEntry() [MdeModulePkg/Universal/BdsDxe/BdsEntry.c]
PlatformBootManagerAfterConsole() [ArmVirtPkg/Library/PlatformBootManagerLib/PlatformBm.c]
EfiBootManagerConnectAll()
EfiBootManagerRefreshAllBootOption()
// at this point all auto-generated options exist at the end of
// "BootOrder"
SetBootOrderFromQemu() [OvmfPkg/Library/QemuNewBootOrderLib/QemuBootOrderLib.c]
// read boot options from "BootOrder" and "Boot####", then
// manipulate them
This patch parallels OvmfPkg commit 04fe914ba53e.
Once the USE_OLD_BDS fallback is removed from OvmfPkg, the parameter list
of the SetBootOrderFromQemu() prototype can be updated to VOID.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ruiyu Ni <ruiyu.ni@Intel.com>
|
|
This patch parallels OvmfPkg commit fed691a6f913.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ruiyu Ni <ruiyu.ni@Intel.com>
|
|
Namely,
- PlatformBdsBootSuccess,
- PlatformBdsBootFail,
- PlatformBdsLockNonUpdatableFlash.
This patch parallels OvmfPkg commit 7f89929f7fb2.
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Ruiyu Ni <ruiyu.ni@Intel.com>
|
