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2014-07-15ARM Packages: Force the SEC modules to be 2K aligned for AArch64Olivier Martin
The AArch64 Vector Table must be aligned on a 2K boundary. The FDF specification does not support 2K alignment but support 4K. A clear comment has been added to help integrator to understand why the assertion fails when porting to a new AArch64 platform. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15659 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Returned the InterruptId in ArmGicAcknowledgeInterrupt()Olivier Martin
The InterruptId has a different width for GicV2 and GicV3 (respectively 10bit and 24bit). The function prototype has been changed to return this value to make the caller GIC architecture version independent. Otherwise, we would have need to expose a different mask to allow the caller to retrieve this value from the read register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15628 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Introduced support for GicV2 to ArmGicDxeOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15627 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Introduced support for GicV2 to ArmGicLibOlivier Martin
The support for GIcV2 was already existing. This change separate the GicV2 specific functions from the common Gic code (in preparation for GicV3 support). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15626 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Moved ArmGicDisableDistributor() to ArmGicLib.cOlivier Martin
The implementation is the same when we run in Secure or Non-Secure world. This change makes this function available for ArmGicSec.inf and ArmGicNonSec.inf. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15625 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Move RegisterInterruptSource() to the common GicDxe fileOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15624 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Move the installation and the registration to ↵Olivier Martin
InstallAndRegisterInterruptService() It will allow reusing the same code for GICv2 and GICv3 only drivers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15623 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Make the GicDxe driver depends on ArmGicLib (cont)Olivier Martin
... and also rename the ArmGicLib sources to use an explicit 'Lib' suffix. The renaming did not work well with SVN. Files were missing from the initial commit. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15622 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Introduced helper functions to access the GIC controllerOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15621 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Make the GicDxe driver depends on ArmGicLibOlivier Martin
... and also rename the ArmGicLib sources to use an explicit 'Lib' suffix. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15620 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/ArmGic: Move out the EndOfInterrupt from the interrupt acknowledgementOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15619 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-04ArmPkg/Drivers/ArmGic: Introduced ArmGicEndOfInterrupt()Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15618 6f19259b-4bc3-4df7-8a09-765794883524
2014-07-01ArmPkg/CpuDxe/ArmV6: Return error status when ExceptionHandlersStart is not ↵Olivier Martin
32-byte aligned The function should detect and return the error in non-debug builds when the ASSERT does nothing. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15606 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-20ARM Packages: Fixed missing braces (the warning was disabled by GCC)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15578 6f19259b-4bc3-4df7-8a09-765794883524
2014-06-03ArmPkg/CpuDxe: Stack Pointer is not 8-bytes aligned in AArch32 interrupt ↵Olivier Martin
handling See section "2.1 The need to align SP to a multiple of 8 at conforming call sites" in "Advisory Note. SP must be 8-byte aligned on entry to AAPCS-conforming functions" Source: http://infocenter.arm.com/help/topic/com.arm.doc.ihi0046b/IHI0046B_ABI_Advisory_1.pdf Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15553 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-14ArmPkg/CpuDxe/AArch64: Fixed SyncCacheConfig() when first entry is in 3-levelOlivier Martin
If the first entry of the memory map is in the third level (case when the region at 0x0 is smaller than 4KB) then its descriptor type would be TT_TYPE_BLOCK_ENTRY_LEVEL3 (=0x3) which has the same value as TT_TYPE_TABLE_ENTRY (=0x3). The first condition in GetFirstPageAttribute() needed the table level to not mix these two descriptor types. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15526 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: Use .8byte instead of .dword for pointersBrendan Jackman
Clang doesn't recognise .dword Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15510 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ArmPkg/CpuDxe/AArch64: use STUR instruction for signed offsetBrendan Jackman
The AARCH64 LDR and STR instructions only support signed offsets for post- and pre-indexed addressing. For normal signed offset addressing, the mnemonic is STUR. GNU As automatically assembles STR with signed offset as STUR, but Clang's integrated assembler doesn't. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15508 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ArmPkg/CpuDxe/AArch64/ExceptionSupport.S: Fix immediate syntaxBrendan Jackman
GNU as assembles instructions without the '#' before immediates. Clang doesn't. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15507 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: use GCC_ASM_EXPORT to export functionsBrendan Jackman
This ensures the .type directive is used to mark them as function symbols Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15506 6f19259b-4bc3-4df7-8a09-765794883524
2014-05-08ARM Packages: Remove GCC filter for AARCH64 assembly filesBrendan Jackman
Some non-GCC toolchain might support the GNU assembly language. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Brendan Jackman <brendan.jackman@arm.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15504 6f19259b-4bc3-4df7-8a09-765794883524
2014-04-23ArmPkg/CpuDxe: Restore AArch64 system registers before returning from exceptionoliviermartin
Current EDK2 source code does actually trigger nested interrupted (even if the PI spec says interrupt should not be nested). This issue has highlighted the lack of restoring ELR_EL2/ELR_EL1 register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off: Vijayakumar Subbu <vsubbu@nvidia.com> Signed-off: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15481 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-26ArmPkg/ArmCpuLib: Added A57 Errata 806969Olivier Martin
This rare errata only affects r0p0 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15400 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-26ArmPkg/ArmCortexA5xLib: Fixed setting of SMP bitOlivier Martin
On CortexA5x the SMP bit is BIT6 of CPUECTLR_EL1 register. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15398 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-26ArmPkg/ArmCortexA5x: Declared the helper functions to access the CPU ↵Olivier Martin
Extended Control Register This register is A5x specific. It is the reason why the code moved from ArmLib to ArmCpuLib/ArmCortexA5xLib. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15397 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-24ArmPkg: Removed unused header files from source filesOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15379 6f19259b-4bc3-4df7-8a09-765794883524
2014-03-01ArmPkg: Tidy assembler codeOlivier Martin
- Fixed typo - Removed unreachable 'dead' loop Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15277 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPkg/CpuDxe: Removed LR adjustement for SVC callOlivier Martin
The Link Register (LR) does not need adjustement when receiving a Supervisor Call (SVC). Note: SVC might be generated by debuggers. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14911 6f19259b-4bc3-4df7-8a09-765794883524
2013-11-28ArmPlatformPkg/ArmVExpressPkg: Removed unused PCDs declaration from INF fileOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14907 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-29ARM Packages: Renamed PL390Gic driver into ArmGic driverOlivier Martin
The aim is to make this driver follows the ARM GIC specifications and be implementation independent. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14810 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-24ArmPkg/PL390Gic: Fixed setting of the Interrupt Processor Targets Registers ↵Olivier Martin
when Uniprocessor When running on a uniprocessor implementation, the ICDIPTRn registers are RAZ (Read as Zero). So the previous assertion was not correct. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14798 6f19259b-4bc3-4df7-8a09-765794883524
2013-10-14ArmPkg/CpuDxe: Fixed confusion in AArch64 Table descriptor typesOlivier Martin
Table Descriptor and Level-3 Block entry descriptors have the same translation table type value (ie: 0x3). Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14771 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-23ArmPkg/CpuDxe: Fixed the condition that checks if the level-1 descriptor ↵Olivier Martin
points to a level-2 page table Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14700 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-16ArmPkg/CpuDxe: Fixed attribute setting in GetNextEntryAttribute()Olivier Martin
The wrong attribute was used to set the region. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14676 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-10ArmPkg/CpuDxe: Exception Handling SP AdjustEugene Cohen
The exception handling support code appears to adjust the stack pointer in the wrong direction. It decrements the stack pointer by 0x60, but this should be an increment (add) for the downward-growing stack. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Eugene Cohen <eugene@hp.com> Reviewed-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14646 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-03ArmPkg/CpuPei: Remove unused functions from the driverRoy Franz
The ConfigureMmu() function is unused - the only call to it is commented out, and the functionality has been moved to InitMmu() in MemoryInitPeiLib.c. This change also removes the unused definitions from the file. Change-Id: Ice795bfee25c403142d0c078533f8a46d04f82e9 Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Roy Franz <roy.franz@linaro.org> Signed-off-by:: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14621 6f19259b-4bc3-4df7-8a09-765794883524
2013-09-02ArmPkg/CpuDxe: Fixed calculation of the Page Table Index (Level 2 Descriptor)Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14617 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: Added support to not set a memory region with the same attributeOlivier Martin
Changing the attribute implies some cache management (clean & invalidate). Preventing the cache management should improve the performance. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14568 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/ArmLib: Added ConvertSectionAttributesToPageAttributes()Olivier Martin
This helper function converts the section attributes into their page equivalents. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14567 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: Fixed AArch64 MMU/GCD synchronizationOlivier Martin
- Fix the length used to set the GCD Memory Space attribute - Print a warning message if the given length of a memory space region is not 4KB-aligned Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14562 6f19259b-4bc3-4df7-8a09-765794883524
2013-08-19ArmPkg/CpuDxe: AArch64: Fix wrong comparison of exception typeGirish K S
During the interrupt registration comparison is made against max value of exception types for ARMV7, but in the common handling function the check is made against max value of exceptions types for ARMV8. This can lead to undefined behaviour during registration of interrupts. This patch modifies the registration function to handle only AArch64 exceptions. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Girish K S <ks.giri@samsung.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14561 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-26ArmPkg,ArmPlatformPkg: Free memory allocated by Get.*SpaceMap()Olivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14507 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg: Added Aarch64 supportHarry Liebel
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14486 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-18ArmPkg/CpuDxe: Moved memory mapping functions that are not architecture ↵Olivier Martin
specific to 'CpuMmuCommon.c' Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14482 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-17ArmPkg: Removed the non-used PCD PcdGicPrimaryCoreIdOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14480 6f19259b-4bc3-4df7-8a09-765794883524
2013-07-17ArmPkg/PL390Gic: Populate the GIC Distributor Target Register with the GIC ↵Olivier Martin
CPU ID retrieved from the GIC The GIC CPU Id (the GIC CPU interface the CPU is connected to) can be retrieved by reading the first registers of the GIC CPU Target Registers. The first GIC Distributor Target registers correspond to the SGIs. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14479 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-27ArmPkg: Made ArmConfigureMmu() returns a status codeOlivier Martin
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14445 6f19259b-4bc3-4df7-8a09-765794883524
2013-06-19ArmPkg/Drivers/TimerDxe: Improve Timer initialisation.Olivier Martin
- Registering a interrupt handler implicitly enables said interrupt. This is in the UEFI Spec. No need to enable the interrupts a second time. - Make sure the Timer is completely disabled before configuring it. Only enable after configuration is complete. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14433 6f19259b-4bc3-4df7-8a09-765794883524
2013-05-10ArmPlatformPkg/ArmPlatformLib: Added support for ArmPlatformIsPrimaryCore()oliviermartin
Checking if a core if the primary/boot core used to be done with the macro IS_PRIMARY_CORE(). Some platforms exposes configuration registers to change the primary core. Replacing the macro IS_PRIMARY_CORE() by ArmPlatformIsPrimaryCore() allows some flexibility in the way to check the primary core. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org> Acked-by: Ryan Harkin <ryan.harkin@linaro.org> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14344 6f19259b-4bc3-4df7-8a09-765794883524
2013-04-14ArmPkg/PL390Gic: Do not try to clear spurious interrupts.oliviermartin
If we have a pending spurious interrupt we should not try to clear it, just ignore. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14265 6f19259b-4bc3-4df7-8a09-765794883524
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