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| author | Olivier Martin <olivier.martin@arm.com> | 2014-07-15 09:24:25 +0000 |
|---|---|---|
| committer | oliviermartin <oliviermartin@6f19259b-4bc3-4df7-8a09-765794883524> | 2014-07-15 09:24:25 +0000 |
| commit | 6d0ca2577c3788ee1087177df439246fe8f2b4fd (patch) | |
| tree | f69fff3250c6dd18b8d8ef558252e35d29a5227b /ArmPkg/Drivers | |
| parent | 9232ee533884b4b516b3979ce355e367a6254749 (diff) | |
| download | edk2-platforms-6d0ca2577c3788ee1087177df439246fe8f2b4fd.tar.xz | |
ARM Packages: Force the SEC modules to be 2K aligned for AArch64
The AArch64 Vector Table must be aligned on a 2K boundary.
The FDF specification does not support 2K alignment but support 4K.
A clear comment has been added to help integrator to understand why the
assertion fails when porting to a new AArch64 platform.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15659 6f19259b-4bc3-4df7-8a09-765794883524
Diffstat (limited to 'ArmPkg/Drivers')
| -rw-r--r-- | ArmPkg/Drivers/CpuDxe/AArch64/Exception.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c b/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c index 59246f80bc..ce1c6ce09a 100644 --- a/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c +++ b/ArmPkg/Drivers/CpuDxe/AArch64/Exception.c @@ -1,7 +1,7 @@ /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
- Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
+ Portions Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
@@ -131,11 +131,12 @@ InitializeExceptions ( FiqEnabled = ArmGetFiqState ();
ArmDisableFiq ();
- // AArch64 alignment? The Vector table must be 2k-byte aligned (bottom 11 bits zero)?
- //DEBUG ((EFI_D_ERROR, "vbar set addr: 0x%016lx\n",(UINTN)ExceptionHandlersStart));
- //ASSERT(((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
+ // The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure 'Align=4K'
+ // is defined into your FDF for this module.
+ ASSERT (((UINTN)ExceptionHandlersStart & ARM_VECTOR_TABLE_ALIGNMENT) == 0);
- // We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector Base Address to point into CpuDxe code.
+ // We do not copy the Exception Table at PcdGet32(PcdCpuVectorBaseAddress). We just set Vector
+ // Base Address to point into CpuDxe code.
ArmWriteVBar ((UINTN)ExceptionHandlersStart);
if (FiqEnabled) {
|