| Age | Commit message (Collapse) | Author |
|---|
|
Replace the PMU compatible string "arm,armv8-pmuv3" with the more
precise "arm,cortex-a53-pmu", potentially making more event types
available.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
As reported by Kojima-san, the PHY reference clock value we use in our
ACPI and DT descriptions is out of sync with the hardware. Replace
125 MHz with 250 MHz throughout.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The receive buffers of the NETSEC driver are owned by the driver itself
(as opposed to the protocol client in the case of the transmit path),
and so the descriptors and the buffers (which are of a fixed size) are
allocated in one go. The idea is that the 'buffer' member of the
descriptor should point to a DMA aligned offset into the same allocation,
but the code in pfdep_alloc_pkt_buf() calculates the value incorrectly,
resulting in corruption of the descriptor metadata if the pool allocation
happens to be DMA aligned.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Add a DT description of the size and geometry of the various levels
of caches that are present in the SynQuacer SoC.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
On the SynQuacer Evalution Board, PCIe RC #0 is not clocked if no card
is inserted into the PCIe slot, and so any attempt to access the device
registers will lock up the system.
So let's check the presence detect pin directly in the _STA implementation
of PCI0. This needs to be done before the config space check, because that
access itself will lock the system if no card is inserted.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
|
|
We have a couple of workarounds available for the ECAM ghosting issue
that affects the Synopsys Designware PCIe RCs. First of all, we can be
optimistic and hope that the silicon gets fixed at some point. Then,
there is a SCP firmware hack that hides these ghosts by remapping the
ECAM region using the SMMU sitting between the CPU and the PCIe RC
slave interface. Finally, we have a workaround involving stage 2
translation tables that may be enabled at will using a DIP switch on
the board.
Instead of adding elaborate logic to infer which of these situations we
may find ourselves in, let's just test for the symptom directly in the
_STA method implementation of the PNP0A08 devices, and deactivate the
device if the ECAM space does not appear sane.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
|
|
Expose a separate ACPI description of the SynQuacer eMMC controller
when both ACPI and eMMC support have been enabled in the HII menu.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
|
|
Create a HII menu option to choose between device tree and ACPI platform
descriptions. Note that the option is only active if PCIe compatibility
mode is enabled.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Add the ACPI tables describing various parts of the SynQuacer SoC and
its peripherals, and the drivers to expose them to the EvalBoard and
DeveloperBox platforms.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Graeme Gregory <graeme.gregory@linaro.org>
|
|
The ACPI/Linux code does not cope very well with I/O BAR windows that
involve type translation and address translation. In particular, the
secondary I/O window we implement on SynQuacer:
I/O 0x10000 ... 0x1ffff -> 0x77f00000
is misinterpreted by Linux, and results in the MMIO range starting at
0x77f10000 to be mapped for I/O port access to this range.
This can be mitigated by using the same bus range for I/O port access
on both RCs., i.e., [0x0 ... 0xffff]. This configuration can be represented
using both DT and ACPI, and will work as expected in Linux.
Now that the generic PCI host bridge driver has gained support for address
translation, we can actually support this configuration seamlessly in UEFI
as well, by applying an offset to the second I/O window to make it appear
adjacent to the first one in the CPU view of the I/O space.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Fix the static B/D/F specifiers that refer to the pair of x1 PCIe slots
on the DeveloperBox PCB. The current configuration caused user-configurable
settings for slots 1/2 to apply to the incorrect one.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The Designware PCIe IP in the SynQuacer SoC needs a little help to
appear sane to the OS. Not only does it lack a true root port, and
therefore does not perform any filtering whatsoever of type 0 config
TLPs that are not intended for the link peer, it also has trouble
issuing 64-bit wide MMIO accesses, which are often used on MMIO BARs
with memory semantics (e.g., frame buffers).
So let's create a stage 2 mapping covering the entire physical address
space, and remap some ECAM regions and demote write combine attributes
to device/strongly ordered. This is not a water tight fix, but it does
work around the issues in the majority of cases.
(Note that the ECAM remapping can also be addressed in the SMMU mapping
of the PCIe IP exposed to the CPU, but this is currently under
development, and it does not hurt to have it in two places)
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
It is no longer necessary to inhibit DEBUG() calls at runtime, due to
the fact that we switched to a DebugLib implementation that takes care
of this. Since a platform could theoretically wire up DXE_RUNTIME_DRIVER
modules to a DebugLib/SerialPortLib implementation combo that does remap
the UART MMIO region for runtime and produces UEFI debug output on a UART
that is not owned by the OS, it is better not to handle this in the
driver directly.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Wire up the various drivers for the 96Boards LS connector and the
optional Secure96 mezzanine board.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Currently, SynQuacerI2cStartRequest() increases the TPL to TPL_HIGH_LEVEL
while accessing the I2C controller hardware, but fails to restore the TPL
to the original level if the call to SynQuacerI2cMasterStart() fails, and
returns right away. Given the TPL_HIGH_LEVEL implies that interrupts are
disabled, this results in a complete system hang. So instead, break out
of the loop, so that the TPL restore will occur before leaving the
function.
Note that this will result in the bus control bits to be de-asserted in
case of a failure to send the START condition, which is an appropriate
cleanup action to take after SynQuacerI2cMasterStart() fails.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Add a node for the I2C controller #1 to the device tree so the OS
may attach to it. This is the I2C controller that is attached to the
96boards mezzanine connector on Developer Box.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Add a node for the SPI controller to the device tree so the OS may
attach to it. This is the SPI controller that is attached to the
96boards mezzanine connector on Developer Box.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
On our SynQuacer based platform, power state handling and other
low-level duties are handled by the secure firmware, not by the
OS, so remove the various MHU/SCPI related nodes from the device
tree.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
We already disable SDR104 support on the SynQuacer eMMC controller to
work around the need for a special tuning quirk that is difficult to
implement without modifying the generic driver, even in the presence
of a SD/MMC override protocol designed to carry such quirks.
Unfortunately, as it turns out, DDR50 does not work either with the
particular 8 GB Kingston part that has been fitted on the rev0.2/0.3
96board samples. Since the mode UEFI drives the eMMC in is independent
from what the OS chooses, and the fact that you would not use eMMC in
the first place if performance was a major concern, let's just disable
DDR50 as well, and fall back to SDR50 mode.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Implement support for the SynQuacer eMMC controller. This involves an
implementation of the SD/MMC override protocol to handle a couple of
quirks that would otherwise prevent this IP from being driven by the
generic SDHCI driver.
Also, add a HII page to the PlatformDxe driver that allows eMMC support
to be enabled, and wire it up for both DeveloperBox and EVB.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Reuse the BootLogoLib graphical progress bar to show the progress of a
capsule update, and in absence of a graphical console, write a period
to the text console for each block updated.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Even though the ARM ARM quite clearly states that the CNTFRQ field of
each MMIO timer frame should be a read-only alias of the CNTFRQ field
of the base frame, the SynQuacer SoC implements it as a register that
is programmable separately.
So let's program it from the hardware rather than overriding the
frequency using a DT property.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Add menu options to the SynQuacer Platform menu screen to limit the
maximum PCIe link speed for each slot individually. This may be useful
to work around potential PCIe issues.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The upstream version of the Linux NETSEC driver expects the PHY DT
node to appear under a MDIO subnode, so fix this in the device tree.
Fix the node name as well, this should be 'ethernet' not 'netsec',
and add a clock-names property describing the single clock reference
as 'phy_ref_clk'.
Also, move the PHY subnode into the per-platform .dts file so we can
set the unit address in the node name. This is necessary because recent
versions of the DT compiler are more finicky about this.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Align the UART DT nodes:
- use 'uart' not 'fuart' as node name for the second serial port
- create an alias 'serial1' for the second serial port
- use UART clock reference instead of hardcoded frequency
- split 'clocks' property into 1 cell per phandle
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
To ensure that the I2C master protocol is installed immediately onto
the handles created by PlatformDxe in its entry point, force the
SynQuacerI2cDxe driver to be loaded before PlatformDxe. These handles
are recursively connected by the DXE core as soon as they appear, and
so ensuring that the I2C master protocol driver is available at this
time will ensure that these handles will be connected to it right away.
This is useful when implementations of architectural protocols such as
RTC or the EFI variable store, which should become available long before
the ordinary dispatch of UEFI driver model drivers is started at the end
of DXE, are based on I2C.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Remove a %r without an associated parameter.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Do a global replace of gPcf8563RealTimeClockLibI2cMasterProtolGuid with
gPcf8563RealTimeClockLibI2cMasterProtocolGuid.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The ASM1061 SATA controller integrated into the DeveloperBox board
emits too much electromagnetic radiation, so it needs spread spectrum
mode enabled.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
For some reason, the Asmedia 118x PCIe switch needs a little help to
make sure that the downstream links train at Gen2 speed. So add a
PCI I/O protocol notifier that implements this for each PCIe downstream
port that is present on the system.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
In order to be able to use UART #0 on the DeveloperBox's 96boards low
speed connector, expose it to the OS by adding a node to the device
tree. This requires a CM3 firmware build that makes the SCP detach
from the serial port after boot.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Masahisa KOJIMA <kojima.masahisa@socionext.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The EVB does not boot if PCI RC #0 has no card inserted, and will hang in
the PCIe initialization code. So let's check the presence detect GPIO,
and only enable PCI RC #0 if it is asserted.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
If a PCIe RC is not enabled (due to the fact that the slot is not
populated), set its DT node 'status' property to 'disabled' so that
the OS will not attempt to attach to it.
This means we will need to switch from the default DtPlatformDtbLoaderLib
to a special one for our platform.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
In order to accommodate the EVB, whose PCIe RC #0 should not be touched
by software if no card is inserted, add a PCD that tells the PCIe driver
code which RCs should be initialized and exposed to the PCI host bridge
driver.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Attempt to adhere more closely to the PCIe spec by ensuring that PERST#
remains asserted for at least 100 ms. Give it a good margin, and delay
for 150 ms; the additional boot time delay is not going to be noticeable
by anyone anyway.
Add some missing barriers as well, so that the reset takes effect right
when we think it does.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
It appears that whatever was preventing us from using CPU idle with
PSCI low power states has disappeared, so let's enable the low power
states in the DT.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Commit ce95ec196da0 ("Silicon/SynQuacer: enable coherent DMA for NETSEC
and eMMC") introduced a call to MmioOr32 into PlatformDxe without adding
the appropriate #include and LibraryClass references, resulting in build
failures when attempting to build the SynQuacer platforms. So add them.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Tested-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
As it turns out, it is surprisingly easy to configure both the NETSEC
and eMMC devices as cache coherent for DMA, given that they are both
behind the same SMMU which is already configured in passthrough mode
by the firmware running on the SCP.
So update the static SMMU configuration to make memory accesses performed
by these devices inner shareable inner/outer writeback cacheable, which
makes them cache coherent with the CPUs.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The I2C driver prints a warning under DEBUG when a I2C transaction times
out. This will occur on the rev 0.1 DeveloperBox boards due to a board
level error in the I2C routing (unless the MCU has been lifted off the
bus).
Currently, this will trigger a crash due to a missing __FUNCTION__
argument to a %a specifier in a DEBUG string, because instead, the code
will attempt to dereference a EFI_STATUS variable as a char pointer.
So add the missing __FUNCTION__ argument.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Now that we incorporated NorFlashInfoLib into the Fip006Dxe driver,
replace the code that explicitly enables flag status register polling
for Micron NOR flash with a test of the flags field provided by
NorFlashInfoLib, which carries the same information.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Pipat Methavanitpong <methavanitpong.pipat@socionext.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
As it turns out, getting the PCIe controllers to switch to Gen2 speed
is surprisingly easy. It only involves setting the 'speed change' bit
in the controller at initialization time, after which the hardware
will automatically attempt to switch to Gen2 speed after training at
Gen1 speed has completed.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Fix the weird indentation in the various #defines in the file containing
the RC init code. This is a whitespace only change.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
The function ArmPlatformInitializeSystemMemory () has been removed from
ArmPlatformLib, so remove all the [empty] implementations provided by
the various platforms.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Add the drivers, library resolutions and PCD settings to enable RTC
support on DeveloperBox. Also, update PlatformDxe to register the
non-discoverable device handles for both I2C controllers.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Add a driver that produces the I2C master protocol on top of the I2C
controllers that are implemented in the SynQuacer Socionext SoC. Note
that this supports two modes simultaneously: I2C controllers that are
only usable at boot time, and usable via the I2C protocol stack, and
I2C controllers that are dedicated for the RTC or other runtime
components.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Describe the SynQuacer SoC's eMMC controller in DT so the OS can
attach to it.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Ordinary computers typically have a physical switch or jumper on the
board that allows non-volatile settings to be cleared. Let's implement
the same using DIP switch #1 on block #3, and clear the EFI variable
store if it is set to ON at boot time.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
In order to be able to sample the state of the DIP switches at early
boot on the Developer Box platform, implement the GPIO PPI based on
the GPIO block that is implemented in the SynQuacer SoC.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
In preparation of adding support for setting a DIP switch to clear the
EFI variable store, update the early capsule handling logic to take the
boot mode into account.
This is necessary for two reasons:
- we override the boot mode when a capsule is detected,
- the capsule detection itself involves reading a EFI variable, which we
shouldn't be doing if the varstore may be in a bad state.
So factor out the initial capsule check (to keep the code understandable)
and only perform it if we are not booting in 'clear NVRAM' mode.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
|
|
Add the power button as a gpio-keys KEY_POWER button, and mark it as
a wakeup source so it can be used under the OS both as a 'sleep' and
as a 'wake' button.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
|
