| Age | Commit message (Expand) | Author |
|---|
| 2017-10-05 | Silicon/Marvell: Refactor Documentation | Nir Erez |
| 2017-10-05 | Platform/Hisilicon: fix D02 driver indentation errors | Leif Lindholm |
| 2017-10-05 | Hisilicon/D03/D05: Add AddressTranslationOffset support | Yan Zhang |
| 2017-10-05 | Hisilicon D03/D05: Enlarge iATU for RP with ARI capable device. | Jason zhang |
| 2017-10-05 | D05/ACPI: Modify I2C device | Ming Huang |
| 2017-10-05 | D05/ACPI: Disable D05 SAS0 and SAS2 | Ming Huang |
| 2017-10-05 | Hisilicon/D03: Disable the function of PerfTuning | Chenhui Sun |
| 2017-10-05 | D05/PCIe: Modify PcieRegionBase of secondary chip | Ming Huang |
| 2017-10-05 | Hisilicon/PciHostBridgeDxe: Assign BAR resource from PciRegionBase | Heyi Guo |
| 2017-10-05 | Hisilicon: Fix the drivers use the same GUID issue | Heyi Guo |
| 2017-09-01 | Platform/Hisilicon: switch to NonCoherentDmaLib | Ard Biesheuvel |
| 2017-08-29 | Silicon/Hisilicon: switch to NonDiscoverable driver for EHCI | Ard Biesheuvel |
| 2017-08-29 | Silicon/Hisilicon/SasV1Dxe: remove bogus UncachedMemoryAllocationLib ref | Ard Biesheuvel |
| 2017-08-24 | Silicon/Openmoko: add driver for ChaosKey RNG USB device | Ard Biesheuvel |
| 2017-08-21 | Silicon/AMD/Styx: Use PcdSataPortMode properly for two controllers | Alan Ott |
| 2017-08-21 | Silicon/AMD/Styx: Make PcdSataPortMode 32 bits | Alan Ott |
| 2017-08-03 | Platform,Silicon: Import Hisilicon D02,D03,D05 and HiKey | Leif Lindholm |
| 2017-08-03 | Platform,Silicon: import AMD Styx SoC support and platforms | Leif Lindholm |
