1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
|
#------------------------------------------------------------------------------
#
# Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Copyright (c) 2011 - 2014, ARM Limited. All rights reserved.
#
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#------------------------------------------------------------------------------
#include <AsmMacroIoLibV8.h>
.text
.align 3
GCC_ASM_EXPORT (ArmReadMidr)
GCC_ASM_EXPORT (ArmCacheInfo)
GCC_ASM_EXPORT (ArmGetInterruptState)
GCC_ASM_EXPORT (ArmGetFiqState)
GCC_ASM_EXPORT (ArmGetTTBR0BaseAddress)
GCC_ASM_EXPORT (ArmSetTTBR0)
GCC_ASM_EXPORT (ArmGetTCR)
GCC_ASM_EXPORT (ArmSetTCR)
GCC_ASM_EXPORT (ArmGetMAIR)
GCC_ASM_EXPORT (ArmSetMAIR)
GCC_ASM_EXPORT (ArmWriteCpacr)
GCC_ASM_EXPORT (ArmWriteAuxCr)
GCC_ASM_EXPORT (ArmReadAuxCr)
GCC_ASM_EXPORT (ArmInvalidateTlb)
GCC_ASM_EXPORT (ArmUpdateTranslationTableEntry)
GCC_ASM_EXPORT (ArmWriteCptr)
GCC_ASM_EXPORT (ArmWriteScr)
GCC_ASM_EXPORT (ArmWriteMVBar)
GCC_ASM_EXPORT (ArmCallWFE)
GCC_ASM_EXPORT (ArmCallSEV)
GCC_ASM_EXPORT (ArmReadCpuActlr)
GCC_ASM_EXPORT (ArmWriteCpuActlr)
#------------------------------------------------------------------------------
.set DAIF_FIQ_BIT, (1 << 0)
.set DAIF_IRQ_BIT, (1 << 1)
ASM_PFX(ArmReadMidr):
mrs x0, midr_el1 // Read from Main ID Register (MIDR)
ret
ASM_PFX(ArmCacheInfo):
mrs x0, ctr_el0 // Read from Cache Type Regiter (CTR)
ret
ASM_PFX(ArmGetInterruptState):
mrs x0, daif
tst w0, #DAIF_IRQ_BIT // Check if IRQ is enabled. Enabled if 0.
mov w0, #0
mov w1, #1
csel w0, w1, w0, ne
ret
ASM_PFX(ArmGetFiqState):
mrs x0, daif
tst w0, #DAIF_FIQ_BIT // Check if FIQ is enabled. Enabled if 0.
mov w0, #0
mov w1, #1
csel w0, w1, w0, ne
ret
ASM_PFX(ArmWriteCpacr):
msr cpacr_el1, x0 // Coprocessor Access Control Reg (CPACR)
ret
ASM_PFX(ArmWriteAuxCr):
EL1_OR_EL2(x1)
1:msr actlr_el1, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
ret
2:msr actlr_el2, x0 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
ret
ASM_PFX(ArmReadAuxCr):
EL1_OR_EL2(x1)
1:mrs x0, actlr_el1 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
ret
2:mrs x0, actlr_el2 // Aux Control Reg (ACTLR) at EL1. Also available in EL2 and EL3
ret
ASM_PFX(ArmSetTTBR0):
EL1_OR_EL2_OR_EL3(x1)
1:msr ttbr0_el1, x0 // Translation Table Base Reg 0 (TTBR0)
b 4f
2:msr ttbr0_el2, x0 // Translation Table Base Reg 0 (TTBR0)
b 4f
3:msr ttbr0_el3, x0 // Translation Table Base Reg 0 (TTBR0)
4:isb
ret
ASM_PFX(ArmGetTTBR0BaseAddress):
EL1_OR_EL2(x1)
1:mrs x0, ttbr0_el1
b 3f
2:mrs x0, ttbr0_el2
3:LoadConstantToReg(0xFFFFFFFFFFFF, x1) /* Look at bottom 48 bits */
and x0, x0, x1
isb
ret
ASM_PFX(ArmGetTCR):
EL1_OR_EL2_OR_EL3(x1)
1:mrs x0, tcr_el1
b 4f
2:mrs x0, tcr_el2
b 4f
3:mrs x0, tcr_el3
4:isb
ret
ASM_PFX(ArmSetTCR):
EL1_OR_EL2_OR_EL3(x1)
1:msr tcr_el1, x0
b 4f
2:msr tcr_el2, x0
b 4f
3:msr tcr_el3, x0
4:isb
ret
ASM_PFX(ArmGetMAIR):
EL1_OR_EL2_OR_EL3(x1)
1:mrs x0, mair_el1
b 4f
2:mrs x0, mair_el2
b 4f
3:mrs x0, mair_el3
4:isb
ret
ASM_PFX(ArmSetMAIR):
EL1_OR_EL2_OR_EL3(x1)
1:msr mair_el1, x0
b 4f
2:msr mair_el2, x0
b 4f
3:msr mair_el3, x0
4:isb
ret
//
//VOID
//ArmUpdateTranslationTableEntry (
// IN VOID *TranslationTableEntry // X0
// IN VOID *MVA // X1
// );
ASM_PFX(ArmUpdateTranslationTableEntry):
dc civac, x0 // Clean and invalidate data line
dsb sy
EL1_OR_EL2_OR_EL3(x0)
1: tlbi vaae1, x1 // TLB Invalidate VA , EL1
b 4f
2: tlbi vae2, x1 // TLB Invalidate VA , EL2
b 4f
3: tlbi vae3, x1 // TLB Invalidate VA , EL3
4: dsb sy
isb
ret
ASM_PFX(ArmInvalidateTlb):
EL1_OR_EL2_OR_EL3(x0)
1: tlbi vmalle1
b 4f
2: tlbi alle2
b 4f
3: tlbi alle3
4: dsb sy
isb
ret
ASM_PFX(ArmWriteCptr):
msr cptr_el3, x0 // EL3 Coprocessor Trap Reg (CPTR)
ret
ASM_PFX(ArmWriteScr):
msr scr_el3, x0 // Secure configuration register EL3
ret
ASM_PFX(ArmWriteMVBar):
msr vbar_el3, x0 // Exception Vector Base address for Monitor on EL3
ret
ASM_PFX(ArmCallWFE):
wfe
ret
ASM_PFX(ArmCallSEV):
sev
ret
ASM_PFX(ArmReadCpuActlr):
mrs x0, S3_1_c15_c2_0
ret
ASM_PFX(ArmWriteCpuActlr):
msr S3_1_c15_c2_0, x0
dsb sy
isb
ret
ASM_FUNCTION_REMOVE_IF_UNREFERENCED
|
