blob: 3dc622ecc38d70e5f74350e6df0b4a9ede76c941 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
|
/** @file
* Header defining Versatile Express constants (Base addresses, sizes, flags)
*
* Copyright (c) 2011, ARM Limited. All rights reserved.
*
* This program and the accompanying materials
* are licensed and made available under the terms and conditions of the BSD License
* which accompanies this distribution. The full text of the license may be found at
* http://opensource.org/licenses/bsd-license.php
*
* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
*
**/
#ifndef __ARM_VEXPRESS_H__
#define __ARM_VEXPRESS_H__
#include <Base.h>
#include <VExpressMotherBoard.h>
/***********************************************************************************
// Platform Memory Map
************************************************************************************/
// Can be NOR0, NOR1, DRAM
#define ARM_VE_REMAP_BASE 0x00000000
#define ARM_VE_REMAP_SZ SIZE_64MB
// Motherboard Peripheral and On-chip peripheral
#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000
#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ SIZE_256MB
#define ARM_VE_BOARD_PERIPH_BASE 0x10000000
#define ARM_VE_CHIP_PERIPH_BASE 0x10020000
// SMC
#define ARM_VE_SMC_BASE 0x40000000
#define ARM_VE_SMC_SZ 0x1C000000
// NOR Flash 1
#define ARM_VE_SMB_NOR0_BASE 0x40000000
#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
// NOR Flash 2
#define ARM_VE_SMB_NOR1_BASE 0x44000000
#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
// SRAM
#define ARM_VE_SMB_SRAM_BASE 0x48000000
#define ARM_VE_SMB_SRAM_SZ SIZE_32MB
// USB, Ethernet, VRAM
#define ARM_VE_SMB_PERIPH_BASE 0x4C000000
#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB
// DRAM
#define ARM_VE_DRAM_BASE 0x60000000
#define ARM_VE_DRAM_SZ 0x40000000
// External AXI between daughterboards (Logic Tile)
#define ARM_VE_EXT_AXI_BASE 0xE0000000
#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */
/***********************************************************************************
Core Tile memory-mapped Peripherals
************************************************************************************/
// PL111 Colour LCD Controller - core tile
#define PL111_CLCD_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x20000)
// PL341 Dynamic Memory Controller Base
#define ARM_VE_DMC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE0000)
// PL354 Static Memory Controller Base
#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)
// System Configuration Controller register Base addresses
//#define ARM_VE_SYS_CFG_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
#define ARM_VE_SYS_CFGRW0_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
#define ARM_VE_SYS_CFGRW1_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2004)
#define ARM_VE_SYS_CFGRW2_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2008)
#define ARM_PLATFORM_SCC_BASE ARM_VE_SYS_CFGRW0_REG
// SP805 Watchdog on Cortex A9 core tile
#define SP805_WDOG_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE5000)
// BP147 TZPC Base Address
#define ARM_VE_TZPC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE6000)
// PL301 Fast AXI Base Address
#define ARM_VE_FAXI_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE9000)
// TZASC Trust Zone Address Space Controller Base Address
#define ARM_VE_TZASC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xEC000)
// PL310 L2x0 Cache Controller Base Address
//#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000
/***********************************************************************************
Peripherals' misc settings
************************************************************************************/
#define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK 0x2000
#define ARM_VE_CFGRW1_REMAP_NOR0 0
#define ARM_VE_CFGRW1_REMAP_NOR1 (1 << 28)
#define ARM_VE_CFGRW1_REMAP_EXT_AXI (1 << 29)
#define ARM_VE_CFGRW1_REMAP_DRAM (1 << 30)
// TZASC - Other settings
#define ARM_VE_DECPROT_BIT_TZPC (1 << 6)
#define ARM_VE_DECPROT_BIT_DMC_TZASC (1 << 11)
#define ARM_VE_DECPROT_BIT_NMC_TZASC (1 << 12)
#define ARM_VE_DECPROT_BIT_SMC_TZASC (1 << 13)
#define ARM_VE_DECPROT_BIT_EXT_MAST_TZ (1)
#define ARM_VE_DECPROT_BIT_DMC_TZASC_LOCK (1 << 3)
#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK (1 << 4)
#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)
/***********************************************************************************
// Interrupt Map
************************************************************************************/
// Timer Interrupts
#define TIMER01_INTERRUPT_NUM 34
#define TIMER23_INTERRUPT_NUM 35
/***********************************************************************************
// EFI Memory Map in Permanent Memory (DRAM)
************************************************************************************/
// This region is allocated at the bottom of the DRAM. It will be used
// for fixed address allocations such as Vector Table
#define ARM_VE_EFI_FIX_ADDRESS_REGION_SZ SIZE_8MB
// This region is the memory declared to PEI as permanent memory for PEI
// and DXE. EFI stacks and heaps will be declared in this region.
#define ARM_VE_EFI_MEMORY_REGION_SZ SIZE_256MB
#endif
|
