summaryrefslogtreecommitdiff
path: root/Silicon/Marvell/Drivers/Spi/MvSpiDxe.c
blob: bab6cf4d5603bd750b990714dd9f3d2290a371da (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
/*******************************************************************************
Copyright (C) 2016 Marvell International Ltd.

Marvell BSD License Option

If you received this File from Marvell, you may opt to use, redistribute and/or
modify this File under the following licensing terms.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

* Redistributions of source code must retain the above copyright notice,
  this list of conditions and the following disclaimer.

* Redistributions in binary form must reproduce the above copyright
  notice, this list of conditions and the following disclaimer in the
  documentation and/or other materials provided with the distribution.

* Neither the name of Marvell nor the names of its contributors may be
  used to endorse or promote products derived from this software without
  specific prior written permission.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

*******************************************************************************/
#include "MvSpiDxe.h"

SPI_MASTER *mSpiMasterInstance;

STATIC
EFI_STATUS
SpiSetBaudRate (
  IN SPI_DEVICE *Slave,
  IN UINT32 CpuClock,
  IN UINT32 MaxFreq
  )
{
  UINT32 Spr, BestSpr, Sppr, BestSppr, ClockDivider, Match, Reg, MinBaudDiff;
  UINTN SpiRegBase = Slave->HostRegisterBaseAddress;

  MinBaudDiff = 0xFFFFFFFF;
  BestSppr = 0;

  //Spr is in range 1-15 and Sppr in range 0-8
  for (Spr = 1; Spr <= 15; Spr++) {
    for (Sppr = 0; Sppr <= 7; Sppr++) {
      ClockDivider = Spr * (1 << Sppr);

      if ((CpuClock / ClockDivider) > MaxFreq) {
        continue;
      }

      if ((CpuClock / ClockDivider) == MaxFreq) {
        BestSpr = Spr;
        BestSppr = Sppr;
        Match = 1;
        break;
        }

      if ((MaxFreq - (CpuClock / ClockDivider)) < MinBaudDiff) {
        MinBaudDiff = (MaxFreq - (CpuClock / ClockDivider));
        BestSpr = Spr;
        BestSppr = Sppr;
      }
    }

    if (Match == 1) {
      break;
    }
  }

  if (BestSpr == 0) {
    return (EFI_INVALID_PARAMETER);
  }

  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
  Reg &= ~(SPI_SPR_MASK | SPI_SPPR_0_MASK | SPI_SPPR_HI_MASK);
  Reg |= (BestSpr << SPI_SPR_OFFSET) |
         ((BestSppr & 0x1) << SPI_SPPR_0_OFFSET) |
         ((BestSppr >> 1) << SPI_SPPR_HI_OFFSET);
  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);

  return EFI_SUCCESS;
}

STATIC
VOID
SpiSetCs (
  IN SPI_DEVICE *Slave
  )
{
  UINT32 Reg;
  UINTN  SpiRegBase = Slave->HostRegisterBaseAddress;

  Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
  Reg &= ~SPI_CS_NUM_MASK;
  Reg |= (Slave->Cs << SPI_CS_NUM_OFFSET);
  MmioWrite32 (SpiRegBase + SPI_CTRL_REG, Reg);
}

STATIC
VOID
SpiActivateCs (
  IN SPI_DEVICE *Slave
  )
{
  UINT32 Reg;
  UINTN  SpiRegBase = Slave->HostRegisterBaseAddress;

  SpiSetCs(Slave);
  Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
  Reg |= SPI_CS_EN_MASK;
  MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
}

STATIC
VOID
SpiDeactivateCs (
  IN SPI_DEVICE *Slave
  )
{
  UINT32 Reg;
  UINTN  SpiRegBase = Slave->HostRegisterBaseAddress;

  Reg = MmioRead32 (SpiRegBase + SPI_CTRL_REG);
  Reg &= ~SPI_CS_EN_MASK;
  MmioWrite32(SpiRegBase + SPI_CTRL_REG, Reg);
}

STATIC
VOID
SpiSetupTransfer (
  IN MARVELL_SPI_MASTER_PROTOCOL *This,
  IN SPI_DEVICE *Slave
  )
{
  SPI_MASTER *SpiMaster;
  UINT32 Reg, CoreClock, SpiMaxFreq;
  UINTN SpiRegBase;

  SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This);

  // Initialize values from PCDs
  SpiRegBase  = Slave->HostRegisterBaseAddress;
  CoreClock   = Slave->CoreClock;
  SpiMaxFreq  = Slave->MaxFreq;

  EfiAcquireLock (&SpiMaster->Lock);

  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
  Reg |= SPI_BYTE_LENGTH;
  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);

  SpiSetCs(Slave);

  SpiSetBaudRate (Slave, CoreClock, SpiMaxFreq);

  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
  Reg &= ~(SPI_CPOL_MASK | SPI_CPHA_MASK | SPI_TXLSBF_MASK | SPI_RXLSBF_MASK);

  switch (Slave->Mode) {
  case SPI_MODE0:
    break;
  case SPI_MODE1:
    Reg |= SPI_CPHA_MASK;
    break;
  case SPI_MODE2:
    Reg |= SPI_CPOL_MASK;
    break;
  case SPI_MODE3:
    Reg |= SPI_CPOL_MASK;
    Reg |= SPI_CPHA_MASK;
    break;
  }

  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);

  EfiReleaseLock (&SpiMaster->Lock);
}

EFI_STATUS
EFIAPI
MvSpiTransfer (
  IN MARVELL_SPI_MASTER_PROTOCOL *This,
  IN SPI_DEVICE *Slave,
  IN UINTN DataByteCount,
  IN VOID *DataOut,
  IN VOID *DataIn,
  IN UINTN Flag
  )
{
  SPI_MASTER *SpiMaster;
  UINT64  Length;
  UINT32  Iterator, Reg;
  UINT8   *DataOutPtr = (UINT8 *)DataOut;
  UINT8   *DataInPtr  = (UINT8 *)DataIn;
  UINT8   DataToSend  = 0;
  UINTN   SpiRegBase;

  SpiMaster = SPI_MASTER_FROM_SPI_MASTER_PROTOCOL (This);

  SpiRegBase = Slave->HostRegisterBaseAddress;

  Length = 8 * DataByteCount;

  if (!EfiAtRuntime ()) {
    EfiAcquireLock (&SpiMaster->Lock);
  }

  if (Flag & SPI_TRANSFER_BEGIN) {
    SpiActivateCs (Slave);
  }

  // Set 8-bit mode
  Reg = MmioRead32 (SpiRegBase + SPI_CONF_REG);
  Reg &= ~SPI_BYTE_LENGTH;
  MmioWrite32 (SpiRegBase + SPI_CONF_REG, Reg);

  while (Length > 0) {
    if (DataOut != NULL) {
      DataToSend = *DataOutPtr & 0xFF;
    }
    // Transmit Data
    MmioWrite32 (SpiRegBase + SPI_INT_CAUSE_REG, 0x0);
    MmioWrite32 (SpiRegBase + SPI_DATA_OUT_REG, DataToSend);
    // Wait for memory ready
    for (Iterator = 0; Iterator < SPI_TIMEOUT; Iterator++) {
      if (MmioRead32 (SpiRegBase + SPI_INT_CAUSE_REG)) {
        if (DataInPtr != NULL) {
          *DataInPtr = MmioRead32 (SpiRegBase + SPI_DATA_IN_REG);
          DataInPtr++;
        }
        if (DataOutPtr != NULL) {
          DataOutPtr++;
        }
        Length -= 8;
        break;
      }
    }

    if (Iterator >= SPI_TIMEOUT) {
      DEBUG ((DEBUG_ERROR, "%a: Timeout\n", __FUNCTION__));
      return EFI_TIMEOUT;
    }
  }

  if (Flag & SPI_TRANSFER_END) {
    SpiDeactivateCs (Slave);
  }

  if (!EfiAtRuntime ()) {
    EfiReleaseLock (&SpiMaster->Lock);
  }

  return EFI_SUCCESS;
}

EFI_STATUS
EFIAPI
MvSpiReadWrite (
  IN  MARVELL_SPI_MASTER_PROTOCOL *This,
  IN  SPI_DEVICE *Slave,
  IN  UINT8 *Cmd,
  IN  UINTN CmdSize,
  IN  UINT8 *DataOut,
  OUT UINT8 *DataIn,
  IN  UINTN DataSize
  )
{
  EFI_STATUS Status;

  Status = MvSpiTransfer (This, Slave, CmdSize, Cmd, NULL, SPI_TRANSFER_BEGIN);
  if (EFI_ERROR (Status)) {
    Print (L"Spi Transfer Error\n");
    return EFI_DEVICE_ERROR;
  }

  Status = MvSpiTransfer (This, Slave, DataSize, DataOut, DataIn, SPI_TRANSFER_END);
  if (EFI_ERROR (Status)) {
    Print (L"Spi Transfer Error\n");
    return EFI_DEVICE_ERROR;
  }

  return EFI_SUCCESS;
}

EFI_STATUS
EFIAPI
MvSpiInit (
  IN MARVELL_SPI_MASTER_PROTOCOL * This
  )
{

  return EFI_SUCCESS;
}

SPI_DEVICE *
EFIAPI
MvSpiSetupSlave (
  IN MARVELL_SPI_MASTER_PROTOCOL *This,
  IN SPI_DEVICE *Slave,
  IN UINTN Cs,
  IN SPI_MODE Mode
  )
{
  if (!Slave) {
    Slave = AllocateZeroPool (sizeof(SPI_DEVICE));
    if (Slave == NULL) {
      DEBUG((DEBUG_ERROR, "Cannot allocate memory\n"));
      return NULL;
    }

    Slave->Cs   = Cs;
    Slave->Mode = Mode;
  }

  Slave->HostRegisterBaseAddress = PcdGet32 (PcdSpiRegBase);
  Slave->CoreClock = PcdGet32 (PcdSpiClockFrequency);
  Slave->MaxFreq = PcdGet32 (PcdSpiMaxFrequency);

  SpiSetupTransfer (This, Slave);

  return Slave;
}

EFI_STATUS
EFIAPI
MvSpiFreeSlave (
  IN SPI_DEVICE *Slave
  )
{
  FreePool (Slave);

  return EFI_SUCCESS;
}

EFI_STATUS
EFIAPI
MvSpiConfigRuntime (
  IN SPI_DEVICE *Slave
  )
{
  EFI_STATUS Status;
  UINTN AlignedAddress;

  //
  // Host register base may be not aligned to the page size,
  // which is not accepted when setting memory space attributes.
  // Add one aligned page of memory space which covers the host
  // controller registers.
  //
  AlignedAddress = Slave->HostRegisterBaseAddress & ~(SIZE_4KB - 1);

  Status = gDS->AddMemorySpace (EfiGcdMemoryTypeMemoryMappedIo,
                  AlignedAddress,
                  SIZE_4KB,
                  EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
  if (EFI_ERROR (Status)) {
    DEBUG ((DEBUG_ERROR, "%a: Failed to add memory space\n", __FUNCTION__));
    return Status;
  }

  Status = gDS->SetMemorySpaceAttributes (AlignedAddress,
                  SIZE_4KB,
                  EFI_MEMORY_UC | EFI_MEMORY_RUNTIME);
  if (EFI_ERROR (Status)) {
    DEBUG ((DEBUG_ERROR, "%a: Failed to set memory attributes\n", __FUNCTION__));
    gDS->RemoveMemorySpace (AlignedAddress, SIZE_4KB);
    return Status;
  }

  return EFI_SUCCESS;
}

STATIC
EFI_STATUS
SpiMasterInitProtocol (
  IN MARVELL_SPI_MASTER_PROTOCOL *SpiMasterProtocol
  )
{

  SpiMasterProtocol->Init        = MvSpiInit;
  SpiMasterProtocol->SetupDevice = MvSpiSetupSlave;
  SpiMasterProtocol->FreeDevice  = MvSpiFreeSlave;
  SpiMasterProtocol->Transfer    = MvSpiTransfer;
  SpiMasterProtocol->ReadWrite   = MvSpiReadWrite;
  SpiMasterProtocol->ConfigRuntime = MvSpiConfigRuntime;

  return EFI_SUCCESS;
}

EFI_STATUS
EFIAPI
SpiMasterEntryPoint (
  IN EFI_HANDLE       ImageHandle,
  IN EFI_SYSTEM_TABLE *SystemTable
  )
{
  EFI_STATUS  Status;

  mSpiMasterInstance = AllocateRuntimeZeroPool (sizeof (SPI_MASTER));
  if (mSpiMasterInstance == NULL) {
    return EFI_OUT_OF_RESOURCES;
  }

  EfiInitializeLock (&mSpiMasterInstance->Lock, TPL_NOTIFY);

  SpiMasterInitProtocol (&mSpiMasterInstance->SpiMasterProtocol);

  mSpiMasterInstance->Signature = SPI_MASTER_SIGNATURE;

  Status = gBS->InstallMultipleProtocolInterfaces (
                  &(mSpiMasterInstance->Handle),
                  &gMarvellSpiMasterProtocolGuid,
                  &(mSpiMasterInstance->SpiMasterProtocol),
                  NULL
                  );
  if (EFI_ERROR (Status)) {
    FreePool (mSpiMasterInstance);
    return EFI_DEVICE_ERROR;
  }

  return EFI_SUCCESS;
}