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authorLisa Hsu <Lisa.Hsu@amd.com>2011-03-31 18:20:12 -0700
committerLisa Hsu <Lisa.Hsu@amd.com>2011-03-31 18:20:12 -0700
commit01fc529bb2e2bf2021b5ec0c0e88136f1665abe6 (patch)
tree7c5a9fd1985b7ba88208de22012d70a2130f6673
parentd857105b5a56bf08f00f17f62a023d8ee3bbcc14 (diff)
downloadgem5-01fc529bb2e2bf2021b5ec0c0e88136f1665abe6.tar.xz
CacheMemory: add allocateVoid() that is == allocate() but no return value.
This function duplicates the functionality of allocate() exactly, except that it does not return a return value. In protocols where you just want to allocate a block but do not want that block to be your implicitly passed cache_entry, use this function. Otherwise, SLICC will complain if you do not consume the pointer returned by allocate(), and if you do a dummy assignment Entry foo := cache.allocate(address), the C++ compiler will complain of an unused variable. This is kind of a hack to get around those issues, but suggestions welcome.
-rw-r--r--src/mem/protocol/RubySlicc_Types.sm1
-rw-r--r--src/mem/ruby/system/CacheMemory.hh4
-rw-r--r--src/mem/ruby/system/WireBuffer.hh3
-rw-r--r--src/mem/ruby/system/WireBuffer.py1
4 files changed, 6 insertions, 3 deletions
diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index 7d444ab57..cf0f64500 100644
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -134,6 +134,7 @@ structure (CacheMemory, external = "yes") {
bool cacheAvail(Address);
Address cacheProbe(Address);
AbstractCacheEntry allocate(Address, AbstractCacheEntry);
+ void allocateVoid(Address, AbstractCacheEntry);
void deallocate(Address);
AbstractCacheEntry lookup(Address);
bool isTagPresent(Address);
diff --git a/src/mem/ruby/system/CacheMemory.hh b/src/mem/ruby/system/CacheMemory.hh
index 197ac9f40..e2e9a429e 100644
--- a/src/mem/ruby/system/CacheMemory.hh
+++ b/src/mem/ruby/system/CacheMemory.hh
@@ -83,6 +83,10 @@ class CacheMemory : public SimObject
// find an unused entry and sets the tag appropriate for the address
AbstractCacheEntry* allocate(const Address& address, AbstractCacheEntry* new_entry);
+ void allocateVoid(const Address& address, AbstractCacheEntry* new_entry)
+ {
+ allocate(address, new_entry);
+ }
// Explicitly free up this address
void deallocate(const Address& address);
diff --git a/src/mem/ruby/system/WireBuffer.hh b/src/mem/ruby/system/WireBuffer.hh
index 1404f5561..b34488fb1 100644
--- a/src/mem/ruby/system/WireBuffer.hh
+++ b/src/mem/ruby/system/WireBuffer.hh
@@ -54,7 +54,7 @@
/////////////////////////////////////////////////////////////////////////////
class Consumer;
-class Message; // I added this and removed Message.hh
+class Message;
class WireBuffer : public SimObject
{
@@ -88,7 +88,6 @@ class WireBuffer : public SimObject
void clearStats() const;
void printStats(std::ostream& out) const;
-// int m_dummy;
uint64_t m_msg_counter;
private:
diff --git a/src/mem/ruby/system/WireBuffer.py b/src/mem/ruby/system/WireBuffer.py
index 0bcc291bb..bca19b4df 100644
--- a/src/mem/ruby/system/WireBuffer.py
+++ b/src/mem/ruby/system/WireBuffer.py
@@ -28,7 +28,6 @@
from m5.params import *
from m5.SimObject import SimObject
-#from Controller import RubyController
class RubyWireBuffer(SimObject):
type = 'RubyWireBuffer'