summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorKorey Sewell <ksewell@umich.edu>2006-07-06 12:18:55 -0400
committerKorey Sewell <ksewell@umich.edu>2006-07-06 12:18:55 -0400
commit03fa13b27ce461886dceef82af0d3e994b5b9288 (patch)
treee162c07d55f9fab7f6ad5e29481f9ae2c44f913d
parent215041215b06f330d072b0537d7fe70739b4927d (diff)
downloadgem5-03fa13b27ce461886dceef82af0d3e994b5b9288.tar.xz
Use O3DynInst in cpu_models.py and in static_inst_exec_sigs.hh instead of a specific ISA dyn. inst.
src/cpu/cpu_models.py: Use O3DynInst src/cpu/o3/dyn_inst.hh: declare O3DynInst here based off of ISA ... this must be updated for each ISA. src/cpu/static_inst.hh: take out O3 forward declarations here and include header file to keep this file clean --HG-- extra : convert_revision : 0d65463479c3cfc2d1154935b1032dae32c5efd0
-rw-r--r--src/cpu/cpu_models.py4
-rw-r--r--src/cpu/o3/dyn_inst.hh15
-rw-r--r--src/cpu/static_inst.hh6
3 files changed, 13 insertions, 12 deletions
diff --git a/src/cpu/cpu_models.py b/src/cpu/cpu_models.py
index ccaceeff3..5b0c6c4da 100644
--- a/src/cpu/cpu_models.py
+++ b/src/cpu/cpu_models.py
@@ -80,5 +80,5 @@ CpuModel('CheckerCPU', 'checker_cpu_exec.cc',
'#include "cpu/checker/cpu.hh"',
{ 'CPU_exec_context': 'CheckerCPU' })
CpuModel('O3CPU', 'o3_cpu_exec.cc',
- '#include "cpu/o3/alpha/dyn_inst.hh"',
- { 'CPU_exec_context': 'AlphaDynInst<AlphaSimpleImpl>' })
+ '#include "cpu/o3/isa_specific.hh"',
+ { 'CPU_exec_context': 'O3DynInst' })
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index d029488fd..34afa2d1b 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2004-2005 The Regents of The University of Michigan
+ * Copyright (c) 2006 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -25,15 +25,20 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- * Authors: Kevin Lim
+ * Authors: Korey Sewell
*/
#ifndef __CPU_O3_DYN_INST_HH__
#define __CPU_O3_DYN_INST_HH__
-#include "cpu/o3/isa_specific.hh"
-/** The O3Impl to be used. */
-typedef DynInst O3DynInst;
+#if THE_ISA == ALPHA_ISA
+template <class Impl>
+class AlphaDynInst;
+
+struct AlphaSimpleImpl;
+
+typedef AlphaDynInst<AlphaSimpleImpl> O3DynInst;
+#endif
#endif // __CPU_O3_DYN_INST_HH__
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 19f06f669..ea1a65148 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -39,6 +39,7 @@
#include "base/misc.hh"
#include "base/refcnt.hh"
#include "cpu/op_class.hh"
+#include "cpu/o3/dyn_inst.hh"
#include "sim/host.hh"
#include "arch/isa_traits.hh"
@@ -51,11 +52,6 @@ class DynInst;
class Packet;
template <class Impl>
-class AlphaDynInst;
-
-//class O3DynInst;
-
-template <class Impl>
class OzoneDynInst;
class CheckerCPU;