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authorAndreas Hansson <andreas.hansson@arm.com>2015-07-03 10:14:40 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-07-03 10:14:40 -0400
commit0ddde83a47e8a129de1a5c00475772c6ac0fd004 (patch)
tree0b49eb8b61a7a8ce9ec2e0b340999b9b78d8c7ab
parent893533a1264bb369b47f74493adf30ce22829f34 (diff)
downloadgem5-0ddde83a47e8a129de1a5c00475772c6ac0fd004.tar.xz
mem: Add ReadCleanReq and ReadSharedReq packets
This patch adds two new read requests packets: ReadCleanReq - For a cache to explicitly request clean data. The response is thus exclusive or shared, but not owned or modified. The read-only caches (see previous patch) use this request type to ensure they do not get dirty data. ReadSharedReq - We add this to distinguish cache read requests from those issued by other masters, such as devices and CPUs. Thus, devices use ReadReq, and caches use ReadCleanReq, ReadExReq, or ReadSharedReq. For the latter, the response can be any state, shared, exclusive, owned or even modified. Both ReadCleanReq and ReadSharedReq re-use the normal ReadResp. The two transactions are aligned with the emerging cache-coherent TLM standard and the AMBA nomenclature. With this change, the normal ReadReq should never be used by a cache, and is reserved for the actual (non-caching) masters in the system. We thus have a way of identifying if a request came from a cache or not. The introduction of ReadSharedReq thus removes the need for the current isTopLevel hack, and also allows us to stop relying on checking the packet size to determine if the source is a cache or not. This is fixed in follow-on patches.
-rw-r--r--src/mem/cache/base.cc3
-rw-r--r--src/mem/cache/cache_impl.hh12
-rw-r--r--src/mem/packet.cc18
-rw-r--r--src/mem/packet.hh2
4 files changed, 28 insertions, 7 deletions
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index af504d9bc..b1c512079 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -190,7 +190,8 @@ BaseCache::regStats()
// to change the subset of commands that are considered "demand" vs
// "non-demand"
#define SUM_DEMAND(s) \
- (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq])
+ (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + \
+ s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq])
// should writebacks be included here? prior code was inconsistent...
#define SUM_NON_DEMAND(s) \
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 5a9205894..1955b9001 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -184,6 +184,10 @@ Cache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
// special handling for coherent block requests from
// upper-level caches
if (pkt->needsExclusive()) {
+ // sanity check
+ assert(pkt->cmd == MemCmd::ReadExReq ||
+ pkt->cmd == MemCmd::SCUpgradeFailReq);
+
// if we have a dirty copy, make sure the recipient
// keeps it marked dirty
if (blk->isDirty()) {
@@ -193,8 +197,9 @@ Cache::satisfyCpuSideRequest(PacketPtr pkt, CacheBlk *blk,
if (blk != tempBlock)
tags->invalidate(blk);
blk->invalidate();
- } else if (blk->isWritable() && !pending_downgrade
- && !pkt->sharedAsserted() && !pkt->req->isInstFetch()) {
+ } else if (blk->isWritable() && !pending_downgrade &&
+ !pkt->sharedAsserted() &&
+ pkt->cmd != MemCmd::ReadCleanReq) {
// we can give the requester an exclusive copy (by not
// asserting shared line) on a read request if:
// - we have an exclusive copy at this level (& below)
@@ -901,7 +906,8 @@ Cache::getBusPacket(PacketPtr cpu_pkt, CacheBlk *blk,
cmd = cpu_pkt->cmd;
} else {
// block is invalid
- cmd = needsExclusive ? MemCmd::ReadExReq : MemCmd::ReadReq;
+ cmd = needsExclusive ? MemCmd::ReadExReq :
+ (isReadOnly ? MemCmd::ReadCleanReq : MemCmd::ReadSharedReq);
}
PacketPtr pkt = new Packet(cpu_pkt->req, cmd, blkSize);
diff --git a/src/mem/packet.cc b/src/mem/packet.cc
index 68a5e6dc2..f584c204f 100644
--- a/src/mem/packet.cc
+++ b/src/mem/packet.cc
@@ -71,7 +71,8 @@ MemCmd::commandInfo[] =
{
/* InvalidCmd */
{ 0, InvalidCmd, "InvalidCmd" },
- /* ReadReq */
+ /* ReadReq - Read issued by a non-caching agent such as a CPU or
+ * device, with no restrictions on alignment. */
{ SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadReq" },
/* ReadResp */
{ SET3(IsRead, IsResponse, HasData), InvalidCmd, "ReadResp" },
@@ -125,12 +126,23 @@ MemCmd::commandInfo[] =
* that it has failed, acquires line as Dirty*/
{ SET4(IsRead, NeedsExclusive, IsResponse, HasData),
InvalidCmd, "UpgradeFailResp" },
- /* ReadExReq */
+ /* ReadExReq - Read issues by a cache, always cache-line aligned,
+ * and the response is guaranteed to be writeable (exclusive or
+ * even modified) */
{ SET5(IsRead, NeedsExclusive, IsInvalidate, IsRequest, NeedsResponse),
ReadExResp, "ReadExReq" },
- /* ReadExResp */
+ /* ReadExResp - Response matching a read exclusive, as we check
+ * the need for exclusive also on responses */
{ SET4(IsRead, NeedsExclusive, IsResponse, HasData),
InvalidCmd, "ReadExResp" },
+ /* ReadCleanReq - Read issued by a cache, always cache-line
+ * aligned, and the response is guaranteed to not contain dirty data
+ * (exclusive or shared).*/
+ { SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadCleanReq" },
+ /* ReadSharedReq - Read issued by a cache, always cache-line
+ * aligned, response is shared, possibly exclusive, owned or even
+ * modified. */
+ { SET3(IsRead, IsRequest, NeedsResponse), ReadResp, "ReadSharedReq" },
/* LoadLockedReq: note that we use plain ReadResp as response, so that
* we can also use ReadRespWithInvalidate when needed */
{ SET4(IsRead, IsLlsc, IsRequest, NeedsResponse),
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
index 192136aba..49a50125e 100644
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -101,6 +101,8 @@ class MemCmd
UpgradeFailResp, // Valid for SCUpgradeReq only
ReadExReq,
ReadExResp,
+ ReadCleanReq,
+ ReadSharedReq,
LoadLockedReq,
StoreCondReq,
StoreCondFailReq, // Failed StoreCondReq in MSHR (never sent)