diff options
| author | Korey Sewell <ksewell@umich.edu> | 2011-07-15 21:26:18 -0400 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-07-15 21:26:18 -0400 |
| commit | 145deb7c88e38d84a747c1984d772218d527b529 (patch) | |
| tree | 19e2e8e6e2db77127480d228edceeee15d192ebd | |
| parent | 147095cb0886a962620e60b6950a68931fbd734a (diff) | |
| download | gem5-145deb7c88e38d84a747c1984d772218d527b529.tar.xz | |
inorder-fs: temp. regression removal
remove this regression till the fix for the hwrei instruction is put in
5 files changed, 0 insertions, 1977 deletions
diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/config.ini b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/config.ini deleted file mode 100644 index a3d5d3586..000000000 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/config.ini +++ /dev/null @@ -1,1168 +0,0 @@ -[root] -type=Root -children=system -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=LinuxAlphaSystem -children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami -boot_cpu_frequency=500 -boot_osflags=root=/dev/hda1 console=ttyS0 -console=/chips/pd/randd/dist/binaries/console -init_param=0 -kernel=/chips/pd/randd/dist/binaries/vmlinux -load_addr_mask=1099511627775 -mem_mode=timing -pal=/chips/pd/randd/dist/binaries/ts_osfpal -physmem=system.physmem -readfile=tests/halt.sh -symbolfile= -system_rev=1024 -system_type=34 -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 - -[system.bridge] -type=Bridge -delay=50000 -filter_ranges_a=0:18446744073709551615 -filter_ranges_b=0:8589934591 -nack_delay=4000 -req_size_a=16 -req_size_b=16 -resp_size_a=16 -resp_size_b=16 -write_ack=false -side_a=system.iobus.port[0] -side_b=system.membus.port[0] - -[system.cpu] -type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer -BTBEntries=4096 -BTBTagSize=16 -LFSTSize=1024 -LQEntries=32 -RASSize=16 -SQEntries=32 -SSITSize=1024 -activity=0 -backComSize=5 -cachePorts=200 -checker=Null -choiceCtrBits=2 -choicePredictorSize=8192 -clock=500 -commitToDecodeDelay=1 -commitToFetchDelay=1 -commitToIEWDelay=1 -commitToRenameDelay=1 -commitWidth=8 -cpu_id=0 -decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -defer_registration=false -dispatchWidth=8 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -fetchToDecodeDelay=1 -fetchTrapLatency=1 -fetchWidth=8 -forwardComSize=5 -fuPool=system.cpu.fuPool -function_trace=false -function_trace_start=0 -globalCtrBits=2 -globalHistoryBits=13 -globalPredictorSize=8192 -iewToCommitDelay=1 -iewToDecodeDelay=1 -iewToFetchDelay=1 -iewToRenameDelay=1 -instShiftAmt=2 -interrupts=system.cpu.interrupts -issueToExecuteDelay=1 -issueWidth=8 -itb=system.cpu.itb -localCtrBits=2 -localHistoryBits=11 -localHistoryTableSize=2048 -localPredictorSize=2048 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -numIQEntries=64 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 -numRobs=1 -numThreads=1 -phase=0 -predType=tournament -profile=0 -progress_interval=0 -renameToDecodeDelay=1 -renameToFetchDelay=1 -renameToIEWDelay=2 -renameToROBDelay=1 -renameWidth=8 -smtCommitPolicy=RoundRobin -smtFetchPolicy=SingleThread -smtIQPolicy=Partitioned -smtIQThreshold=100 -smtLSQPolicy=Partitioned -smtLSQThreshold=100 -smtNumFetchingThreads=1 -smtROBPolicy=Partitioned -smtROBThreshold=100 -squashWidth=8 -system=system -tracer=system.cpu.tracer -trapLatency=13 -wbDepth=1 -wbWidth=8 -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.dcache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=4 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=32768 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.port[2] - -[system.cpu.dtb] -type=AlphaTLB -size=64 - -[system.cpu.fuPool] -type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 - -[system.cpu.fuPool.FUList0] -type=FUDesc -children=opList -count=6 -opList=system.cpu.fuPool.FUList0.opList - -[system.cpu.fuPool.FUList0.opList] -type=OpDesc -issueLat=1 -opClass=IntAlu -opLat=1 - -[system.cpu.fuPool.FUList1] -type=FUDesc -children=opList0 opList1 -count=2 -opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 - -[system.cpu.fuPool.FUList1.opList0] -type=OpDesc -issueLat=1 -opClass=IntMult -opLat=3 - -[system.cpu.fuPool.FUList1.opList1] -type=OpDesc -issueLat=19 -opClass=IntDiv -opLat=20 - -[system.cpu.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 - -[system.cpu.fuPool.FUList2.opList0] -type=OpDesc -issueLat=1 -opClass=FloatAdd -opLat=2 - -[system.cpu.fuPool.FUList2.opList1] -type=OpDesc -issueLat=1 -opClass=FloatCmp -opLat=2 - -[system.cpu.fuPool.FUList2.opList2] -type=OpDesc -issueLat=1 -opClass=FloatCvt -opLat=2 - -[system.cpu.fuPool.FUList3] -type=FUDesc -children=opList0 opList1 opList2 -count=2 -opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 - -[system.cpu.fuPool.FUList3.opList0] -type=OpDesc -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu.fuPool.FUList3.opList1] -type=OpDesc -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu.fuPool.FUList3.opList2] -type=OpDesc -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu.fuPool.FUList4] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList4.opList - -[system.cpu.fuPool.FUList4.opList] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList5] -type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 -opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 - -[system.cpu.fuPool.FUList5.opList00] -type=OpDesc -issueLat=1 -opClass=SimdAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList01] -type=OpDesc -issueLat=1 -opClass=SimdAddAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList02] -type=OpDesc -issueLat=1 -opClass=SimdAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList03] -type=OpDesc -issueLat=1 -opClass=SimdCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList04] -type=OpDesc -issueLat=1 -opClass=SimdCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList05] -type=OpDesc -issueLat=1 -opClass=SimdMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList06] -type=OpDesc -issueLat=1 -opClass=SimdMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList07] -type=OpDesc -issueLat=1 -opClass=SimdMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList08] -type=OpDesc -issueLat=1 -opClass=SimdShift -opLat=1 - -[system.cpu.fuPool.FUList5.opList09] -type=OpDesc -issueLat=1 -opClass=SimdShiftAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList10] -type=OpDesc -issueLat=1 -opClass=SimdSqrt -opLat=1 - -[system.cpu.fuPool.FUList5.opList11] -type=OpDesc -issueLat=1 -opClass=SimdFloatAdd -opLat=1 - -[system.cpu.fuPool.FUList5.opList12] -type=OpDesc -issueLat=1 -opClass=SimdFloatAlu -opLat=1 - -[system.cpu.fuPool.FUList5.opList13] -type=OpDesc -issueLat=1 -opClass=SimdFloatCmp -opLat=1 - -[system.cpu.fuPool.FUList5.opList14] -type=OpDesc -issueLat=1 -opClass=SimdFloatCvt -opLat=1 - -[system.cpu.fuPool.FUList5.opList15] -type=OpDesc -issueLat=1 -opClass=SimdFloatDiv -opLat=1 - -[system.cpu.fuPool.FUList5.opList16] -type=OpDesc -issueLat=1 -opClass=SimdFloatMisc -opLat=1 - -[system.cpu.fuPool.FUList5.opList17] -type=OpDesc -issueLat=1 -opClass=SimdFloatMult -opLat=1 - -[system.cpu.fuPool.FUList5.opList18] -type=OpDesc -issueLat=1 -opClass=SimdFloatMultAcc -opLat=1 - -[system.cpu.fuPool.FUList5.opList19] -type=OpDesc -issueLat=1 -opClass=SimdFloatSqrt -opLat=1 - -[system.cpu.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -opList=system.cpu.fuPool.FUList6.opList - -[system.cpu.fuPool.FUList6.opList] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 -opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 - -[system.cpu.fuPool.FUList7.opList0] -type=OpDesc -issueLat=1 -opClass=MemRead -opLat=1 - -[system.cpu.fuPool.FUList7.opList1] -type=OpDesc -issueLat=1 -opClass=MemWrite -opLat=1 - -[system.cpu.fuPool.FUList8] -type=FUDesc -children=opList -count=1 -opList=system.cpu.fuPool.FUList8.opList - -[system.cpu.fuPool.FUList8.opList] -type=OpDesc -issueLat=3 -opClass=IprAccess -opLat=3 - -[system.cpu.icache] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=1 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=true -latency=1000 -max_miss_count=0 -mshrs=4 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=10000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=32768 -subblock_size=0 -tgts_per_mshr=20 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.port[1] - -[system.cpu.interrupts] -type=AlphaInterrupts - -[system.cpu.itb] -type=AlphaTLB -size=48 - -[system.cpu.tracer] -type=ExeTracer - -[system.disk0] -type=IdeDisk -children=image -delay=1000000 -driveID=master -image=system.disk0.image - -[system.disk0.image] -type=CowDiskImage -children=child -child=system.disk0.image.child -image_file= -read_only=false -table_size=65536 - -[system.disk0.image.child] -type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img -read_only=true - -[system.disk2] -type=IdeDisk -children=image -delay=1000000 -driveID=master -image=system.disk2.image - -[system.disk2.image] -type=CowDiskImage -children=child -child=system.disk2.image.child -image_file= -read_only=false -table_size=65536 - -[system.disk2.image.child] -type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-bigswap2.img -read_only=true - -[system.intrctrl] -type=IntrControl -sys=system - -[system.iobus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=true -width=64 -default=system.tsunami.pciconfig.pio -port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma - -[system.iocache] -type=BaseCache -addr_range=0:8589934591 -assoc=8 -block_size=64 -forward_snoops=false -hash_delay=1 -is_top_level=true -latency=50000 -max_miss_count=0 -mshrs=20 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=500000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=1024 -subblock_size=0 -tgts_per_mshr=12 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.iobus.port[28] -mem_side=system.membus.port[2] - -[system.l2c] -type=BaseCache -addr_range=0:18446744073709551615 -assoc=8 -block_size=64 -forward_snoops=true -hash_delay=1 -is_top_level=false -latency=10000 -max_miss_count=0 -mshrs=92 -num_cpus=1 -prefetch_data_accesses_only=false -prefetch_degree=1 -prefetch_latency=100000 -prefetch_on_access=false -prefetch_past_page=false -prefetch_policy=none -prefetch_serial_squash=false -prefetch_use_cpu_id=true -prefetcher_size=100 -prioritizeRequests=false -repl=Null -size=4194304 -subblock_size=0 -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.port[0] -mem_side=system.membus.port[3] - -[system.membus] -type=Bus -children=badaddr_responder -block_size=64 -bus_id=1 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -default=system.membus.badaddr_responder.pio -port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side - -[system.membus.badaddr_responder] -type=IsaFake -pio_addr=0 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=true -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.membus.default - -[system.physmem] -type=PhysicalMemory -file= -latency=30000 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.membus.port[1] - -[system.simple_disk] -type=SimpleDisk -children=disk -disk=system.simple_disk.disk -system=system - -[system.simple_disk.disk] -type=RawDiskImage -image_file=/chips/pd/randd/dist/disks/linux-latest.img -read_only=true - -[system.terminal] -type=Terminal -intr_control=system.intrctrl -number=0 -output=true -port=3456 - -[system.toL2Bus] -type=Bus -block_size=64 -bus_id=0 -clock=1000 -header_cycles=1 -use_default_range=false -width=64 -port=system.l2c.cpu_side system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.tsunami] -type=Tsunami -children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart -intrctrl=system.intrctrl -system=system - -[system.tsunami.backdoor] -type=AlphaBackdoor -cpu=system.cpu -disk=system.simple_disk -pio_addr=8804682956800 -pio_latency=1000 -platform=system.tsunami -system=system -terminal=system.terminal -pio=system.iobus.port[25] - -[system.tsunami.cchip] -type=TsunamiCChip -pio_addr=8803072344064 -pio_latency=1000 -platform=system.tsunami -system=system -tsunami=system.tsunami -pio=system.iobus.port[1] - -[system.tsunami.ethernet] -type=NSGigE -BAR0=1 -BAR0LegacyIO=false -BAR0Size=256 -BAR1=0 -BAR1LegacyIO=false -BAR1Size=4096 -BAR2=0 -BAR2LegacyIO=false -BAR2Size=0 -BAR3=0 -BAR3LegacyIO=false -BAR3Size=0 -BAR4=0 -BAR4LegacyIO=false -BAR4Size=0 -BAR5=0 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CardbusCIS=0 -ClassCode=2 -Command=0 -DeviceID=34 -ExpansionROM=0 -HeaderType=0 -InterruptLine=30 -InterruptPin=1 -LatencyTimer=0 -MaximumLatency=52 -MinimumGrant=176 -ProgIF=0 -Revision=0 -Status=656 -SubClassCode=0 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=4107 -clock=0 -config_latency=20000 -dma_data_free=false -dma_desc_free=false -dma_no_allocate=true -dma_read_delay=0 -dma_read_factor=0 -dma_write_delay=0 -dma_write_factor=0 -hardware_address=00:90:00:00:00:01 -intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=1 -pci_func=0 -pio_latency=1000 -platform=system.tsunami -rss=false -rx_delay=1000000 -rx_fifo_size=524288 -rx_filter=true -rx_thread=false -system=system -tx_delay=1000000 -tx_fifo_size=524288 -tx_thread=false -config=system.iobus.port[29] -dma=system.iobus.port[30] -pio=system.iobus.port[27] - -[system.tsunami.fake_OROM] -type=IsaFake -pio_addr=8796093677568 -pio_latency=1000 -pio_size=393216 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[9] - -[system.tsunami.fake_ata0] -type=IsaFake -pio_addr=8804615848432 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[20] - -[system.tsunami.fake_ata1] -type=IsaFake -pio_addr=8804615848304 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[21] - -[system.tsunami.fake_pnp_addr] -type=IsaFake -pio_addr=8804615848569 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[10] - -[system.tsunami.fake_pnp_read0] -type=IsaFake -pio_addr=8804615848451 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[12] - -[system.tsunami.fake_pnp_read1] -type=IsaFake -pio_addr=8804615848515 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[13] - -[system.tsunami.fake_pnp_read2] -type=IsaFake -pio_addr=8804615848579 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[14] - -[system.tsunami.fake_pnp_read3] -type=IsaFake -pio_addr=8804615848643 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[15] - -[system.tsunami.fake_pnp_read4] -type=IsaFake -pio_addr=8804615848707 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[16] - -[system.tsunami.fake_pnp_read5] -type=IsaFake -pio_addr=8804615848771 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[17] - -[system.tsunami.fake_pnp_read6] -type=IsaFake -pio_addr=8804615848835 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[18] - -[system.tsunami.fake_pnp_read7] -type=IsaFake -pio_addr=8804615848899 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[19] - -[system.tsunami.fake_pnp_write] -type=IsaFake -pio_addr=8804615850617 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[11] - -[system.tsunami.fake_ppc] -type=IsaFake -pio_addr=8804615848891 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[8] - -[system.tsunami.fake_sm_chip] -type=IsaFake -pio_addr=8804615848816 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[3] - -[system.tsunami.fake_uart1] -type=IsaFake -pio_addr=8804615848696 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[4] - -[system.tsunami.fake_uart2] -type=IsaFake -pio_addr=8804615848936 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[5] - -[system.tsunami.fake_uart3] -type=IsaFake -pio_addr=8804615848680 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[6] - -[system.tsunami.fake_uart4] -type=IsaFake -pio_addr=8804615848944 -pio_latency=1000 -pio_size=8 -platform=system.tsunami -ret_bad_addr=false -ret_data16=65535 -ret_data32=4294967295 -ret_data64=18446744073709551615 -ret_data8=255 -system=system -update_data=false -warn_access= -pio=system.iobus.port[7] - -[system.tsunami.fb] -type=BadDevice -devicename=FrameBuffer -pio_addr=8804615848912 -pio_latency=1000 -platform=system.tsunami -system=system -pio=system.iobus.port[22] - -[system.tsunami.ide] -type=IdeController -BAR0=1 -BAR0LegacyIO=false -BAR0Size=8 -BAR1=1 -BAR1LegacyIO=false -BAR1Size=4 -BAR2=1 -BAR2LegacyIO=false -BAR2Size=8 -BAR3=1 -BAR3LegacyIO=false -BAR3Size=4 -BAR4=1 -BAR4LegacyIO=false -BAR4Size=16 -BAR5=1 -BAR5LegacyIO=false -BAR5Size=0 -BIST=0 -CacheLineSize=0 -CardbusCIS=0 -ClassCode=1 -Command=0 -DeviceID=28945 -ExpansionROM=0 -HeaderType=0 -InterruptLine=31 -InterruptPin=1 -LatencyTimer=0 -MaximumLatency=0 -MinimumGrant=0 -ProgIF=133 -Revision=0 -Status=640 -SubClassCode=1 -SubsystemID=0 -SubsystemVendorID=0 -VendorID=32902 -config_latency=20000 -ctrl_offset=0 -disks=system.disk0 system.disk2 -io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 -pci_bus=0 -pci_dev=0 -pci_func=0 -pio_latency=1000 -platform=system.tsunami -system=system -config=system.iobus.port[31] -dma=system.iobus.port[32] -pio=system.iobus.port[26] - -[system.tsunami.io] -type=TsunamiIO -frequency=976562500 -pio_addr=8804615847936 -pio_latency=1000 -platform=system.tsunami -system=system -time=Thu Jan 1 00:00:00 2009 -tsunami=system.tsunami -year_is_bcd=false -pio=system.iobus.port[23] - -[system.tsunami.pchip] -type=TsunamiPChip -pio_addr=8802535473152 -pio_latency=1000 -platform=system.tsunami -system=system -tsunami=system.tsunami -pio=system.iobus.port[2] - -[system.tsunami.pciconfig] -type=PciConfigAll -bus=0 -pio_latency=1 -platform=system.tsunami -size=16777216 -system=system -pio=system.iobus.default - -[system.tsunami.uart] -type=Uart8250 -pio_addr=8804615848952 -pio_latency=1000 -platform=system.tsunami -system=system -terminal=system.terminal -pio=system.iobus.port[24] - diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/simerr b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/simerr deleted file mode 100755 index 0bcb6e870..000000000 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/simerr +++ /dev/null @@ -1,5 +0,0 @@ -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: Prefetch instructions in Alpha do not do anything -warn: Prefetch instructions in Alpha do not do anything -hack: be nice to actually delete the event here diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/simout b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/simout deleted file mode 100755 index e4b944617..000000000 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/simout +++ /dev/null @@ -1,11 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jun 19 2011 18:17:08 -gem5 started Jun 19 2011 18:17:16 -gem5 executing on m60-009.pool -command line: build/ALPHA_FS/gem5.fast -d build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-inorder -re tests/run.py build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-inorder -Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux -info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1899194993500 because m5_exit instruction encountered diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/stats.txt b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/stats.txt deleted file mode 100644 index c477a0994..000000000 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/stats.txt +++ /dev/null @@ -1,685 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 1.899195 # Number of seconds simulated -sim_ticks 1899194993500 # Number of ticks simulated -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 102570 # Simulator instruction rate (inst/s) -host_tick_rate 2450099766 # Simulator tick rate (ticks/s) -host_mem_usage 278932 # Number of bytes of host memory used -host_seconds 775.15 # Real time elapsed on the host -sim_insts 79507003 # Number of instructions simulated -system.l2c.replacements 389890 # number of replacements -system.l2c.tagsinuse 34369.845754 # Cycle average of tags in use -system.l2c.total_refs 2354607 # Total number of references to valid blocks. -system.l2c.sampled_refs 422592 # Sample count of references to valid blocks. -system.l2c.avg_refs 5.571821 # Average number of references to valid blocks. -system.l2c.warmup_cycle 5902814000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::0 11156.941025 # Average occupied blocks per context -system.l2c.occ_blocks::1 23212.904730 # Average occupied blocks per context -system.l2c.occ_percent::0 0.170241 # Average percentage of cache occupancy -system.l2c.occ_percent::1 0.354201 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::0 1754804 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1754804 # number of ReadReq hits -system.l2c.Writeback_hits::0 825539 # number of Writeback hits -system.l2c.Writeback_hits::total 825539 # number of Writeback hits -system.l2c.UpgradeReq_hits::0 7 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 7 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::0 188732 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 188732 # number of ReadExReq hits -system.l2c.demand_hits::0 1943536 # number of demand (read+write) hits -system.l2c.demand_hits::1 0 # number of demand (read+write) hits -system.l2c.demand_hits::total 1943536 # number of demand (read+write) hits -system.l2c.overall_hits::0 1943536 # number of overall hits -system.l2c.overall_hits::1 0 # number of overall hits -system.l2c.overall_hits::total 1943536 # number of overall hits -system.l2c.ReadReq_misses::0 304763 # number of ReadReq misses -system.l2c.ReadReq_misses::total 304763 # number of ReadReq misses -system.l2c.UpgradeReq_misses::0 7 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::0 118469 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 118469 # number of ReadExReq misses -system.l2c.demand_misses::0 423232 # number of demand (read+write) misses -system.l2c.demand_misses::1 0 # number of demand (read+write) misses -system.l2c.demand_misses::total 423232 # number of demand (read+write) misses -system.l2c.overall_misses::0 423232 # number of overall misses -system.l2c.overall_misses::1 0 # number of overall misses -system.l2c.overall_misses::total 423232 # number of overall misses -system.l2c.ReadReq_miss_latency 15864418500 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency 249000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency 6171282500 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency 22035701000 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency 22035701000 # number of overall miss cycles -system.l2c.ReadReq_accesses::0 2059567 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2059567 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::0 825539 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 825539 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::0 14 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::0 307201 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 307201 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::0 2366768 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 0 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2366768 # number of demand (read+write) accesses -system.l2c.overall_accesses::0 2366768 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 0 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2366768 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::0 0.147974 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::0 0.500000 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::0 0.385640 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::0 0.178823 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses -system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses -system.l2c.overall_miss_rate::0 0.178823 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses -system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::0 52054.936131 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::0 35571.428571 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::0 52091.960766 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::0 52065.299883 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 inf # average overall miss latency -system.l2c.demand_avg_miss_latency::total inf # average overall miss latency -system.l2c.overall_avg_miss_latency::0 52065.299883 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 inf # average overall miss latency -system.l2c.overall_avg_miss_latency::total inf # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks 116891 # number of writebacks -system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits 0 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses 304763 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses 7 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses 118469 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses 423232 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses 423232 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency 12196601000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency 321000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency 4740688000 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency 16937289000 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency 16937289000 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency 811651000 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency 1119429000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency 1931080000 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::0 0.147974 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::0 0.500000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::0 0.385640 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::0 0.178823 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::0 0.178823 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency 40019.953210 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 45857.142857 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 40016.274300 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency 40018.923427 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency 40018.923427 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated -system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.305719 # Cycle average of tags in use -system.iocache.total_refs 0 # Total number of references to valid blocks. -system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. -system.iocache.avg_refs 0 # Average number of references to valid blocks. -system.iocache.warmup_cycle 1740606093000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::1 1.305719 # Average occupied blocks per context -system.iocache.occ_percent::1 0.081607 # Average percentage of cache occupancy -system.iocache.demand_hits::0 0 # number of demand (read+write) hits -system.iocache.demand_hits::1 0 # number of demand (read+write) hits -system.iocache.demand_hits::total 0 # number of demand (read+write) hits -system.iocache.overall_hits::0 0 # number of overall hits -system.iocache.overall_hits::1 0 # number of overall hits -system.iocache.overall_hits::total 0 # number of overall hits -system.iocache.ReadReq_misses::1 173 # number of ReadReq misses -system.iocache.ReadReq_misses::total 173 # number of ReadReq misses -system.iocache.WriteReq_misses::1 41552 # number of WriteReq misses -system.iocache.WriteReq_misses::total 41552 # number of WriteReq misses -system.iocache.demand_misses::0 0 # number of demand (read+write) misses -system.iocache.demand_misses::1 41725 # number of demand (read+write) misses -system.iocache.demand_misses::total 41725 # number of demand (read+write) misses -system.iocache.overall_misses::0 0 # number of overall misses -system.iocache.overall_misses::1 41725 # number of overall misses -system.iocache.overall_misses::total 41725 # number of overall misses -system.iocache.ReadReq_miss_latency 19963998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency 5720707806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency 5740671804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency 5740671804 # number of overall miss cycles -system.iocache.ReadReq_accesses::1 173 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses) -system.iocache.WriteReq_accesses::1 41552 # number of WriteReq accesses(hits+misses) -system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses) -system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses -system.iocache.demand_accesses::1 41725 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 41725 # number of demand (read+write) accesses -system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses -system.iocache.overall_accesses::1 41725 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses -system.iocache.ReadReq_miss_rate::1 1 # miss rate for ReadReq accesses -system.iocache.WriteReq_miss_rate::1 1 # miss rate for WriteReq accesses -system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses -system.iocache.demand_miss_rate::1 1 # miss rate for demand accesses -system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses -system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses -system.iocache.overall_miss_rate::1 1 # miss rate for overall accesses -system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::0 inf # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::1 115398.832370 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::0 inf # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::1 137675.871342 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::0 inf # average overall miss latency -system.iocache.demand_avg_miss_latency::1 137583.506387 # average overall miss latency -system.iocache.demand_avg_miss_latency::total inf # average overall miss latency -system.iocache.overall_avg_miss_latency::0 inf # average overall miss latency -system.iocache.overall_avg_miss_latency::1 137583.506387 # average overall miss latency -system.iocache.overall_avg_miss_latency::total inf # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 64617964 # number of cycles access was blocked -system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 10476 # number of cycles access was blocked -system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6168.190531 # average number of cycles each access was blocked -system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed -system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks 41512 # number of writebacks -system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.iocache.overall_mshr_hits 0 # number of overall MSHR hits -system.iocache.ReadReq_mshr_misses 173 # number of ReadReq MSHR misses -system.iocache.WriteReq_mshr_misses 41552 # number of WriteReq MSHR misses -system.iocache.demand_mshr_misses 41725 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses 41725 # number of overall MSHR misses -system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.iocache.ReadReq_mshr_miss_latency 10967998 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency 3559854894 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency 3570822892 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency 3570822892 # number of overall MSHR miss cycles -system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_mshr_miss_rate::0 inf # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::1 1 # mshr miss rate for ReadReq accesses -system.iocache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.iocache.WriteReq_mshr_miss_rate::0 inf # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::1 1 # mshr miss rate for WriteReq accesses -system.iocache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.iocache.demand_mshr_miss_rate::0 inf # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::1 1 # mshr miss rate for demand accesses -system.iocache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.iocache.overall_mshr_miss_rate::0 inf # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::1 1 # mshr miss rate for overall accesses -system.iocache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency 63398.832370 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency 85672.287591 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency 85579.937496 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency 85579.937496 # average overall mshr miss latency -system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated -system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). -system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). -system.disk0.dma_write_full_pages 298 # Number of full page size DMA writes. -system.disk0.dma_write_bytes 2651136 # Number of bytes transfered via DMA writes. -system.disk0.dma_write_txs 395 # Number of DMA write transactions. -system.disk2.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.disk2.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.disk2.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes. -system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes. -system.disk2.dma_write_txs 1 # Number of DMA write transactions. -system.cpu.dtb.fetch_hits 0 # ITB hits -system.cpu.dtb.fetch_misses 0 # ITB misses -system.cpu.dtb.fetch_acv 0 # ITB acv -system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 12031830 # DTB read hits -system.cpu.dtb.read_misses 10329 # DTB read misses -system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_accesses 728887 # DTB read accesses -system.cpu.dtb.write_hits 6468534 # DTB write hits -system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_accesses 292164 # DTB write accesses -system.cpu.dtb.data_hits 18500364 # DTB hits -system.cpu.dtb.data_misses 11471 # DTB misses -system.cpu.dtb.data_acv 367 # DTB access violations -system.cpu.dtb.data_accesses 1021051 # DTB accesses -system.cpu.itb.fetch_hits 773687 # ITB hits -system.cpu.itb.fetch_misses 9100 # ITB misses -system.cpu.itb.fetch_acv 713 # ITB acv -system.cpu.itb.fetch_accesses 782787 # ITB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_acv 0 # DTB read access violations -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_acv 0 # DTB write access violations -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.data_hits 0 # DTB hits -system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.data_acv 0 # DTB access violations -system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3798914951 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.contextSwitches 6446 # Number of context switches -system.cpu.threadCycles 133331613 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 2296368 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 3687762143 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 111152808 # Number of cycles cpu stages are processed. -system.cpu.activity 2.925909 # Percentage of cycles cpu is active -system.cpu.comLoads 12027889 # Number of Load instructions committed -system.cpu.comStores 6376597 # Number of Store instructions committed -system.cpu.comBranches 15426722 # Number of Branches instructions committed -system.cpu.comNops 6123598 # Number of Nop instructions committed -system.cpu.comNonSpec 20710 # Number of Non-Speculative instructions committed -system.cpu.comInts 39260671 # Number of Integer instructions committed -system.cpu.comFloats 29243 # Number of Floating Point instructions committed -system.cpu.committedInsts 79507003 # Number of Instructions Simulated (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 79507003 # Number of Instructions Simulated (Total) -system.cpu.cpi 47.780885 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi no_value # CPI: Total SMT-CPI -system.cpu.cpi_total 47.780885 # CPI: Total CPI of All Threads -system.cpu.ipc 0.020929 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.ipc_total 0.020929 # IPC: Total IPC of All Threads -system.cpu.branch_predictor.lookups 17886857 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 15450279 # Number of conditional branches predicted -system.cpu.branch_predictor.condIncorrect 12067312 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 16082928 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 11760845 # Number of BTB hits -system.cpu.branch_predictor.usedRAS 748072 # Number of times the RAS was used to get a target. -system.cpu.branch_predictor.RASInCorrect 698 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 73.126268 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 12717384 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 5169473 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 66085429 # Number of Reads from Int. Register File -system.cpu.regfile_manager.intRegFileWrites 51239825 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 117325254 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 156392 # Number of Reads from FP Register File -system.cpu.regfile_manager.floatRegFileWrites 166486 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 322878 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 23151020 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 18525347 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 11562750 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 483435 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 12046185 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 3381472 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 78.081753 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 55021479 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 60941 # Number of Multipy Operations Executed -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.stage0.idleCycles 3695693335 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 103221616 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 2.717134 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 3723812456 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 75102495 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 1.976946 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 3732347710 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 66567241 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 1.752270 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 3782991821 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 15923130 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 0.419149 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 3738659661 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 60255290 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 1.586118 # Percentage of cycles stage was utilized (processing insts). -system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.tsunami.ethernet.coalescedSwi no_value # average number of Swi's coalesced into each post -system.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR -system.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedRxIdle no_value # average number of RxIdle's coalesced into each post -system.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedRxOk no_value # average number of RxOk's coalesced into each post -system.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedRxDesc no_value # average number of RxDesc's coalesced into each post -system.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.tsunami.ethernet.coalescedTxOk no_value # average number of TxOk's coalesced into each post -system.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.tsunami.ethernet.coalescedTxIdle no_value # average number of TxIdle's coalesced into each post -system.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.tsunami.ethernet.coalescedTxDesc no_value # average number of TxDesc's coalesced into each post -system.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.tsunami.ethernet.coalescedRxOrn no_value # average number of RxOrn's coalesced into each post -system.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.tsunami.ethernet.coalescedTotal no_value # average number of interrupts coalesced into each post -system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU -system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 976859 # number of replacements -system.cpu.icache.tagsinuse 509.192354 # Cycle average of tags in use -system.cpu.icache.total_refs 14112403 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 977370 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 14.439161 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 48225021000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::0 509.192354 # Average occupied blocks per context -system.cpu.icache.occ_percent::0 0.994516 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::0 14112405 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 14112405 # number of ReadReq hits -system.cpu.icache.demand_hits::0 14112405 # number of demand (read+write) hits -system.cpu.icache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 14112405 # number of demand (read+write) hits -system.cpu.icache.overall_hits::0 14112405 # number of overall hits -system.cpu.icache.overall_hits::1 0 # number of overall hits -system.cpu.icache.overall_hits::total 14112405 # number of overall hits -system.cpu.icache.ReadReq_misses::0 1171582 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1171582 # number of ReadReq misses -system.cpu.icache.demand_misses::0 1171582 # number of demand (read+write) misses -system.cpu.icache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1171582 # number of demand (read+write) misses -system.cpu.icache.overall_misses::0 1171582 # number of overall misses -system.cpu.icache.overall_misses::1 0 # number of overall misses -system.cpu.icache.overall_misses::total 1171582 # number of overall misses -system.cpu.icache.ReadReq_miss_latency 17108277000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency 17108277000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency 17108277000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::0 15283987 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 15283987 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::0 15283987 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 15283987 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::0 15283987 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 15283987 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::0 0.076654 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::0 0.076654 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::0 0.076654 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::0 14602.714108 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::0 14602.714108 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::0 14602.714108 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 29000 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 209500 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 10 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 12 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 2900 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 17458.333333 # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks 151 # number of writebacks -system.cpu.icache.ReadReq_mshr_hits 194034 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits 194034 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits 194034 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses 977548 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses 977548 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses 977548 # number of overall MSHR misses -system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency 11589669500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency 11589669500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency 11589669500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::0 0.063959 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::0 0.063959 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::0 0.063959 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency 11855.857206 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 11855.857206 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 11855.857206 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1388966 # number of replacements -system.cpu.dcache.tagsinuse 511.992872 # Cycle average of tags in use -system.cpu.dcache.total_refs 15595787 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1389478 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 11.224206 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 41598000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::0 511.992872 # Average occupied blocks per context -system.cpu.dcache.occ_percent::0 0.999986 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::0 10619576 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 10619576 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::0 4593305 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 4593305 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::0 183295 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 183295 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::0 199575 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 199575 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::0 15212881 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 15212881 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::0 15212881 # number of overall hits -system.cpu.dcache.overall_hits::1 0 # number of overall hits -system.cpu.dcache.overall_hits::total 15212881 # number of overall hits -system.cpu.dcache.ReadReq_misses::0 1200515 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1200515 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::0 1568476 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 1568476 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::0 17334 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 17334 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::0 2768991 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 2768991 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::0 2768991 # number of overall misses -system.cpu.dcache.overall_misses::1 0 # number of overall misses -system.cpu.dcache.overall_misses::total 2768991 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency 29846929000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency 52147271000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency 254755500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency 81994200000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency 81994200000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::0 11820091 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 11820091 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::0 6161781 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 6161781 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::0 200629 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 200629 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::0 199575 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 199575 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::0 17981872 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 17981872 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::0 17981872 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 17981872 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::0 0.101566 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::0 0.254549 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::0 0.086398 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::0 0.153988 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::0 0.153988 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::0 24861.770990 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::0 33247.095270 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14696.867428 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::0 29611.580536 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::0 29611.580536 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 22647500 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 4244310000 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2708 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 136112 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 8363.183161 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 31182.482074 # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks 825388 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits 132590 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits 1264137 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits 102 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits 1396727 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits 1396727 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses 1067925 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses 304339 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses 17232 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses 1372264 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses 1372264 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency 24081352000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency 8438501500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency 195926000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency 32519853500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency 32519853500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency 906226000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1239305500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency 2145531500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.090348 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.049391 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.085890 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::0 0.076314 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::0 0.076314 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22549.665941 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27727.309021 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11369.893222 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 23697.957172 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 23697.957172 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated -system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 6445 # number of quiesce instructions executed -system.cpu.kern.inst.hwrei 212089 # number of hwrei instructions executed -system.cpu.kern.ipl_count::0 75017 40.93% 40.93% # number of times we switched to this ipl -system.cpu.kern.ipl_count::21 240 0.13% 41.06% # number of times we switched to this ipl -system.cpu.kern.ipl_count::22 1920 1.05% 42.10% # number of times we switched to this ipl -system.cpu.kern.ipl_count::31 106125 57.90% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_count::total 183302 # number of times we switched to this ipl -system.cpu.kern.ipl_good::0 73650 49.28% 49.28% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::21 240 0.16% 49.44% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::22 1920 1.28% 50.72% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::31 73650 49.28% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good::total 149460 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1857236384500 97.79% 97.79% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::21 103259500 0.01% 97.80% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 182902000 0.01% 97.81% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 41671857000 2.19% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1899194403000 # number of cycles we spent at this ipl -system.cpu.kern.ipl_used::0 0.981777 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used::31 0.693993 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.syscall::2 8 2.45% 2.45% # number of syscalls executed -system.cpu.kern.syscall::3 30 9.20% 11.66% # number of syscalls executed -system.cpu.kern.syscall::4 4 1.23% 12.88% # number of syscalls executed -system.cpu.kern.syscall::6 42 12.88% 25.77% # number of syscalls executed -system.cpu.kern.syscall::12 1 0.31% 26.07% # number of syscalls executed -system.cpu.kern.syscall::15 1 0.31% 26.38% # number of syscalls executed -system.cpu.kern.syscall::17 15 4.60% 30.98% # number of syscalls executed -system.cpu.kern.syscall::19 10 3.07% 34.05% # number of syscalls executed -system.cpu.kern.syscall::20 6 1.84% 35.89% # number of syscalls executed -system.cpu.kern.syscall::23 4 1.23% 37.12% # number of syscalls executed -system.cpu.kern.syscall::24 6 1.84% 38.96% # number of syscalls executed -system.cpu.kern.syscall::33 11 3.37% 42.33% # number of syscalls executed -system.cpu.kern.syscall::41 2 0.61% 42.94% # number of syscalls executed -system.cpu.kern.syscall::45 54 16.56% 59.51% # number of syscalls executed -system.cpu.kern.syscall::47 6 1.84% 61.35% # number of syscalls executed -system.cpu.kern.syscall::48 10 3.07% 64.42% # number of syscalls executed -system.cpu.kern.syscall::54 10 3.07% 67.48% # number of syscalls executed -system.cpu.kern.syscall::58 1 0.31% 67.79% # number of syscalls executed -system.cpu.kern.syscall::59 7 2.15% 69.94% # number of syscalls executed -system.cpu.kern.syscall::71 54 16.56% 86.50% # number of syscalls executed -system.cpu.kern.syscall::73 3 0.92% 87.42% # number of syscalls executed -system.cpu.kern.syscall::74 16 4.91% 92.33% # number of syscalls executed -system.cpu.kern.syscall::87 1 0.31% 92.64% # number of syscalls executed -system.cpu.kern.syscall::90 3 0.92% 93.56% # number of syscalls executed -system.cpu.kern.syscall::92 9 2.76% 96.32% # number of syscalls executed -system.cpu.kern.syscall::97 2 0.61% 96.93% # number of syscalls executed -system.cpu.kern.syscall::98 2 0.61% 97.55% # number of syscalls executed -system.cpu.kern.syscall::132 4 1.23% 98.77% # number of syscalls executed -system.cpu.kern.syscall::144 2 0.61% 99.39% # number of syscalls executed -system.cpu.kern.syscall::147 2 0.61% 100.00% # number of syscalls executed -system.cpu.kern.syscall::total 326 # number of syscalls executed -system.cpu.kern.callpal::cserve 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrmces 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrfen 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal::swpctx 4176 2.16% 2.17% # number of callpals executed -system.cpu.kern.callpal::tbi 54 0.03% 2.19% # number of callpals executed -system.cpu.kern.callpal::wrent 7 0.00% 2.20% # number of callpals executed -system.cpu.kern.callpal::swpipl 175887 91.18% 93.38% # number of callpals executed -system.cpu.kern.callpal::rdps 6802 3.53% 96.91% # number of callpals executed -system.cpu.kern.callpal::wrkgp 1 0.00% 96.91% # number of callpals executed -system.cpu.kern.callpal::wrusp 7 0.00% 96.91% # number of callpals executed -system.cpu.kern.callpal::rdusp 9 0.00% 96.91% # number of callpals executed -system.cpu.kern.callpal::whami 2 0.00% 96.92% # number of callpals executed -system.cpu.kern.callpal::rti 5254 2.72% 99.64% # number of callpals executed -system.cpu.kern.callpal::callsys 515 0.27% 99.91% # number of callpals executed -system.cpu.kern.callpal::imb 181 0.09% 100.00% # number of callpals executed -system.cpu.kern.callpal::total 192899 # number of callpals executed -system.cpu.kern.mode_switch::kernel 8095 # number of protection mode switches -system.cpu.kern.mode_switch::user 1737 # number of protection mode switches -system.cpu.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu.kern.mode_good::kernel 1736 -system.cpu.kern.mode_good::user 1737 -system.cpu.kern.mode_good::idle 0 -system.cpu.kern.mode_switch_good::kernel 0.214453 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::idle no_value # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good::total no_value # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 1895952878500 99.83% 99.83% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 3241521500 0.17% 100.00% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4177 # number of times the context was actually changed - ----------- End Simulation Statistics ---------- diff --git a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/system.terminal b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/system.terminal deleted file mode 100644 index d200f0a04..000000000 --- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-inorder/system.terminal +++ /dev/null @@ -1,108 +0,0 @@ -M5 console: m5AlphaAccess @ 0xFFFFFD0200000000 -
Got Configuration 623 -
memsize 8000000 pages 4000 -
First free page after ROM 0xFFFFFC0000018000 -
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000 -
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1 -
CPU Clock at 2000 MHz IntrClockFrequency=1024 -
Booting with 1 processor(s) -
KSP: 0x20043FE8 PTBR 0x20 -
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510 -
Memory cluster 0 [0 - 392] -
Memory cluster 1 [392 - 15992] -
Initalizing mdt_bitmap addr 0xFFFFFC0000038000 mem_pages 4000 -
ConsoleDispatch at virt 10000658 phys 18658 val FFFFFC00000100A8 -
unix_boot_mem ends at FFFFFC0000076000 -
k_argc = 0 -
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067) -
CallbackFixup 0 18000, t7=FFFFFC000070C000 -
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006 -
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM -
Major Options: SMP LEGACY_START VERBOSE_MCHECK -
Command line: root=/dev/hda1 console=ttyS0 -
memcluster 0, usage 1, start 0, end 392 -
memcluster 1, usage 0, start 392, end 16384 -
freeing pages 1069:16384 -
reserving pages 1069:1070 -
4096K Bcache detected; load hit latency 34 cycles, load miss latency 118 cycles -
SMP: 1 CPUs probed -- cpu_present_mask = 1 -
Built 1 zonelists -
Kernel command line: root=/dev/hda1 console=ttyS0 -
PID hash table entries: 1024 (order: 10, 32768 bytes) -
Using epoch = 1900 -
Console: colour dummy device 80x25 -
Dentry cache hash table entries: 32768 (order: 5, 262144 bytes) -
Inode-cache hash table entries: 16384 (order: 4, 131072 bytes) -
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init) -
Mount-cache hash table entries: 512 -
SMP mode deactivated. -
Brought up 1 CPUs -
SMP: Total of 1 processors activated (4000.49 BogoMIPS). -
NET: Registered protocol family 16 -
EISA bus registered -
pci: enabling save/restore of SRM state -
SCSI subsystem initialized -
srm_env: version 0.0.5 loaded successfully -
Installing knfsd (copyright (C) 1996 okir@monad.swb.de). -
Initializing Cryptographic API -
rtc: Standard PC (1900) epoch (1900) detected -
Real Time Clock Driver v1.12 -
Serial: 8250/16550 driver $Revision: 1.90 $ 1 ports, IRQ sharing disabled -
ttyS0 at I/O 0x3f8 (irq = 4) is a 8250 -
io scheduler noop registered -
io scheduler anticipatory registered -
io scheduler deadline registered -
io scheduler cfq registered -
loop: loaded (max 8 devices) -
nbd: registered device at major 43 -
ns83820.c: National Semiconductor DP83820 10/100/1000 driver. -
PCI: Setting latency timer of device 0000:00:01.0 to 64 -
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000 -
eth0: enabling optical transceiver -
eth0: using 64 bit addressing. -
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg -
tun: Universal TUN/TAP device driver, 1.6 -
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com> -
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2 -
ide: Assuming 33MHz system bus speed for PIO modes; override with idebus=xx -
PIIX4: IDE controller at PCI slot 0000:00:00.0 -
PIIX4: chipset revision 0 -
PIIX4: 100% native mode on irq 31 -
PCI: Setting latency timer of device 0000:00:00.0 to 64 -
ide0: BM-DMA at 0x8400-0x8407, BIOS settings: hda:DMA, hdb:DMA -
ide1: BM-DMA at 0x8408-0x840f, BIOS settings: hdc:DMA, hdd:DMA -
hda: M5 IDE Disk, ATA DISK drive -
hdb: M5 IDE Disk, ATA DISK drive -
ide0 at 0x8410-0x8417,0x8422 on irq 31 -
hda: max request size: 128KiB -
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33) -
hda: cache flushes not supported -
hda: hda1 -
hdb: max request size: 128KiB -
hdb: 4177920 sectors (2139 MB), CHS=4144/16/63, UDMA(33) -
hdb: cache flushes not supported -
hdb: unknown partition table -
mice: PS/2 mouse device common for all mice -
NET: Registered protocol family 2 -
IP route cache hash table entries: 4096 (order: 2, 32768 bytes) -
TCP established hash table entries: 16384 (order: 5, 262144 bytes) -
TCP bind hash table entries: 16384 (order: 5, 262144 bytes) -
TCP: Hash tables configured (established 16384 bind 16384) -
TCP reno registered -
ip_conntrack version 2.1 (512 buckets, 4096 max) - 296 bytes per conntrack -
ip_tables: (C) 2000-2002 Netfilter core team -
arp_tables: (C) 2002 David S. Miller -
TCP bic registered -
Initializing IPsec netlink socket -
NET: Registered protocol family 1 -
NET: Registered protocol family 17 -
NET: Registered protocol family 15 -
Bridge firewalling registered -
802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com> -
All bugs added by David S. Miller <davem@redhat.com> -
VFS: Mounted root (ext2 filesystem) readonly. -
Freeing unused kernel memory: 224k freed -
init started: BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary
-mounting filesystems...
-EXT2-fs warning: checktime reached, running e2fsck is recommended -
loading script...
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