summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorIru Cai <mytbk920423@gmail.com>2019-05-11 21:41:14 +0800
committerIru Cai <mytbk920423@gmail.com>2019-05-11 21:41:14 +0800
commit2b62fec3590024a7ce82ef5d4647397d37ed37eb (patch)
tree8f4a6d9bed9d5006f3d5d9ac94b1b6b5fa8d5578
parent3b26d5f86c9a427e6ab9b9fa688b76ab2034a0d2 (diff)
downloadgem5-2b62fec3590024a7ce82ef5d4647397d37ed37eb.tar.xz
try not expose if L1 hitis-ift-cachehit
-rw-r--r--src/cpu/base_dyn_inst.hh3
-rw-r--r--src/cpu/o3/lsq_unit.hh1
-rw-r--r--src/cpu/o3/lsq_unit_impl.hh28
-rw-r--r--src/mem/protocol/MESI_Two_Level-L1cache.sm1
4 files changed, 18 insertions, 15 deletions
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 6301864b7..8681d3d91 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -331,9 +331,6 @@ class BaseDynInst : public ExecContext, public RefCounted
bool needPostFetch() const { return instFlags[NeedPostFetch]; }
void needPostFetch(bool f) { instFlags[NeedPostFetch] = f; }
- bool needDeletePostReq() const { return instFlags[NeedDeletePostReq]; }
- void needDeletePostReq(bool f) { instFlags[NeedDeletePostReq] = f; }
-
bool fenceDelay() const { return instFlags[ReadyToExpose]; }
void fenceDelay(bool f) { instFlags[ReadyToExpose] = f; }
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index fbe5248f7..1c8b98f2e 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -1045,7 +1045,6 @@ LSQUnit<Impl>::read(const RequestPtr &req,
" req=%#x\n",
load_inst->seqNum, load_inst->postReq->getVaddr());
}
- load_inst->needDeletePostReq(true);
} else {
load_inst->setExposeCompleted();
load_inst->needPostFetch(false);
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index 164a768bb..56870b5a3 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -1197,6 +1197,23 @@ LSQUnit<Impl>::exposeLoads()
load_inst->postSreqHigh->getVaddr());
}
+ bool split = false;
+ if (TheISA::HasUnalignedMemAcc && sreqLow) {
+ split = true;
+ } else {
+ assert(req);
+ }
+
+ if (load_inst->isL1HitLow() && (!split || load_inst->isL1HitHigh()) ) {
+ load_inst->setExposeCompleted();
+ load_inst->setExposeSent();
+ --loadsToVLD;
+ incrLdIdx(loadVLDIdx);
+ iewStage->instToCommit(load_inst);
+ iewStage->activityThisCycle();
+ continue;
+ }
+
PacketPtr data_pkt = NULL;
PacketPtr snd_data_pkt = NULL;
@@ -1206,13 +1223,6 @@ LSQUnit<Impl>::exposeLoads()
state->inst = load_inst;
state->noWB = true;
- bool split = false;
- if (TheISA::HasUnalignedMemAcc && sreqLow) {
- split = true;
- } else {
- assert(req);
- }
-
bool onlyExpose = false;
if (!split) {
if (load_inst->needExposeOnly() || load_inst->isL1HitLow()){
@@ -1325,10 +1335,6 @@ LSQUnit<Impl>::exposeLoads()
++lsqCacheBlocked;
break;
} else {
- // Here is to fix memory leakage
- // it is ugly, but we have to do it now.
- load_inst->needDeletePostReq(false);
-
// if all the packets we sent out is expose,
// we assume the expose is alreay completed
if (onlyExpose) {
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index 846af7da5..f5feb7e23 100644
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -1323,6 +1323,7 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
transition({S,E,M}, SpecLoad) {
h_spec_load_hit;
+ uu_profileDataHit;
k_popMandatoryQueue;
}