summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorPaul Rosenfeld <dramninjas@gmail.com>2014-03-12 07:03:22 -0500
committerPaul Rosenfeld <dramninjas@gmail.com>2014-03-12 07:03:22 -0500
commit32bf74cb8ee4c9293636041c05d93fbfd01087da (patch)
treea8f219af38c3986aee56ffadae8ecdb0dd618cf9
parent62fe81e9c1ab09f1b401231f58d9c34008c7b558 (diff)
downloadgem5-32bf74cb8ee4c9293636041c05d93fbfd01087da.tar.xz
alpha: Small removal of dead comments/code from alpha ISA
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
-rw-r--r--src/arch/alpha/isa/mem.isa13
-rw-r--r--src/cpu/o3/dyn_inst.hh7
2 files changed, 0 insertions, 20 deletions
diff --git a/src/arch/alpha/isa/mem.isa b/src/arch/alpha/isa/mem.isa
index f286be91c..ef140f515 100644
--- a/src/arch/alpha/isa/mem.isa
+++ b/src/arch/alpha/isa/mem.isa
@@ -465,27 +465,14 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags)
- # Some CPU models execute the memory operation as an atomic unit,
- # while others want to separate them into an effective address
- # computation and a memory access operation. As a result, we need
- # to generate three StaticInst objects. Note that the latter two
- # are nested inside the larger "atomic" one.
-
- # Generate InstObjParams for each of the three objects. Note that
- # they differ only in the set of code objects contained (which in
- # turn affects the object's overall operand list).
iop = InstObjParams(name, Name, base_class,
{ 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
inst_flags)
- memacc_iop = InstObjParams(name, Name, base_class,
- { 'memacc_code':memacc_code, 'postacc_code':postacc_code },
- inst_flags)
if mem_flags:
mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
iop.constructor += s
- memacc_iop.constructor += s
# select templates
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 5477f46d6..76bd8b291 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -54,13 +54,6 @@
class Packet;
-/**
- * Mostly implementation & ISA specific AlphaDynInst. As with most
- * other classes in the new CPU model, it is templated on the Impl to
- * allow for passing in of all types, such as the CPU type and the ISA
- * type. The AlphaDynInst serves as the primary interface to the CPU
- * for instructions that are executing.
- */
template <class Impl>
class BaseO3DynInst : public BaseDynInst<Impl>
{