Fix the RTC code so it is in the cchip, only interrupt processors that

are present

dev/tsunami_cchip.cc:
    Only need to interrupt processors that are there
    Move RTC interrupt code into a function
dev/tsunami_cchip.hh:
    Make a RTC interrupt function, move variables out of public scope
dev/tsunami_io.cc:
    Make a call to the RTC interrupt routine instead

--HG--
extra : convert_revision : 88113664d0e54a7dddc00ec11ff9b9d088232b31

3 files changed, 31 insertions, 18 deletions

diff --git a/dev/tsunami_cchip.cc b/dev/tsunami_cchip.cc
index abf2b1da4..ba49c361b 100644
--- a/dev/tsunami_cchip.cc
+++ b/dev/tsunami_cchip.cc
@@ -137,7 +137,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
     Addr daddr = (req->paddr - (addr & PA_IMPL_MASK)) >> 6;
 
     bool supportedWrite = false;
-
+    uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
 
     switch (req->size) {
 
@@ -155,11 +155,11 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
                 if ((itintr = (*(uint64_t*) data) & (0xf<<4))) {
                     //Clear the bits in ITINTR
                     misc &= ~(itintr);
-                    for (int i=0; i < 4; i++) {
+                    for (int i=0; i < size; i++) {
                         if ((itintr & (1 << (i+4))) && RTCInterrupting[i]) {
                             tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ2, 0);
                             RTCInterrupting[i] = false;
-                            DPRINTF(Tsunami, "clearing rtc interrupt\n");
+                            DPRINTF(Tsunami, "clearing rtc interrupt to cpu=%d\n", i);
                         }
                     }
                     supportedWrite = true;
@@ -169,7 +169,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
                 if ((ipreq = (*(uint64_t*) data) & (0xf << 12))) {
                     //Set the bits in IPINTR
                     misc |= (ipreq >> 4);
-                    for (int i=0; i < 4; i++) {
+                    for (int i=0; i < size; i++) {
                         if ((ipreq & (1 << (i + 12)))) {
                             if (!ipiInterrupting[i])
                                 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ3, 0);
@@ -185,7 +185,7 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
                 if ((ipintr = (*(uint64_t*) data) & (0xf << 8))) {
                     //Clear the bits in IPINTR
                     misc &= ~(ipintr);
-                    for (int i=0; i < 4; i++) {
+                    for (int i=0; i < size; i++) {
                         if ((ipintr & (1 << (i + 8))) && ipiInterrupting[i]) {
                             if (!(--ipiInterrupting[i]))
                                 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ3, 0);
@@ -289,11 +289,28 @@ TsunamiCChip::write(MemReqPtr &req, const uint8_t *data)
 }
 
 void
+TsunamiCChip::postRTC()
+{
+    int size = tsunami->intrctrl->cpu->system->execContexts.size();
+
+    for (int i = 0; i < size; i++) {
+        if (!RTCInterrupting[i]) {
+            misc |= 16 << i;
+            RTCInterrupting[i] = true;
+            tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
+            DPRINTF(Tsunami, "Posting RTC interrupt to cpu=%d", i);
+        }
+    }
+
+}
+
+void
 TsunamiCChip::postDRIR(uint32_t interrupt)
 {
     uint64_t bitvector = (uint64_t)0x1 << interrupt;
     drir |= bitvector;
-    for(int i=0; i < Tsunami::Max_CPUs; i++) {
+    uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
+    for(int i=0; i < size; i++) {
         dir[i] = dim[i] & drir;
         if (dim[i] & bitvector) {
                 tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ1, interrupt);
@@ -307,10 +324,11 @@ void
 TsunamiCChip::clearDRIR(uint32_t interrupt)
 {
     uint64_t bitvector = (uint64_t)0x1 << interrupt;
+    uint64_t size = tsunami->intrctrl->cpu->system->execContexts.size();
     if (drir & bitvector)
     {
         drir &= ~bitvector;
-        for(int i=0; i < Tsunami::Max_CPUs; i++) {
+        for(int i=0; i < size; i++) {
             if (dir[i] & bitvector) {
                 tsunami->intrctrl->clear(i, TheISA::INTLEVEL_IRQ1, interrupt);
                 DPRINTF(Tsunami, "clearing dir interrupt to cpu %d,"
diff --git a/dev/tsunami_cchip.hh b/dev/tsunami_cchip.hh
index a816e723e..adb05a572 100644
--- a/dev/tsunami_cchip.hh
+++ b/dev/tsunami_cchip.hh
@@ -71,7 +71,11 @@ class TsunamiCChip : public FunctionalMemory
      * that can occur.
      */
     uint64_t drir;
+
+    uint64_t misc;
+
     uint64_t ipiInterrupting[Tsunami::Max_CPUs];
+    bool RTCInterrupting[Tsunami::Max_CPUs];
 
   public:
     TsunamiCChip(const std::string &name, Tsunami *t, Addr a,
@@ -80,14 +84,12 @@ class TsunamiCChip : public FunctionalMemory
     virtual Fault read(MemReqPtr &req, uint8_t *data);
     virtual Fault write(MemReqPtr &req, const uint8_t *data);
 
+    void postRTC();
     void postDRIR(uint32_t interrupt);
     void clearDRIR(uint32_t interrupt);
 
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
-
-    uint64_t misc;
-    bool RTCInterrupting[Tsunami::Max_CPUs];
 };
 
 #endif // __TSUNAMI_CCHIP_HH__
diff --git a/dev/tsunami_io.cc b/dev/tsunami_io.cc
index 41acf1fae..d32291d0d 100644
--- a/dev/tsunami_io.cc
+++ b/dev/tsunami_io.cc
@@ -65,15 +65,8 @@ TsunamiIO::RTCEvent::process()
     DPRINTF(MC146818, "RTC Timer Interrupt\n");
     schedule(curTick + ticksPerSecond/RTC_RATE);
     //Actually interrupt the processor here
-    int size = tsunami->intrctrl->cpu->system->execContexts.size();
+    tsunami->cchip->postRTC();
 
-    for (int i = 0; i < size; i++) {
-        if (!tsunami->cchip->RTCInterrupting[i]) {
-            tsunami->cchip->misc |= 16 << i;
-            tsunami->cchip->RTCInterrupting[i] = true;
-            tsunami->intrctrl->post(i, TheISA::INTLEVEL_IRQ2, 0);
-        }
-    }
 }
 
 const char *