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| author | Javier Bueno <javier.bueno@metempsy.com> | 2019-04-02 23:29:42 +0200 |
|---|---|---|
| committer | Javier Bueno Hedo <javier.bueno@metempsy.com> | 2019-04-03 09:20:28 +0000 |
| commit | 5caa4517345d4833af44e510f78717ee7e0ad8d4 (patch) | |
| tree | 78a26c95e2516f30d9b18b0f5d1a7c6b36e3c98c | |
| parent | f662b8aaacba60632e69da11cf7fc0deba958604 (diff) | |
| download | gem5-5caa4517345d4833af44e510f78717ee7e0ad8d4.tar.xz | |
mem-cache: Fix PIF prefetcher compilation error with NULL ISA
Referencing BaseCPU is causing a compilation error when using the NULL ISA.
This patch changes the reference to a SimObject, which fixes the problem.
Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17731
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
| -rw-r--r-- | src/mem/cache/prefetch/Prefetcher.py | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py index 404a44240..aaa140887 100644 --- a/src/mem/cache/prefetch/Prefetcher.py +++ b/src/mem/cache/prefetch/Prefetcher.py @@ -43,7 +43,6 @@ from m5.SimObject import * from m5.params import * from m5.proxy import * -from m5.objects.BaseCPU import BaseCPU from m5.objects.ClockedObject import ClockedObject from m5.objects.IndexingPolicies import * from m5.objects.ReplacementPolicies import * @@ -481,6 +480,6 @@ class PIFPrefetcher(QueuedPrefetcher): "Replacement policy of the index") def listenFromProbeRetiredInstructions(self, simObj): - if not isinstance(simObj, BaseCPU): - raise TypeError("argument must be of BaseCPU type") + if not isinstance(simObj, SimObject): + raise TypeError("argument must be of SimObject type") self.addEvent(HWPProbeEventRetiredInsts(self, simObj,"RetiredInstsPC")) |