merge

--HG--
extra : convert_revision : 5866eaa4008c4fa5da7fbb443132b8326955f71d

68 files changed, 1968 insertions, 963 deletions

diff --git a/configs/common/Caches.py b/configs/common/Caches.py
index 43a1c6378..f1ea957b5 100644
--- a/configs/common/Caches.py
+++ b/configs/common/Caches.py
@@ -43,3 +43,10 @@ class L2Cache(BaseCache):
     mshrs = 20
     tgts_per_mshr = 12
 
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '10ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6bcdafb14..9778be3f1 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -53,7 +53,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
     self.readfile = mdesc.script()
     self.iobus = Bus(bus_id=0)
     self.membus = Bus(bus_id=1)
-    self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns')
+    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
     self.bridge.side_a = self.iobus.port
     self.bridge.side_b = self.membus.port
diff --git a/configs/common/Options.py b/configs/common/Options.py
index 4f2b317c0..225916840 100644
--- a/configs/common/Options.py
+++ b/configs/common/Options.py
@@ -32,6 +32,7 @@ parser.add_option("-t", "--timing", action="store_true")
 parser.add_option("-n", "--num_cpus", type="int", default=1)
 parser.add_option("--caches", action="store_true")
 parser.add_option("--l2cache", action="store_true")
+parser.add_option("--fastmem", action="store_true")
 
 # Run duration options
 parser.add_option("-m", "--maxtick", type="int")
diff --git a/configs/example/fs.py b/configs/example/fs.py
index e772a3ab1..3a57fe5b8 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -121,12 +121,20 @@ for i in xrange(np):
     if options.caches:
         test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
                                                 L1Cache(size = '64kB'))
-
+        test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+        test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+        test_sys.iocache = IOCache(mem_side_filter_ranges=[AddrRange(0, Addr.max)],
+                           cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)])
+        test_sys.iocache.cpu_side = test_sys.iobus.port
+        test_sys.iocache.mem_side = test_sys.membus.port
     if options.l2cache:
         test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
     else:
         test_sys.cpu[i].connectMemPorts(test_sys.membus)
 
+    if options.fastmem:
+        test_sys.cpu[i].physmem_port = test_sys.physmem.port
+
 if len(bm) == 2:
     if m5.build_env['TARGET_ISA'] == 'alpha':
         drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
@@ -134,6 +142,8 @@ if len(bm) == 2:
         drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
     drive_sys.cpu = DriveCPUClass(cpu_id=0)
     drive_sys.cpu.connectMemPorts(drive_sys.membus)
+    if options.fastmem:
+        drive_sys.cpu.physmem_port = drive_sys.physmem.port
     if options.kernel is not None:
         drive_sys.kernel = binary(options.kernel)
 
diff --git a/configs/example/se.py b/configs/example/se.py
index 20fe75a21..639bcd7c6 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -114,6 +114,9 @@ for i in xrange(np):
         system.cpu[i].connectMemPorts(system.membus)
     system.cpu[i].workload = process
 
+    if options.fastmem:
+        system.cpu[0].physmem_port = system.physmem.port
+
 root = Root(system = system)
 
 Simulation.run(options, root, system, FutureClass)
diff --git a/src/arch/alpha/tlb.cc b/src/arch/alpha/tlb.cc
index 214b2579f..f701c423d 100644
--- a/src/arch/alpha/tlb.cc
+++ b/src/arch/alpha/tlb.cc
@@ -64,6 +64,7 @@ TLB::TLB(const string &name, int s)
 {
     table = new PTE[size];
     memset(table, 0, sizeof(PTE[size]));
+    flushCache();
 }
 
 TLB::~TLB()
@@ -74,23 +75,39 @@ TLB::~TLB()
 
 // look up an entry in the TLB
 PTE *
-TLB::lookup(Addr vpn, uint8_t asn) const
+TLB::lookup(Addr vpn, uint8_t asn)
 {
     // assume not found...
     PTE *retval = NULL;
 
-    PageTable::const_iterator i = lookupTable.find(vpn);
-    if (i != lookupTable.end()) {
-        while (i->first == vpn) {
-            int index = i->second;
-            PTE *pte = &table[index];
-            assert(pte->valid);
-            if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
-                retval = pte;
-                break;
-            }
+    if (PTECache[0]) {
+        if (vpn == PTECache[0]->tag &&
+            (PTECache[0]->asma || PTECache[0]->asn == asn))
+            retval = PTECache[0];
+        else if (PTECache[1]) {
+            if (vpn == PTECache[1]->tag &&
+                (PTECache[1]->asma || PTECache[1]->asn == asn))
+                retval = PTECache[1];
+            else if (PTECache[2] && vpn == PTECache[2]->tag &&
+                     (PTECache[2]->asma || PTECache[2]->asn == asn))
+                retval = PTECache[2];
+        }
+    }
 
-            ++i;
+    if (retval == NULL) {
+        PageTable::const_iterator i = lookupTable.find(vpn);
+        if (i != lookupTable.end()) {
+            while (i->first == vpn) {
+                int index = i->second;
+                PTE *pte = &table[index];
+                assert(pte->valid);
+                if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
+                    retval = updateCache(pte);
+                    break;
+                }
+
+                ++i;
+            }
         }
     }
 
@@ -142,6 +159,7 @@ TLB::checkCacheability(RequestPtr &req)
 void
 TLB::insert(Addr addr, PTE &pte)
 {
+    flushCache();
     VAddr vaddr = addr;
     if (table[nlu].valid) {
         Addr oldvpn = table[nlu].tag;
@@ -178,6 +196,7 @@ TLB::flushAll()
 {
     DPRINTF(TLB, "flushAll\n");
     memset(table, 0, sizeof(PTE[size]));
+    flushCache();
     lookupTable.clear();
     nlu = 0;
 }
@@ -185,6 +204,7 @@ TLB::flushAll()
 void
 TLB::flushProcesses()
 {
+    flushCache();
     PageTable::iterator i = lookupTable.begin();
     PageTable::iterator end = lookupTable.end();
     while (i != end) {
@@ -208,6 +228,7 @@ TLB::flushProcesses()
 void
 TLB::flushAddr(Addr addr, uint8_t asn)
 {
+    flushCache();
     VAddr vaddr = addr;
 
     PageTable::iterator i = lookupTable.find(vaddr.vpn());
@@ -291,7 +312,7 @@ ITB::regStats()
 
 
 Fault
-ITB::translate(RequestPtr &req, ThreadContext *tc) const
+ITB::translate(RequestPtr &req, ThreadContext *tc)
 {
     //If this is a pal pc, then set PHYSICAL
     if(FULL_SYSTEM && PcPAL(req->getPC()))
@@ -453,7 +474,7 @@ DTB::regStats()
 }
 
 Fault
-DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) const
+DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
 {
     Addr pc = tc->readPC();
 
diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index ea5ba5539..a4255f3c5 100644
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -61,7 +61,7 @@ namespace AlphaISA
         int nlu;			// not last used entry (for replacement)
 
         void nextnlu() { if (++nlu >= size) nlu = 0; }
-        PTE *lookup(Addr vpn, uint8_t asn) const;
+        PTE *lookup(Addr vpn, uint8_t asn);
 
       public:
         TLB(const std::string &name, int size);
@@ -88,6 +88,16 @@ namespace AlphaISA
         // Checkpointing
         virtual void serialize(std::ostream &os);
         virtual void unserialize(Checkpoint *cp, const std::string &section);
+
+        // Most recently used page table entries
+        PTE *PTECache[3];
+        inline void flushCache() { memset(PTECache, 0, 3 * sizeof(PTE*)); }
+        inline PTE* updateCache(PTE *pte) {
+            PTECache[2] = PTECache[1];
+            PTECache[1] = PTECache[0];
+            PTECache[0] = pte;
+            return pte;
+        }
     };
 
     class ITB : public TLB
@@ -102,7 +112,7 @@ namespace AlphaISA
         ITB(const std::string &name, int size);
         virtual void regStats();
 
-        Fault translate(RequestPtr &req, ThreadContext *tc) const;
+        Fault translate(RequestPtr &req, ThreadContext *tc);
     };
 
     class DTB : public TLB
@@ -125,7 +135,7 @@ namespace AlphaISA
         DTB(const std::string &name, int size);
         virtual void regStats();
 
-        Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const;
+        Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
     };
 }
 
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py
index 64a120c4c..fb398d152 100755
--- a/src/arch/isa_parser.py
+++ b/src/arch/isa_parser.py
@@ -1464,6 +1464,25 @@ class MemOperand(Operand):
     def makeAccSize(self):
         return self.size
 
+class UPCOperand(Operand):
+    def makeConstructor(self):
+        return ''
+
+    def makeRead(self):
+        return '%s = xc->readMicroPC();\n' % self.base_name
+
+    def makeWrite(self):
+        return 'xc->setMicroPC(%s);\n' % self.base_name
+
+class NUPCOperand(Operand):
+    def makeConstructor(self):
+        return ''
+
+    def makeRead(self):
+        return '%s = xc->readNextMicroPC();\n' % self.base_name
+
+    def makeWrite(self):
+        return 'xc->setNextMicroPC(%s);\n' % self.base_name
 
 class NPCOperand(Operand):
     def makeConstructor(self):
diff --git a/src/arch/x86/insts/microregop.cc b/src/arch/x86/insts/microregop.cc
index e67a82d4f..b6a30d6a7 100644
--- a/src/arch/x86/insts/microregop.cc
+++ b/src/arch/x86/insts/microregop.cc
@@ -69,19 +69,23 @@ namespace X86ISA
         DPRINTF(Sparc, "flagMask = %#x\n", flagMask);
         uint64_t flags = oldFlags & ~flagMask;
         if(flagMask & CFBit)
+        {
             if(findCarry(dataSize*8, _dest, _src1, _src2))
                 flags |= CFBit;
             if(subtract)
                 flags ^= CFBit;
+        }
         if(flagMask & PFBit && findParity(dataSize*8, _dest))
             flags |= PFBit;
         if(flagMask & ECFBit && findCarry(dataSize*8, _dest, _src1, _src2))
             flags |= ECFBit;
         if(flagMask & AFBit)
+        {
             if(findCarry(4, _dest, _src1, _src2))
                 flags |= AFBit;
             if(subtract)
                 flags ^= AFBit;
+        }
         if(flagMask & EZFBit && findZero(dataSize*8, _dest))
             flags |= EZFBit;
         if(flagMask & ZFBit && findZero(dataSize*8, _dest))
@@ -112,8 +116,9 @@ namespace X86ISA
             panic("This condition is not implemented!");
           case ConditionTests::MSTRC:
             panic("This condition is not implemented!");
-          case ConditionTests::STRZnZF:
-            panic("This condition is not implemented!");
+          case ConditionTests::STRZnEZF:
+            return !ccflags.EZF & ccflags.ZF;
+                //And no interrupts or debug traps are waiting
           case ConditionTests::OF:
             return ccflags.OF;
           case ConditionTests::CF:
@@ -144,8 +149,9 @@ namespace X86ISA
             panic("This condition is not implemented!");
           case ConditionTests::NotMSTRC:
             panic("This condition is not implemented!");
-          case ConditionTests::NotSTRZnZF:
-            panic("This condition is not implemented!");
+          case ConditionTests::STRnZnEZF:
+            return !ccflags.EZF & !ccflags.ZF;
+                //And no interrupts or debug traps are waiting
           case ConditionTests::NotOF:
             return !ccflags.OF;
           case ConditionTests::NotCF:
diff --git a/src/arch/x86/insts/microregop.hh b/src/arch/x86/insts/microregop.hh
index f465ac651..f6bebb763 100644
--- a/src/arch/x86/insts/microregop.hh
+++ b/src/arch/x86/insts/microregop.hh
@@ -73,7 +73,7 @@ namespace X86ISA
             MSTRZ,
             STRZ,
             MSTRC,
-            STRZnZF,
+            STRZnEZF,
             OF,
             CF,
             ZF,
@@ -91,7 +91,7 @@ namespace X86ISA
             NotMSTRZ,
             NotSTRZ,
             NotMSTRC,
-            NotSTRZnZF,
+            STRnZnEZF,
             NotOF,
             NotCF,
             NotZF,
diff --git a/src/arch/x86/isa/decoder/one_byte_opcodes.isa b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
index cce07d6fe..ee7fbc683 100644
--- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa
@@ -342,8 +342,8 @@
             0x3: stos_Yv_rAX();
             0x4: lods_Al_Xb();
             0x5: lods_rAX_Xv();
-            0x6: scas_Yb_Al();
-            0x7: scas_Yv_rAX();
+            0x6: StringInst::SCAS(Yb);
+            0x7: StringInst::SCAS(Yv);
         }
         format Inst {
             0x16: MOV(Bb,Ib);
diff --git a/src/arch/x86/isa/formats/formats.isa b/src/arch/x86/isa/formats/formats.isa
index 1e7bb4a74..6906413c0 100644
--- a/src/arch/x86/isa/formats/formats.isa
+++ b/src/arch/x86/isa/formats/formats.isa
@@ -99,6 +99,10 @@
 //thing on a variety of inputs
 ##include "multi.isa"
 
+//Include a format which implements an extra layer of decoding to handle the
+//repe and repne prefixes
+##include "string.isa"
+
 //Include a format which makes instructions who's sole purpose is to generate
 //a syscall.
 ##include "syscall.isa"
diff --git a/src/arch/x86/isa/formats/string.isa b/src/arch/x86/isa/formats/string.isa
new file mode 100644
index 000000000..cd182ff62
--- /dev/null
+++ b/src/arch/x86/isa/formats/string.isa
@@ -0,0 +1,88 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2007 The Hewlett-Packard Development Company
+// All rights reserved.
+//
+// Redistribution and use of this software in source and binary forms,
+// with or without modification, are permitted provided that the
+// following conditions are met:
+//
+// The software must be used only for Non-Commercial Use which means any
+// use which is NOT directed to receiving any direct monetary
+// compensation for, or commercial advantage from such use.  Illustrative
+// examples of non-commercial use are academic research, personal study,
+// teaching, education and corporate research & development.
+// Illustrative examples of commercial use are distributing products for
+// commercial advantage and providing services using the software for
+// commercial advantage.
+//
+// If you wish to use this software or functionality therein that may be
+// covered by patents for commercial use, please contact:
+//     Director of Intellectual Property Licensing
+//     Office of Strategy and Technology
+//     Hewlett-Packard Company
+//     1501 Page Mill Road
+//     Palo Alto, California  94304
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.  Redistributions
+// in binary form must reproduce the above copyright notice, this list of
+// conditions and the following disclaimer in the documentation and/or
+// other materials provided with the distribution.  Neither the name of
+// the COPYRIGHT HOLDER(s), HEWLETT-PACKARD COMPANY, nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.  No right of
+// sublicense is granted herewith.  Derivatives of the software and
+// output created using the software may be prepared, but only for
+// Non-Commercial Uses.  Derivatives of the software may be shared with
+// others provided: (i) the others agree to abide by the list of
+// conditions herein which includes the Non-Commercial Use restrictions;
+// and (ii) such Derivatives of the software include the above copyright
+// notice to acknowledge the contribution from this software where
+// applicable, this list of conditions and the disclaimer below.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+//////////////////////////////////////////////////////////////////////////
+//
+// String Instructions
+//
+//////////////////////////////////////////////////////////////////////////
+
+def format StringInst(*opTypeSet) {{
+    allBlocks = OutputBlocks()
+
+    regBlocks = specializeInst(Name, list(opTypeSet), EmulEnv())
+    eBlocks = specializeInst(Name + "_E", list(opTypeSet), EmulEnv())
+    nBlocks = specializeInst(Name + "_N", list(opTypeSet), EmulEnv())
+
+    for blocks in (regBlocks, eBlocks, nBlocks):
+        allBlocks.header_output += blocks.header_output
+        allBlocks.decoder_output += blocks.decoder_output
+        allBlocks.exec_output += blocks.exec_output
+
+    allBlocks.decode_block = '''
+        if (LEGACY_REP) {
+            %s
+        } else if (LEGACY_REPNE) {
+            %s
+        } else {
+            %s
+        }
+    ''' % (eBlocks.decode_block, nBlocks.decode_block, regBlocks.decode_block)
+
+    (header_output, decoder_output,
+     decode_block, exec_output) = allBlocks.makeList()
+}};
diff --git a/src/arch/x86/isa/insts/string/scan_string.py b/src/arch/x86/isa/insts/string/scan_string.py
index cd3d5b549..b038cc00a 100644
--- a/src/arch/x86/isa/insts/string/scan_string.py
+++ b/src/arch/x86/isa/insts/string/scan_string.py
@@ -53,16 +53,55 @@
 #
 # Authors: Gabe Black
 
-microcode = ""
-#let {{
-#    class SCAS(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SCASB(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SCASW(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SCASD(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#    class SCASQ(Inst):
-#	"GenFault ${new UnimpInstFault}"
-#}};
+microcode = '''
+def macroop SCAS_M {
+    # Find the constant we need to either add or subtract from rdi
+    ruflag t0, 10
+    movi t2, t2, dsz, flags=(CEZF,), dataSize=asz
+    subi t3, t0, dsz, dataSize=asz
+    mov t2, t2, t3, flags=(nCEZF,), dataSize=asz
+
+    ld t1, es, [1, t0, rdi]
+    sub t0, t1, rax, flags=(OF, SF, ZF, AF, PF, CF)
+
+    add rdi, rdi, t2, dataSize=asz
+};
+
+#
+# Versions which have the rep prefix. These could benefit from some loop
+# unrolling.
+#
+
+def macroop SCAS_E_M {
+    # Find the constant we need to either add or subtract from rdi
+    ruflag t0, 10
+    movi t2, t2, dsz, flags=(CEZF,), dataSize=asz
+    subi t3, t0, dsz, dataSize=asz
+    mov t2, t2, t3, flags=(nCEZF,), dataSize=asz
+
+    ld t1, es, [1, t0, rdi]
+    sub t0, t1, rax, flags=(OF, SF, ZF, AF, PF, CF)
+
+    subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
+    add rdi, rdi, t2, dataSize=asz
+    bri t0, 4, flags=(CSTRZnEZF,)
+    fault "NoFault"
+};
+
+def macroop SCAS_N_M {
+    # Find the constant we need to either add or subtract from rdi
+    ruflag t0, 10
+    movi t2, t2, dsz, flags=(CEZF,), dataSize=asz
+    subi t3, t0, dsz, dataSize=asz
+    mov t2, t2, t3, flags=(nCEZF,), dataSize=asz
+
+    ld t1, es, [1, t0, rdi]
+    sub t0, t1, rax, flags=(OF, SF, ZF, AF, PF, CF)
+
+    subi rcx, rcx, 1, flags=(EZF,), dataSize=asz
+    add rdi, rdi, t2, dataSize=asz
+    bri t0, 4, flags=(CSTRnZnEZF,)
+    fault "NoFault"
+};
+
+'''
diff --git a/src/arch/x86/isa/microasm.isa b/src/arch/x86/isa/microasm.isa
index 5c567a30c..af3148631 100644
--- a/src/arch/x86/isa/microasm.isa
+++ b/src/arch/x86/isa/microasm.isa
@@ -89,7 +89,7 @@ let {{
         "index" : "env.index",
         "base" : "env.base",
         "dsz" : "env.dataSize",
-        "osz" : "env.operandSize",
+        "asz" : "env.addressSize",
         "ssz" : "env.stackSize"
     }
     assembler.symbols.update(symbols)
@@ -107,11 +107,13 @@ let {{
         assembler.symbols[flag] = flag + "Bit"
 
     for cond in ('True', 'False', 'ECF', 'EZF', 'SZnZF',
-                 'MSTRZ', 'STRZ', 'MSTRC', 'STRZnZF',
+                 'MSTRZ', 'STRZ', 'MSTRC',
                  'OF', 'CF', 'ZF', 'CvZF',
                  'SF', 'PF', 'SxOF', 'SxOvZF'):
         assembler.symbols["C%s" % cond] = "ConditionTests::%s" % cond
         assembler.symbols["nC%s" % cond] = "ConditionTests::Not%s" % cond
+    assembler.symbols["CSTRZnEZF"] = "ConditionTests::STRZnEZF"
+    assembler.symbols["CSTRnZnEZF"] = "ConditionTests::STRnZnEZF"
 
     assembler.symbols["CTrue"] = "ConditionTests::True"
     assembler.symbols["CFalse"] = "ConditionTests::False"
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index ac88be657..608b86a70 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -89,7 +89,7 @@ def template MicroRegOpExecute {{
 }};
 
 def template MicroRegOpImmExecute {{
-        Fault %(class_name)sImm::execute(%(CPU_exec_context)s *xc,
+        Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
                 Trace::InstRecord *traceData) const
         {
             Fault fault = NoFault;
@@ -140,21 +140,21 @@ def template MicroRegOpDeclare {{
 
 def template MicroRegOpImmDeclare {{
 
-    class %(class_name)sImm : public %(base_class)s
+    class %(class_name)s : public %(base_class)s
     {
       protected:
         void buildMe();
 
       public:
-        %(class_name)sImm(ExtMachInst _machInst,
+        %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
                 bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
+                RegIndex _src1, uint16_t _imm8, RegIndex _dest,
                 uint8_t _dataSize, uint16_t _ext);
 
-        %(class_name)sImm(ExtMachInst _machInst,
+        %(class_name)s(ExtMachInst _machInst,
                 const char * instMnem,
-                RegIndex _src1, uint8_t _imm8, RegIndex _dest,
+                RegIndex _src1, uint16_t _imm8, RegIndex _dest,
                 uint8_t _dataSize, uint16_t _ext);
 
         %(BasicExecDeclare)s
@@ -196,14 +196,14 @@ def template MicroRegOpConstructor {{
 
 def template MicroRegOpImmConstructor {{
 
-    inline void %(class_name)sImm::buildMe()
+    inline void %(class_name)s::buildMe()
     {
         %(constructor)s;
     }
 
-    inline %(class_name)sImm::%(class_name)sImm(
+    inline %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem,
-            RegIndex _src1, uint8_t _imm8, RegIndex _dest,
+            RegIndex _src1, uint16_t _imm8, RegIndex _dest,
             uint8_t _dataSize, uint16_t _ext) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 false, false, false, false,
@@ -213,10 +213,10 @@ def template MicroRegOpImmConstructor {{
         buildMe();
     }
 
-    inline %(class_name)sImm::%(class_name)sImm(
+    inline %(class_name)s::%(class_name)s(
             ExtMachInst machInst, const char * instMnem,
             bool isMicro, bool isDelayed, bool isFirst, bool isLast,
-            RegIndex _src1, uint8_t _imm8, RegIndex _dest,
+            RegIndex _src1, uint16_t _imm8, RegIndex _dest,
             uint8_t _dataSize, uint16_t _ext) :
         %(base_class)s(machInst, "%(mnemonic)s", instMnem,
                 isMicro, isDelayed, isFirst, isLast,
@@ -310,7 +310,7 @@ let {{
     exec_output = ""
 
     # A function which builds the C++ classes that implement the microops
-    def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";"):
+    def setUpMicroRegOp(name, Name, base, code, flagCode = "", condCheck = "true", elseCode = ";", imm=False):
         global header_output
         global decoder_output
         global exec_output
@@ -321,9 +321,14 @@ let {{
                  "flag_code" : flagCode,
                  "cond_check" : condCheck,
                  "else_code" : elseCode})
-        header_output += MicroRegOpDeclare.subst(iop)
-        decoder_output += MicroRegOpConstructor.subst(iop)
-        exec_output += MicroRegOpExecute.subst(iop)
+        if imm:
+            header_output += MicroRegOpImmDeclare.subst(iop)
+            decoder_output += MicroRegOpImmConstructor.subst(iop)
+            exec_output += MicroRegOpImmExecute.subst(iop)
+        else:
+            header_output += MicroRegOpDeclare.subst(iop)
+            decoder_output += MicroRegOpConstructor.subst(iop)
+            exec_output += MicroRegOpExecute.subst(iop)
 
 
     checkCCFlagBits = "checkCondition(ccFlagBits)"
@@ -397,10 +402,11 @@ let {{
 
         microopClasses[name + 'i'] = RegOpChildImm
 
-        setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", immCode);
+        setUpMicroRegOp(name + "i", Name + "Imm", "X86ISA::RegOpImm", \
+                immCode, imm=True);
         setUpMicroRegOp(name + "i", Name + "ImmFlags", "X86ISA::RegOpImm",
                 immCode, flagCode=immFlagCode,
-                condCheck=condCode, elseCode=elseCode);
+                condCheck=condCode, elseCode=elseCode, imm=True);
 
     # This has it's own function because Wr ops have implicit destinations
     def defineMicroRegOpWr(mnemonic, code, elseCode=";"):
@@ -434,9 +440,11 @@ let {{
 
         microopClasses[name + 'i'] = RegOpChildImm
 
-        setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", immCode);
-        setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", immCode,
-                condCheck = checkCCFlagBits, elseCode = elseCode);
+        setUpMicroRegOp(name + 'i', Name + "Imm", "X86ISA::RegOpImm", \
+                immCode, imm=True);
+        setUpMicroRegOp(name + 'i', Name + "ImmFlags", "X86ISA::RegOpImm", \
+                immCode, condCheck = checkCCFlagBits, elseCode = elseCode, \
+                imm=True);
 
     # This has it's own function because Rd ops don't always have two parameters
     def defineMicroRegOpRd(mnemonic, code):
@@ -444,29 +452,52 @@ let {{
         name = mnemonic.lower()
 
         class RegOpChild(RegOp):
+            className = Name
+            mnemonic = name
             def __init__(self, dest, src1 = "NUM_INTREGS", dataSize="env.dataSize"):
                 super(RegOpChild, self).__init__(dest, src1, "NUM_INTREGS", None, dataSize)
-                self.className = Name
-                self.mnemonic = name
 
         microopClasses[name] = RegOpChild
 
         setUpMicroRegOp(name, Name, "X86ISA::RegOp", code);
 
-    def defineMicroRegOpImm(mnemonic, code):
+    def defineMicroRegOpImm(mnemonic, code, flagCode=""):
         Name = mnemonic
         name = mnemonic.lower()
         code = immPick + code
 
         class RegOpChild(RegOpImm):
-            def __init__(self, dest, src1, src2, dataSize="env.dataSize"):
-                super(RegOpChild, self).__init__(dest, src1, src2, None, dataSize)
-                self.className = Name
-                self.mnemonic = name
+            className = Name
+            mnemonic = name
+            def __init__(self, dest, src1, src2, \
+                    flags=None, dataSize="env.dataSize"):
+                super(RegOpChild, self).__init__(dest, \
+                        src1, src2, flags, dataSize)
 
         microopClasses[name] = RegOpChild
 
-        setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code);
+        setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, imm=True);
+        setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOpImm", \
+                code, flagCode=flagCode, imm=True);
+
+    def defineMicroRegOpRdImm(mnemonic, code, flagCode=""):
+        Name = mnemonic
+        name = mnemonic.lower()
+        code = immPick + code
+
+        class RegOpChildRdImm(RegOpImm):
+            className = Name
+            mnemonic = name
+            def __init__(self, dest, imm, flags=None, \
+                    dataSize="env.dataSize"):
+                super(RegOpChildRdImm, self).__init__(dest, \
+                        "NUM_INTREGS", imm, flags, dataSize)
+
+        microopClasses[name] = RegOpChildRdImm
+
+        setUpMicroRegOp(name, Name, "X86ISA::RegOpImm", code, imm=True);
+        setUpMicroRegOp(name, Name + "Flags", "X86ISA::RegOpImm", \
+                code, flagCode=flagCode, imm=True);
 
     defineMicroRegOp('Add', 'DestReg = merge(DestReg, psrc1 + op2, dataSize)')
     defineMicroRegOp('Or', 'DestReg = merge(DestReg, psrc1 | op2, dataSize);',
@@ -615,12 +646,17 @@ let {{
             ''')
 
     defineMicroRegOpWr('Wrip', 'RIP = psrc1 + op2', elseCode="RIP = RIP;")
+    defineMicroRegOpWr('Br', 'nuIP = psrc1 + op2;', elseCode='nuIP = nuIP;')
     defineMicroRegOpWr('Wruflags', 'ccFlagBits = psrc1 ^ op2')
 
     defineMicroRegOpRd('Rdip', 'DestReg = RIP')
     defineMicroRegOpRd('Ruflags', 'DestReg = ccFlagBits')
-    defineMicroRegOpImm('Ruflag', 'DestReg = bits(ccFlagBits, imm8);', \
-            flagCode = genCCFlagBitsLogic)
+    defineMicroRegOpRdImm('Ruflag', '''
+            int flag = bits(ccFlagBits, (1 << imm8) + 0*psrc1);
+            DestReg = merge(DestReg, flag, dataSize);
+            ccFlagBits = ccFlagBits & ~EZFBit;
+            ccFlagBits = ccFlagBits | ((flag == 0) ? EZFBit : 0);
+            ''')
 
     defineMicroRegOpImm('Sext', '''
             IntReg val = psrc1;
diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa
index 64179ca98..098a75370 100644
--- a/src/arch/x86/isa/operands.isa
+++ b/src/arch/x86/isa/operands.isa
@@ -104,7 +104,9 @@ def operands {{
         'Data':          ('IntReg', 'uqw', '(((data & 0x1C) == 4 ? foldOBit : 0) | data)', 'IsInteger', 6),
         'rax':           ('IntReg', 'uqw', '(INTREG_RAX)', 'IsInteger', 7),
         'RIP':           ('NPC', 'uqw', None, (None, None, 'IsControl'), 10),
-        'ccFlagBits':       ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
+        'uIP':           ('UPC', 'uqw', None, (None, None, 'IsControl'), 11),
+        'nuIP':          ('NUPC', 'uqw', None, (None, None, 'IsControl'), 12),
+        'ccFlagBits':    ('IntReg', 'uqw', 'NUM_INTREGS + NumMicroIntRegs', None, 20),
         'SegBase':       ('ControlReg', 'uqw', 'MISCREG_SEG_BASE_BASE + segment', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 50),
         'Mem':           ('Mem', 'uqw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 100)
 }};
diff --git a/src/base/compiler.hh b/src/base/compiler.hh
index dc23ed7b3..2c655af60 100644
--- a/src/base/compiler.hh
+++ b/src/base/compiler.hh
@@ -40,11 +40,13 @@
 #define M5_ATTR_NORETURN  __attribute__((noreturn))
 #define M5_PRAGMA_NORETURN(x)
 #define M5_DUMMY_RETURN
+#define M5_VAR_USED __attribute__((unused))
 #elif defined(__SUNPRO_CC)
 // this doesn't do anything with sun cc, but why not
 #define M5_ATTR_NORETURN  __sun_attr__((__noreturn__))
 #define M5_DUMMY_RETURN return (0);
 #define DO_PRAGMA(x) _Pragma(#x)
+#define M5_VAR_USED
 #define M5_PRAGMA_NORETURN(x) DO_PRAGMA(does_not_return(x))
 #else
 #error "Need to define compiler options in base/compiler.hh"
diff --git a/src/base/range_ops.hh b/src/base/range_ops.hh
new file mode 100644
index 000000000..f2b11b649
--- /dev/null
+++ b/src/base/range_ops.hh
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2007 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Ali Saidi
+ */
+
+#ifndef __BASE_RANGE_OPS_HH__
+#define __BASE_RANGE_OPS_HH__
+#include <list>
+#include <vector>
+
+#include "base/range.hh"
+
+template <class T>
+inline void
+FilterRangeList(std::vector<Range<T> > filter_list, std::list<Range<T> >
+        &range_list) {
+    typename std::list<Range<T> >::iterator i;
+    for (int x = 0; x < filter_list.size(); x++) {
+        for (i = range_list.begin(); i != range_list.end(); ) {
+            // Is the range within one of our filter ranges?
+            if (filter_list[x] == i->start || filter_list[x] == i->end)
+                range_list.erase(i++);
+            else
+                i++;
+        }
+    }
+}
+
+#endif //__BASE_RANGE_OPS_HH__
+
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index 8be84392d..7a51650e6 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -93,10 +93,11 @@ class BaseCPU(SimObject):
 
     def connectMemPorts(self, bus):
         for p in self._mem_ports:
-            exec('self.%s = bus.port' % p)
+            if p != 'physmem_port':
+                exec('self.%s = bus.port' % p)
 
     def addPrivateSplitL1Caches(self, ic, dc):
-        assert(len(self._mem_ports) == 2)
+        assert(len(self._mem_ports) == 2 or len(self._mem_ports) == 3)
         self.icache = ic
         self.dcache = dc
         self.icache_port = ic.cpu_side
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index e97f059c1..bfd1825c2 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -40,4 +40,5 @@ class AtomicSimpleCPU(BaseCPU):
         profile = Param.Latency('0ns', "trace the kernel stack")
     icache_port = Port("Instruction Port")
     dcache_port = Port("Data Port")
-    _mem_ports = ['icache_port', 'dcache_port']
+    physmem_port = Port("Physical Memory Port")
+    _mem_ports = ['icache_port', 'dcache_port', 'physmem_port']
diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 704b65f36..e2a7d5938 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -67,6 +67,10 @@ AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
         return &dcachePort;
     else if (if_name == "icache_port")
         return &icachePort;
+    else if (if_name == "physmem_port") {
+        hasPhysMemPort = true;
+        return &physmemPort;
+    }
     else
         panic("No Such Port\n");
 }
@@ -83,6 +87,12 @@ AtomicSimpleCPU::init()
         TheISA::initCPU(tc, tc->readCpuId());
     }
 #endif
+    if (hasPhysMemPort) {
+        bool snoop = false;
+        AddrRangeList pmAddrList;
+        physmemPort.getPeerAddressRanges(pmAddrList, snoop);
+        physMemAddr = *pmAddrList.begin();
+    }
 }
 
 bool
@@ -141,7 +151,8 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
 AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
     : BaseSimpleCPU(p), tickEvent(this),
       width(p->width), simulate_stalls(p->simulate_stalls),
-      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
+      icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
+      physmemPort(name() + "-iport", this), hasPhysMemPort(false)
 {
     _status = Idle;
 
@@ -293,8 +304,12 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
 
         if (req->isMmapedIpr())
             dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
-        else
-            dcache_latency = dcachePort.sendAtomic(&pkt);
+        else {
+            if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
+                dcache_latency = physmemPort.sendAtomic(&pkt);
+            else
+                dcache_latency = dcachePort.sendAtomic(&pkt);
+        }
         dcache_access = true;
         assert(!pkt.isError());
 
@@ -402,7 +417,10 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
                 dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
             } else {
                 data = htog(data);
-                dcache_latency = dcachePort.sendAtomic(&pkt);
+                if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
+                    dcache_latency = physmemPort.sendAtomic(&pkt);
+                else
+                    dcache_latency = dcachePort.sendAtomic(&pkt);
             }
             dcache_access = true;
             assert(!pkt.isError());
@@ -513,7 +531,12 @@ AtomicSimpleCPU::tick()
                                            Packet::Broadcast);
                 ifetch_pkt.dataStatic(&inst);
 
-                icache_latency = icachePort.sendAtomic(&ifetch_pkt);
+                if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
+                    icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
+                else
+                    icache_latency = icachePort.sendAtomic(&ifetch_pkt);
+
+
                 // ifetch_req is initialized to read the instruction directly
                 // into the CPU object's inst field.
             //}
diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh
index 28e883b24..96429e5b1 100644
--- a/src/cpu/simple/atomic.hh
+++ b/src/cpu/simple/atomic.hh
@@ -121,6 +121,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     };
     DcachePort dcachePort;
 
+    CpuPort physmemPort;
+    bool hasPhysMemPort;
     Request ifetch_req;
     Request data_read_req;
     Request data_write_req;
@@ -128,6 +130,8 @@ class AtomicSimpleCPU : public BaseSimpleCPU
     bool dcache_access;
     Tick dcache_latency;
 
+    Range<Addr> physMemAddr;
+
   public:
 
     virtual Port *getPort(const std::string &if_name, int idx = -1);
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 0550aa036..22ffff3b9 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -291,11 +291,15 @@ class BaseSimpleCPU : public BaseCPU
     }
 
     uint64_t readPC() { return thread->readPC(); }
+    uint64_t readMicroPC() { return thread->readMicroPC(); }
     uint64_t readNextPC() { return thread->readNextPC(); }
+    uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
     uint64_t readNextNPC() { return thread->readNextNPC(); }
 
     void setPC(uint64_t val) { thread->setPC(val); }
+    void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
     void setNextPC(uint64_t val) { thread->setNextPC(val); }
+    void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
     void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
 
     MiscReg readMiscRegNoEffect(int misc_reg)
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index f32b61ee5..2e1ebd766 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -353,9 +353,7 @@ class StaticInst : public StaticInstBase
     StaticInst(const char *_mnemonic, ExtMachInst _machInst, OpClass __opClass)
         : StaticInstBase(__opClass),
           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
-    {
-        memset(&recentDecodes, 0, 2 * sizeof(cacheElement));
-    }
+    { }
 
   public:
 
@@ -459,6 +457,9 @@ class StaticInst : public StaticInstBase
     struct cacheElement {
         Addr page_addr;
         AddrDecodePage *decodePage;
+
+        cacheElement()
+          :decodePage(NULL) { }
     } ;
 
     /// An array of recently decoded instructions.
diff --git a/src/dev/io_device.hh b/src/dev/io_device.hh
index e65400ca2..876166adb 100644
--- a/src/dev/io_device.hh
+++ b/src/dev/io_device.hh
@@ -266,8 +266,7 @@ class DmaDevice : public PioDevice
 
     void dmaWrite(Addr addr, int size, Event *event, uint8_t *data)
     {
-        dmaPort->dmaAction(MemCmd::WriteInvalidateReq,
-                           addr, size, event, data);
+        dmaPort->dmaAction(MemCmd::WriteReq, addr, size, event, data);
     }
 
     void dmaRead(Addr addr, int size, Event *event, uint8_t *data)
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index 8377221cd..b48e1684d 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -40,5 +40,7 @@ class Bridge(MemObject):
     delay = Param.Latency('0ns', "The latency of this bridge")
     nack_delay = Param.Latency('0ns', "The latency of this bridge")
     write_ack = Param.Bool(False, "Should this bridge ack writes")
-    fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes")
-    fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes")
+    filter_ranges_a = VectorParam.AddrRange([],
+            "What addresses shouldn't be passed through the side of the bridge")
+    filter_ranges_b = VectorParam.AddrRange([],
+            "What addresses shouldn't be passed through the side of the bridge")
diff --git a/src/mem/bridge.cc b/src/mem/bridge.cc
index 6cfa5a2ac..c502c5130 100644
--- a/src/mem/bridge.cc
+++ b/src/mem/bridge.cc
@@ -37,6 +37,7 @@
 
 #include <algorithm>
 
+#include "base/range_ops.hh"
 #include "base/trace.hh"
 #include "mem/bridge.hh"
 #include "params/Bridge.hh"
@@ -44,9 +45,10 @@
 Bridge::BridgePort::BridgePort(const std::string &_name,
                                Bridge *_bridge, BridgePort *_otherPort,
                                int _delay, int _nack_delay, int _req_limit,
-                               int _resp_limit, bool fix_partial_write)
+                               int _resp_limit,
+                               std::vector<Range<Addr> > filter_ranges)
     : Port(_name), bridge(_bridge), otherPort(_otherPort),
-      delay(_delay), nackDelay(_nack_delay), fixPartialWrite(fix_partial_write),
+      delay(_delay), nackDelay(_nack_delay), filterRanges(filter_ranges),
       outstandingResponses(0), queuedRequests(0), inRetry(false),
       reqQueueLimit(_req_limit), respQueueLimit(_resp_limit), sendEvent(this)
 {
@@ -55,9 +57,9 @@ Bridge::BridgePort::BridgePort(const std::string &_name,
 Bridge::Bridge(Params *p)
     : MemObject(p->name),
       portA(p->name + "-portA", this, &portB, p->delay, p->nack_delay,
-              p->req_size_a, p->resp_size_a, p->fix_partial_write_a),
+              p->req_size_a, p->resp_size_a, p->filter_ranges_a),
       portB(p->name + "-portB", this, &portA, p->delay, p->nack_delay,
-              p->req_size_b, p->resp_size_b, p->fix_partial_write_b),
+              p->req_size_b, p->resp_size_b, p->filter_ranges_b),
       ackWrites(p->write_ack), _params(p)
 {
     if (ackWrites)
@@ -243,17 +245,6 @@ Bridge::BridgePort::trySend()
 
     PacketPtr pkt = buf->pkt;
 
-    // Ugly! @todo When multilevel coherence works this will be removed
-    if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite &&
-            !pkt->wasNacked()) {
-        PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq,
-                            Packet::Broadcast);
-        funcPkt->dataStatic(pkt->getPtr<uint8_t>());
-        sendFunctional(funcPkt);
-        pkt->cmd = MemCmd::WriteReq;
-        delete funcPkt;
-    }
-
     DPRINTF(BusBridge, "trySend: origSrc %d dest %d addr 0x%x\n",
             buf->origSrc, pkt->getDest(), pkt->getAddr());
 
@@ -313,17 +304,6 @@ Bridge::BridgePort::recvRetry()
 Tick
 Bridge::BridgePort::recvAtomic(PacketPtr pkt)
 {
-    // fix partial atomic writes... similar to the timing code that does the
-    // same... will be removed once our code gets this right
-    if (pkt->cmd == MemCmd::WriteInvalidateReq && fixPartialWrite) {
-
-        PacketPtr funcPkt = new Packet(pkt->req, MemCmd::WriteReq,
-                         Packet::Broadcast);
-        funcPkt->dataStatic(pkt->getPtr<uint8_t>());
-        otherPort->sendFunctional(funcPkt);
-        delete funcPkt;
-        pkt->cmd = MemCmd::WriteReq;
-    }
     return delay + otherPort->sendAtomic(pkt);
 }
 
@@ -355,6 +335,7 @@ Bridge::BridgePort::getDeviceAddressRanges(AddrRangeList &resp,
                                            bool &snoop)
 {
     otherPort->getPeerAddressRanges(resp, snoop);
+    FilterRangeList(filterRanges, resp);
     // we don't allow snooping across bridges
     snoop = false;
 }
diff --git a/src/mem/bridge.hh b/src/mem/bridge.hh
index d3bbf2ddf..82001948e 100644
--- a/src/mem/bridge.hh
+++ b/src/mem/bridge.hh
@@ -70,7 +70,8 @@ class Bridge : public MemObject
         /** Min delay to respond to a nack. */
         Tick nackDelay;
 
-        bool fixPartialWrite;
+        /** Pass ranges from one side of the bridge to the other? */
+        std::vector<Range<Addr> > filterRanges;
 
         class PacketBuffer : public Packet::SenderState {
 
@@ -156,7 +157,8 @@ class Bridge : public MemObject
         /** Constructor for the BusPort.*/
         BridgePort(const std::string &_name, Bridge *_bridge,
                 BridgePort *_otherPort, int _delay, int _nack_delay,
-                int _req_limit, int _resp_limit, bool fix_partial_write);
+                int _req_limit, int _resp_limit,
+                std::vector<Range<Addr> > filter_ranges);
 
       protected:
 
diff --git a/src/mem/bus.cc b/src/mem/bus.cc
index cb359734b..42c4431bb 100644
--- a/src/mem/bus.cc
+++ b/src/mem/bus.cc
@@ -84,6 +84,7 @@ Bus::deletePortRefs(Port *p)
     if (funcPort == bp)
         return;
     interfaces.erase(bp->getId());
+    clearBusCache();
     delete bp;
 }
 
@@ -176,7 +177,16 @@ Bus::recvTiming(PacketPtr pkt)
     DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s\n",
             src, pkt->getDest(), pkt->getAddr(), pkt->cmdString());
 
-    BusPort *src_port = (src == defaultId) ? defaultPort : interfaces[src];
+    BusPort *src_port;
+    if (src == defaultId)
+        src_port = defaultPort;
+    else {
+        src_port = checkBusCache(src);
+        if (src_port == NULL) {
+            src_port = interfaces[src];
+            updateBusCache(src, src_port);
+        }
+    }
 
     // If the bus is busy, or other devices are in line ahead of the current
     // one, put this device on the retry list.
@@ -201,25 +211,28 @@ Bus::recvTiming(PacketPtr pkt)
         dest_port_id = findPort(pkt->getAddr());
         dest_port = (dest_port_id == defaultId) ?
             defaultPort : interfaces[dest_port_id];
-        for (SnoopIter s_iter = snoopPorts.begin();
-             s_iter != snoopPorts.end();
-             s_iter++) {
+        SnoopIter s_end = snoopPorts.end();
+        for (SnoopIter s_iter = snoopPorts.begin(); s_iter != s_end; s_iter++) {
             BusPort *p = *s_iter;
             if (p != dest_port && p != src_port) {
-#ifndef NDEBUG
                 // cache is not allowed to refuse snoop
-                bool success = p->sendTiming(pkt);
+                bool success M5_VAR_USED = p->sendTiming(pkt);
                 assert(success);
-#else
-                // avoid unused variable warning
-                p->sendTiming(pkt);
-#endif
             }
         }
     } else {
         assert(dest >= 0 && dest < maxId);
         assert(dest != src); // catch infinite loops
         dest_port_id = dest;
+        if (dest_port_id == defaultId)
+            dest_port = defaultPort;
+        else {
+            dest_port = checkBusCache(dest);
+            if (dest_port == NULL) {
+                dest_port = interfaces[dest_port_id];
+            // updateBusCache(dest_port_id, dest_port);
+            }
+        }
         dest_port = (dest_port_id == defaultId) ?
             defaultPort : interfaces[dest_port_id];
     }
@@ -291,15 +304,19 @@ Bus::findPort(Addr addr)
     /* An interval tree would be a better way to do this. --ali. */
     int dest_id = -1;
 
-    PortIter i = portMap.find(RangeSize(addr,1));
-    if (i != portMap.end())
-        dest_id = i->second;
+    dest_id = checkPortCache(addr);
+    if (dest_id == -1) {
+        PortIter i = portMap.find(RangeSize(addr,1));
+        if (i != portMap.end())
+          dest_id = i->second;
+        updatePortCache(dest_id, i->first.start, i->first.end);
+    }
 
     // Check if this matches the default range
     if (dest_id == -1) {
-        for (AddrRangeIter iter = defaultRange.begin();
-             iter != defaultRange.end(); iter++) {
-            if (*iter == addr) {
+        AddrRangeIter a_end = defaultRange.end();
+        for (AddrRangeIter i = defaultRange.begin(); i != a_end; i++) {
+            if (*i == addr) {
                 DPRINTF(Bus, "  found addr %#llx on default\n", addr);
                 return defaultId;
             }
@@ -340,8 +357,16 @@ Bus::recvAtomic(PacketPtr pkt)
     int orig_src = pkt->getSrc();
 
     int target_port_id = findPort(pkt->getAddr());
-    Port *target_port = (target_port_id == defaultId) ?
-        defaultPort : interfaces[target_port_id];
+    BusPort *target_port;
+    if (target_port_id == defaultId)
+        target_port = defaultPort;
+    else {
+      target_port = checkBusCache(target_port_id);
+      if (target_port == NULL) {
+          target_port = interfaces[target_port_id];
+          updateBusCache(target_port_id, target_port);
+      }
+    }
 
     SnoopIter s_end = snoopPorts.end();
     for (SnoopIter s_iter = snoopPorts.begin(); s_iter != s_end; s_iter++) {
@@ -406,9 +431,8 @@ Bus::recvFunctional(PacketPtr pkt)
 
     assert(pkt->isRequest()); // hasn't already been satisfied
 
-    for (SnoopIter s_iter = snoopPorts.begin();
-         s_iter != snoopPorts.end();
-         s_iter++) {
+    SnoopIter s_end = snoopPorts.end();
+    for (SnoopIter s_iter = snoopPorts.begin(); s_iter != s_end; s_iter++) {
         BusPort *p = *s_iter;
         if (p != port && p->getId() != src_id) {
             p->sendFunctional(pkt);
@@ -433,11 +457,16 @@ Bus::recvStatusChange(Port::Status status, int id)
     bool snoops;
     AddrRangeIter iter;
 
+    if (inRecvStatusChange.count(id))
+        return;
+    inRecvStatusChange.insert(id);
+
     assert(status == Port::RangeChange &&
            "The other statuses need to be implemented.");
 
     DPRINTF(BusAddrRanges, "received RangeChange from device id %d\n", id);
 
+    clearPortCache();
     if (id == defaultId) {
         defaultRange.clear();
         // Only try to update these ranges if the user set a default responder.
@@ -499,6 +528,7 @@ Bus::recvStatusChange(Port::Status status, int id)
 
     if (id != defaultId && defaultPort)
         defaultPort->sendStatusChange(Port::RangeChange);
+    inRecvStatusChange.erase(id);
 }
 
 void
@@ -557,14 +587,14 @@ Bus::findBlockSize(int id)
 
     int max_bs = -1;
 
-    for (PortIter portIter = portMap.begin();
-         portIter != portMap.end(); portIter++) {
-        int tmp_bs = interfaces[portIter->second]->peerBlockSize();
+    PortIter p_end = portMap.end();
+    for (PortIter p_iter = portMap.begin(); p_iter != p_end; p_iter++) {
+        int tmp_bs = interfaces[p_iter->second]->peerBlockSize();
         if (tmp_bs > max_bs)
             max_bs = tmp_bs;
     }
-    for (SnoopIter s_iter = snoopPorts.begin();
-         s_iter != snoopPorts.end(); s_iter++) {
+    SnoopIter s_end = snoopPorts.end();
+    for (SnoopIter s_iter = snoopPorts.begin(); s_iter != s_end; s_iter++) {
         int tmp_bs = (*s_iter)->peerBlockSize();
         if (tmp_bs > max_bs)
             max_bs = tmp_bs;
diff --git a/src/mem/bus.hh b/src/mem/bus.hh
index 06ccd4ac0..0c594c463 100644
--- a/src/mem/bus.hh
+++ b/src/mem/bus.hh
@@ -38,6 +38,7 @@
 #define __MEM_BUS_HH__
 
 #include <string>
+#include <set>
 #include <list>
 #include <inttypes.h>
 
@@ -180,6 +181,60 @@ class Bus : public MemObject
      */
     int findPort(Addr addr);
 
+    // Cache for the findPort function storing recently used ports from portMap
+    struct PortCache {
+        bool valid;
+        int  id;
+        Addr start;
+        Addr end;
+    };
+
+    PortCache portCache[3];
+
+    // Checks the cache and returns the id of the port that has the requested
+    // address within its range
+    inline int checkPortCache(Addr addr) {
+        if (portCache[0].valid && addr >= portCache[0].start &&
+            addr < portCache[0].end) {
+            return portCache[0].id;
+        }
+        if (portCache[1].valid && addr >= portCache[1].start &&
+                   addr < portCache[1].end) {
+            return portCache[1].id;
+        }
+        if (portCache[2].valid && addr >= portCache[2].start &&
+            addr < portCache[2].end) {
+            return portCache[2].id;
+        }
+
+        return -1;
+    }
+
+    // Clears the earliest entry of the cache and inserts a new port entry
+    inline void updatePortCache(short id, Addr start, Addr end) {
+        portCache[2].valid = portCache[1].valid;
+        portCache[2].id    = portCache[1].id;
+        portCache[2].start = portCache[1].start;
+        portCache[2].end   = portCache[1].end;
+
+        portCache[1].valid = portCache[0].valid;
+        portCache[1].id    = portCache[0].id;
+        portCache[1].start = portCache[0].start;
+        portCache[1].end   = portCache[0].end;
+
+        portCache[0].valid = true;
+        portCache[0].id    = id;
+        portCache[0].start = start;
+        portCache[0].end   = end;
+    }
+
+    // Clears the cache. Needs to be called in constructor.
+    inline void clearPortCache() {
+        portCache[2].valid = false;
+        portCache[1].valid = false;
+        portCache[0].valid = false;
+    }
+
     /** Process address range request.
      * @param resp addresses that we can respond to
      * @param snoop addresses that we would like to snoop
@@ -199,6 +254,7 @@ class Bus : public MemObject
     BusFreeEvent busIdle;
 
     bool inRetry;
+    std::set<int> inRecvStatusChange;
 
     /** max number of bus ids we've handed out so far */
     short maxId;
@@ -246,6 +302,54 @@ class Bus : public MemObject
     int cachedBlockSize;
     bool cachedBlockSizeValid;
 
+   // Cache for the peer port interfaces
+    struct BusCache {
+        bool  valid;
+        short id;
+        BusPort  *port;
+    };
+
+    BusCache busCache[3];
+
+    // Checks the peer port interfaces cache for the port id and returns
+    // a pointer to the matching port
+    inline BusPort* checkBusCache(short id) {
+        if (busCache[0].valid && id == busCache[0].id) {
+            return busCache[0].port;
+        }
+        if (busCache[1].valid && id == busCache[1].id) {
+            return busCache[1].port;
+        }
+        if (busCache[2].valid && id == busCache[2].id) {
+            return busCache[2].port;
+        }
+
+        return NULL;
+    }
+
+    // Replaces the earliest entry in the cache with a new entry
+    inline void updateBusCache(short id, BusPort *port) {
+        busCache[2].valid = busCache[1].valid;
+        busCache[2].id    = busCache[1].id;
+        busCache[2].port  = busCache[1].port;
+
+        busCache[1].valid = busCache[0].valid;
+        busCache[1].id    = busCache[0].id;
+        busCache[1].port  = busCache[0].port;
+
+        busCache[0].valid = true;
+        busCache[0].id    = id;
+        busCache[0].port  = port;
+    }
+
+    // Invalidates the cache. Needs to be called in constructor.
+    inline void clearBusCache() {
+        busCache[2].valid = false;
+        busCache[1].valid = false;
+        busCache[0].valid = false;
+    }
+
+
   public:
 
     /** A function used to return the port associated with this bus object. */
@@ -270,6 +374,8 @@ class Bus : public MemObject
             fatal("Bus width must be positive\n");
         if (clock <= 0)
             fatal("Bus clock period must be positive\n");
+        clearBusCache();
+        clearPortCache();
     }
 
 };
diff --git a/src/mem/cache/BaseCache.py b/src/mem/cache/BaseCache.py
index 2bf44cdf9..f6d42b1ef 100644
--- a/src/mem/cache/BaseCache.py
+++ b/src/mem/cache/BaseCache.py
@@ -81,4 +81,8 @@ class BaseCache(MemObject):
          "Only prefetch on data not on instruction accesses")
     cpu_side = Port("Port on side closer to CPU")
     mem_side = Port("Port on side closer to MEM")
+    cpu_side_filter_ranges = VectorParam.AddrRange([],
+            "What addresses shouldn't be passed through the side of the bridge")
+    mem_side_filter_ranges = VectorParam.AddrRange([],
+            "What addresses shouldn't be passed through the side of the bridge")
     addr_range = VectorParam.AddrRange(AllMemory, "The address range in bytes")
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index b44468486..0c8b02cb3 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -40,9 +40,10 @@
 
 using namespace std;
 
-BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache)
+BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
+        std::vector<Range<Addr> > filter_ranges)
     : SimpleTimingPort(_name, _cache), cache(_cache), otherPort(NULL),
-      blocked(false), mustSendRetry(false)
+      blocked(false), mustSendRetry(false), filterRanges(filter_ranges)
 {
 }
 
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 719ab0245..6a4eec43e 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -98,7 +98,8 @@ class BaseCache : public MemObject
         BaseCache *cache;
 
       protected:
-        CachePort(const std::string &_name, BaseCache *_cache);
+        CachePort(const std::string &_name, BaseCache *_cache,
+                std::vector<Range<Addr> > filter_ranges);
 
         virtual void recvStatusChange(Status status);
 
@@ -124,6 +125,9 @@ class BaseCache : public MemObject
 
         bool mustSendRetry;
 
+        /** filter ranges */
+        std::vector<Range<Addr> > filterRanges;
+
         void requestBus(RequestCause cause, Tick time)
         {
             DPRINTF(CachePort, "Asserting bus request for cause %d\n", cause);
@@ -367,15 +371,21 @@ class BaseCache : public MemObject
          */
         Counter maxMisses;
 
+        std::vector<Range<Addr> > cpuSideFilterRanges;
+        std::vector<Range<Addr> > memSideFilterRanges;
         /**
          * Construct an instance of this parameter class.
          */
         Params(int _hitLatency, int _blkSize,
                int _numMSHRs, int _numTargets, int _numWriteBuffers,
-               Counter _maxMisses)
+               Counter _maxMisses,
+               std::vector<Range<Addr> > cpu_side_filter_ranges,
+               std::vector<Range<Addr> > mem_side_filter_ranges)
             : hitLatency(_hitLatency), blkSize(_blkSize),
               numMSHRs(_numMSHRs), numTargets(_numTargets),
-              numWriteBuffers(_numWriteBuffers), maxMisses(_maxMisses)
+              numWriteBuffers(_numWriteBuffers), maxMisses(_maxMisses),
+              cpuSideFilterRanges(cpu_side_filter_ranges),
+              memSideFilterRanges(mem_side_filter_ranges)
         {
         }
     };
diff --git a/src/mem/cache/cache.hh b/src/mem/cache/cache.hh
index 57028a05e..821fa9702 100644
--- a/src/mem/cache/cache.hh
+++ b/src/mem/cache/cache.hh
@@ -72,7 +72,8 @@ class Cache : public BaseCache
     {
       public:
         CpuSidePort(const std::string &_name,
-                    Cache<TagStore> *_cache);
+                    Cache<TagStore> *_cache,
+                    std::vector<Range<Addr> > filterRanges);
 
         // BaseCache::CachePort just has a BaseCache *; this function
         // lets us get back the type info we lost when we stored the
@@ -95,7 +96,8 @@ class Cache : public BaseCache
     {
       public:
         MemSidePort(const std::string &_name,
-                    Cache<TagStore> *_cache);
+                    Cache<TagStore> *_cache,
+                    std::vector<Range<Addr> > filterRanges);
 
         // BaseCache::CachePort just has a BaseCache *; this function
         // lets us get back the type info we lost when we stored the
diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc
index 4c9592a1b..0f8b52af2 100644
--- a/src/mem/cache/cache_builder.cc
+++ b/src/mem/cache/cache_builder.cc
@@ -241,7 +241,8 @@ BaseCacheParams::create()
     // Build BaseCache param object
     BaseCache::Params base_params(latency, block_size,
                                   mshrs, tgts_per_mshr, write_buffers,
-                                  max_miss_count);
+                                  max_miss_count, cpu_side_filter_ranges,
+                                  mem_side_filter_ranges);
 
     //Warnings about prefetcher policy
     if (prefetch_policy == Enums::none) {
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index d144266ed..402e34db2 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -39,6 +39,7 @@
 
 #include "sim/host.hh"
 #include "base/misc.hh"
+#include "base/range_ops.hh"
 
 #include "mem/cache/cache.hh"
 #include "mem/cache/cache_blk.hh"
@@ -61,8 +62,10 @@ Cache<TagStore>::Cache(const std::string &_name,
     tempBlock = new BlkType();
     tempBlock->data = new uint8_t[blkSize];
 
-    cpuSidePort = new CpuSidePort(_name + "-cpu_side_port", this);
-    memSidePort = new MemSidePort(_name + "-mem_side_port", this);
+    cpuSidePort = new CpuSidePort(_name + "-cpu_side_port", this,
+            params.baseParams.cpuSideFilterRanges);
+    memSidePort = new MemSidePort(_name + "-mem_side_port", this,
+            params.baseParams.memSideFilterRanges);
     cpuSidePort->setOtherPort(memSidePort);
     memSidePort->setOtherPort(cpuSidePort);
 
@@ -88,7 +91,8 @@ Cache<TagStore>::getPort(const std::string &if_name, int idx)
     } else if (if_name == "mem_side") {
         return memSidePort;
     } else if (if_name == "functional") {
-        return new CpuSidePort(name() + "-cpu_side_funcport", this);
+        return new CpuSidePort(name() + "-cpu_side_funcport", this,
+                std::vector<Range<Addr> >());
     } else {
         panic("Port name %s unrecognized\n", if_name);
     }
@@ -1221,6 +1225,7 @@ getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
     // CPU side port doesn't snoop; it's a target only.
     bool dummy;
     otherPort->getPeerAddressRanges(resp, dummy);
+    FilterRangeList(filterRanges, resp);
     snoop = false;
 }
 
@@ -1262,8 +1267,9 @@ Cache<TagStore>::CpuSidePort::recvFunctional(PacketPtr pkt)
 template<class TagStore>
 Cache<TagStore>::
 CpuSidePort::CpuSidePort(const std::string &_name,
-                         Cache<TagStore> *_cache)
-    : BaseCache::CachePort(_name, _cache)
+                         Cache<TagStore> *_cache, std::vector<Range<Addr> >
+                         filterRanges)
+    : BaseCache::CachePort(_name, _cache, filterRanges)
 {
 }
 
@@ -1279,6 +1285,8 @@ Cache<TagStore>::MemSidePort::
 getDeviceAddressRanges(AddrRangeList &resp, bool &snoop)
 {
     otherPort->getPeerAddressRanges(resp, snoop);
+    FilterRangeList(filterRanges, resp);
+
     // Memory-side port always snoops, so unconditionally set flag for
     // caller.
     snoop = true;
@@ -1416,8 +1424,9 @@ Cache<TagStore>::MemSidePort::processSendEvent()
 
 template<class TagStore>
 Cache<TagStore>::
-MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache)
-    : BaseCache::CachePort(_name, _cache)
+MemSidePort::MemSidePort(const std::string &_name, Cache<TagStore> *_cache,
+        std::vector<Range<Addr> > filterRanges)
+    : BaseCache::CachePort(_name, _cache, filterRanges)
 {
     // override default send event from SimpleTimingPort
     delete sendEvent;
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index de8fe2474..0e58d39af 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -52,10 +52,28 @@ class L2(BaseCache):
     tgts_per_mshr = 16
     write_buffers = 8
 
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
+    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+
 #cpu
 cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeLinuxAlphaSystem('atomic')
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
 
 system.cpu = cpus
 #create the l1/l2 bus
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index 2ba50273a..2374734ec 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -52,10 +52,28 @@ class L2(BaseCache):
     tgts_per_mshr = 16
     write_buffers = 8
 
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
+    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+
 #cpu
 cpu = AtomicSimpleCPU(cpu_id=0)
 #the system
 system = FSConfig.makeLinuxAlphaSystem('atomic')
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
 
 system.cpu = cpu
 #create the l1/l2 bus
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index 3b1a4f5cf..d7c4bb6e8 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -52,10 +52,28 @@ class L2(BaseCache):
     tgts_per_mshr = 16
     write_buffers = 8
 
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
+    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+
 #cpu
 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ]
 #the system
 system = FSConfig.makeLinuxAlphaSystem('timing')
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
 
 system.cpu = cpus
 #create the l1/l2 bus
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 3f18c6848..96cd27111 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -53,6 +53,19 @@ class L2(BaseCache):
     tgts_per_mshr = 16
     write_buffers = 8
 
+# ---------------------
+# I/O Cache
+# ---------------------
+class IOCache(BaseCache):
+    assoc = 8
+    block_size = 64
+    latency = '50ns'
+    mshrs = 20
+    size = '1kB'
+    tgts_per_mshr = 12
+    mem_side_filter_ranges=[AddrRange(0, Addr.max)]
+    cpu_side_filter_ranges=[AddrRange(0x8000000000, Addr.max)]
+
 #cpu
 cpu = TimingSimpleCPU(cpu_id=0)
 #the system
@@ -61,6 +74,12 @@ system = FSConfig.makeLinuxAlphaSystem('timing')
 system.cpu = cpu
 #create the l1/l2 bus
 system.toL2Bus = Bus()
+system.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
+system.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
+system.iocache = IOCache()
+system.iocache.cpu_side = system.iobus.port
+system.iocache.mem_side = system.membus.port
+
 
 #connect up the l2 cache
 system.l2c = L2(size='4MB', assoc=8)
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index d3a9862e8..1f7fcb065 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -5,7 +5,7 @@ dummy=0
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
+children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 console=/dist/m5/system/binaries/console
@@ -22,8 +22,8 @@ system_type=34
 [system.bridge]
 type=Bridge
 delay=50000
-fix_partial_write_a=false
-fix_partial_write_b=true
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:8589934591
 nack_delay=4000
 req_size_a=16
 req_size_b=16
@@ -65,10 +65,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -103,10 +105,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -171,10 +175,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -209,10 +215,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -295,17 +303,55 @@ clock=1000
 responder_set=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+cpu_side_filter_ranges=549755813888:18446744073709551615
+hash_delay=1
+latency=50000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=0:18446744073709551615
+mshrs=20
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[2]
 
 [system.l2c]
 type=BaseCache
 addr_range=0:18446744073709551615
 assoc=8
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=10000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=92
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -329,7 +375,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[2]
+mem_side=system.membus.port[3]
 
 [system.membus]
 type=Bus
@@ -340,7 +386,7 @@ clock=1000
 responder_set=false
 width=64
 default=system.membus.responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
+port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.responder]
 type=IsaFake
@@ -474,8 +520,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[28]
-dma=system.iobus.port[29]
+config=system.iobus.port[29]
+dma=system.iobus.port[30]
 pio=system.iobus.port[27]
 
 [system.tsunami.ethernet.configdata]
@@ -840,8 +886,8 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
+config=system.iobus.port[31]
+dma=system.iobus.port[32]
 pio=system.iobus.port[26]
 
 [system.tsunami.ide.configdata]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
index 27adebb82..c2aeea3f1 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/console.system.sim_console
@@ -38,7 +38,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
 
Mount-cache hash table entries: 512
 
SMP starting up secondaries.
-
Slave CPU 1 console command START
+
Slave CPU 1 console command START

 SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
 
Brought up 2 CPUs
 
SMP: Total of 2 processors activated (8000.15 BogoMIPS).
@@ -77,7 +77,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
hdb: M5 IDE Disk, ATA DISK drive
 
ide0 at 0x8410-0x8417,0x8422 on irq 31
 
hda: max request size: 128KiB
-
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
+
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
 
hda: cache flushes not supported
 
 hda: hda1
 
hdb: max request size: 128KiB
@@ -104,6 +104,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
All bugs added by David S. Miller <davem@redhat.com>
 
VFS: Mounted root (ext2 filesystem) readonly.
 
Freeing unused kernel memory: 224k freed
-

init started:  BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
-mounting filesystems...
-loading script...
+

init started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary

+mounting filesystems...

+EXT2-fs warning: checktime reached, running e2fsck is recommended
+
loading script...

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
index df780ee45..d9ba4afe5 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1258571                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 256444                       # Number of bytes of host memory used
-host_seconds                                    50.16                       # Real time elapsed on the host
-host_tick_rate                            37289409683                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2271343                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 326380                       # Number of bytes of host memory used
+host_seconds                                    27.79                       # Real time elapsed on the host
+host_tick_rate                            67296173797                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    63125943                       # Number of instructions simulated
 sim_seconds                                  1.870335                       # Number of seconds simulated
@@ -471,6 +471,64 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.iocache.ReadReq_accesses                   175                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses                     175                       # number of ReadReq misses
+system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
+system.iocache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs                     0                       # number of cycles access was blocked
+system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs              0                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.demand_accesses                  41727                       # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency              0                       # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
+system.iocache.demand_hits                          0                       # number of demand (read+write) hits
+system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
+system.iocache.demand_misses                    41727                       # number of demand (read+write) misses
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate                0                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_accesses                 41727                       # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency             0                       # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.iocache.overall_hits                         0                       # number of overall hits
+system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
+system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
+system.iocache.overall_misses                   41727                       # number of overall misses
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate               0                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements                     41695                       # number of replacements
+system.iocache.sampled_refs                     41711                       # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse                     0.435433                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.warmup_cycle              1685787165017                       # Cycle when the warmup percentage was hit.
+system.iocache.writebacks                       41520                       # number of writebacks
 system.l2c.ReadExReq_accesses                  306246                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_misses                    306246                       # number of ReadExReq misses
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
index 563ca3160..85bd66f32 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stderr
@@ -1,5 +1,5 @@
-Listening for system connection on port 3457
+Listening for system connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
 0: system.remote_gdb.listener: listening for remote gdb on port 7001
-0: system.remote_gdb.listener: listening for remote gdb on port 7002
 warn: Entering event queue @ 0.  Starting simulation...
 warn: 97861500: Trying to launch CPU number 1!
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
index 1298154d9..b97e23c2a 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  3 2007 04:02:11
-M5 started Fri Aug  3 04:22:43 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 10 2007 16:03:34
+M5 started Fri Aug 10 16:04:07 2007
+M5 executing on zeep
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 1870335101500 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 3457f5f8f..c2e3afa96 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -5,7 +5,7 @@ dummy=0
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
+children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 console=/dist/m5/system/binaries/console
@@ -22,8 +22,8 @@ system_type=34
 [system.bridge]
 type=Bridge
 delay=50000
-fix_partial_write_a=false
-fix_partial_write_b=true
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:8589934591
 nack_delay=4000
 req_size_a=16
 req_size_b=16
@@ -65,10 +65,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -103,10 +105,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -189,17 +193,55 @@ clock=1000
 responder_set=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+cpu_side_filter_ranges=549755813888:18446744073709551615
+hash_delay=1
+latency=50000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=0:18446744073709551615
+mshrs=20
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[2]
 
 [system.l2c]
 type=BaseCache
 addr_range=0:18446744073709551615
 assoc=8
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=10000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=92
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -223,7 +265,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[2]
+mem_side=system.membus.port[3]
 
 [system.membus]
 type=Bus
@@ -234,7 +276,7 @@ clock=1000
 responder_set=false
 width=64
 default=system.membus.responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
+port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.responder]
 type=IsaFake
@@ -368,8 +410,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[28]
-dma=system.iobus.port[29]
+config=system.iobus.port[29]
+dma=system.iobus.port[30]
 pio=system.iobus.port[27]
 
 [system.tsunami.ethernet.configdata]
@@ -734,8 +776,8 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
+config=system.iobus.port[31]
+dma=system.iobus.port[32]
 pio=system.iobus.port[26]
 
 [system.tsunami.ide.configdata]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
index 5461cc4ab..7930e9e46 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/console.system.sim_console
@@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
hdb: M5 IDE Disk, ATA DISK drive
 
ide0 at 0x8410-0x8417,0x8422 on irq 31
 
hda: max request size: 128KiB
-
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
+
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
 
hda: cache flushes not supported
 
 hda: hda1
 
hdb: max request size: 128KiB
@@ -99,6 +99,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
All bugs added by David S. Miller <davem@redhat.com>
 
VFS: Mounted root (ext2 filesystem) readonly.
 
Freeing unused kernel memory: 224k freed
-

init started:  BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
-mounting filesystems...
-loading script...
+

init started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary

+mounting filesystems...

+EXT2-fs warning: checktime reached, running e2fsck is recommended
+
loading script...

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
index cc91e4c90..a4dd50e83 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/m5stats.txt
@@ -1,9 +1,9 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                1294756                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 255900                       # Number of bytes of host memory used
-host_seconds                                    46.35                       # Real time elapsed on the host
-host_tick_rate                            39449403667                       # Simulator tick rate (ticks/s)
+host_inst_rate                                2322212                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 325356                       # Number of bytes of host memory used
+host_seconds                                    25.84                       # Real time elapsed on the host
+host_tick_rate                            70754225205                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                    60007317                       # Number of instructions simulated
 sim_seconds                                  1.828355                       # Number of seconds simulated
@@ -249,6 +249,64 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
+system.iocache.ReadReq_accesses                   174                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses                     174                       # number of ReadReq misses
+system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
+system.iocache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs                     0                       # number of cycles access was blocked
+system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs              0                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.demand_accesses                  41726                       # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency              0                       # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
+system.iocache.demand_hits                          0                       # number of demand (read+write) hits
+system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
+system.iocache.demand_misses                    41726                       # number of demand (read+write) misses
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate                0                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_accesses                 41726                       # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency             0                       # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency <err: div-0>                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.iocache.overall_hits                         0                       # number of overall hits
+system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
+system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
+system.iocache.overall_misses                   41726                       # number of overall misses
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate               0                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements                     41686                       # number of replacements
+system.iocache.sampled_refs                     41702                       # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse                     1.226223                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.warmup_cycle              1684804097017                       # Cycle when the warmup percentage was hit.
+system.iocache.writebacks                       41512                       # number of writebacks
 system.l2c.ReadExReq_accesses                  304342                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
 system.l2c.ReadExReq_misses                    304342                       # number of ReadExReq misses
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
index 32120d9d6..072cb6c8c 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stderr
@@ -1,3 +1,3 @@
-Listening for system connection on port 3457
-0: system.remote_gdb.listener: listening for remote gdb on port 7001
+Listening for system connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
 warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
index 1f648aea1..00122ad9f 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  3 2007 04:02:11
-M5 started Fri Aug  3 04:21:55 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 10 2007 16:03:34
+M5 started Fri Aug 10 16:03:39 2007
+M5 executing on zeep
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 1828355476000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index bbfd059cd..f2dae72bb 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -5,7 +5,7 @@ dummy=0
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
+children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 console=/dist/m5/system/binaries/console
@@ -22,8 +22,8 @@ system_type=34
 [system.bridge]
 type=Bridge
 delay=50000
-fix_partial_write_a=false
-fix_partial_write_b=true
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:8589934591
 nack_delay=4000
 req_size_a=16
 req_size_b=16
@@ -63,10 +63,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -101,10 +103,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -167,10 +171,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -205,10 +211,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -291,17 +299,55 @@ clock=1000
 responder_set=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+cpu_side_filter_ranges=549755813888:18446744073709551615
+hash_delay=1
+latency=50000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=0:18446744073709551615
+mshrs=20
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[2]
 
 [system.l2c]
 type=BaseCache
 addr_range=0:18446744073709551615
 assoc=8
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=10000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=92
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -325,7 +371,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[2]
+mem_side=system.membus.port[3]
 
 [system.membus]
 type=Bus
@@ -336,7 +382,7 @@ clock=1000
 responder_set=false
 width=64
 default=system.membus.responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
+port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.responder]
 type=IsaFake
@@ -470,8 +516,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[28]
-dma=system.iobus.port[29]
+config=system.iobus.port[29]
+dma=system.iobus.port[30]
 pio=system.iobus.port[27]
 
 [system.tsunami.ethernet.configdata]
@@ -836,8 +882,8 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
+config=system.iobus.port[31]
+dma=system.iobus.port[32]
 pio=system.iobus.port[26]
 
 [system.tsunami.ide.configdata]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
index ceae1faaf..c2aeea3f1 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/console.system.sim_console
@@ -17,8 +17,8 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
unix_boot_mem ends at FFFFFC0000078000 
 
k_argc = 0 
 
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
-
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
 
CallbackFixup 0 18000, t7=FFFFFC000070C000
+
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
 
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
 
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
 
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
@@ -38,7 +38,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Memory: 118784k/131072k available (3314k kernel code, 8952k reserved, 983k data, 224k init)
 
Mount-cache hash table entries: 512
 
SMP starting up secondaries.
-
Slave CPU 1 console command START
+
Slave CPU 1 console command START

 SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb FFFFFC0000018400 my_rpb_phys 18400
 
Brought up 2 CPUs
 
SMP: Total of 2 processors activated (8000.15 BogoMIPS).
@@ -77,7 +77,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
hdb: M5 IDE Disk, ATA DISK drive
 
ide0 at 0x8410-0x8417,0x8422 on irq 31
 
hda: max request size: 128KiB
-
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
+
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
 
hda: cache flushes not supported
 
 hda: hda1
 
hdb: max request size: 128KiB
@@ -104,6 +104,7 @@ SlaveCmd: restart FFFFFC0000310020 FFFFFC0000310020 vptb FFFFFFFE00000000 my_rpb
 
All bugs added by David S. Miller <davem@redhat.com>
 
VFS: Mounted root (ext2 filesystem) readonly.
 
Freeing unused kernel memory: 224k freed
-

init started:  BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
-mounting filesystems...
-loading script...
+

init started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary

+mounting filesystems...

+EXT2-fs warning: checktime reached, running e2fsck is recommended
+
loading script...

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
index b7e78eb06..1f23524ef 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt
@@ -1,92 +1,92 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 608366                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 227884                       # Number of bytes of host memory used
-host_seconds                                   106.58                       # Real time elapsed on the host
-host_tick_rate                            18308931831                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1074925                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 296176                       # Number of bytes of host memory used
+host_seconds                                    60.33                       # Real time elapsed on the host
+host_tick_rate                            32328249055                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    64839479                       # Number of instructions simulated
-sim_seconds                                  1.951367                       # Number of seconds simulated
-sim_ticks                                1951367346000                       # Number of ticks simulated
-system.cpu0.dcache.LoadLockedReq_accesses       150248                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency 10860.561606                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency  9860.561606                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits          136751                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency    146585000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate     0.089831                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses         13497                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    133088000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate     0.089831                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses        13497                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses           7920707                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 13239.029006                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12239.003253                       # average ReadReq mshr miss latency
+sim_insts                                    64849281                       # Number of instructions simulated
+sim_seconds                                  1.950343                       # Number of seconds simulated
+sim_ticks                                1950343222000                       # Number of ticks simulated
+system.cpu0.dcache.LoadLockedReq_accesses       150730                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency 10884.490158                       # average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency  9884.490158                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits          137216                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency    147093000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate     0.089657                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses         13514                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    133579000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate     0.089657                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_misses        13514                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses           7931562                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency 13248.229322                       # average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12248.200096                       # average ReadReq mshr miss latency
 system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits               6328668                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency   21077050500                       # number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate         0.200997                       # miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses             1592039                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency  19484970500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate     0.200997                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses        1592039                       # number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    846944000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses       149727                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency 12266.165876                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 11266.165876                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits           126963                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency    279227000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate     0.152037                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses          22764                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency    256463000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate     0.152037                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses        22764                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses          4824283                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 13877.297001                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 12877.297001                       # average WriteReq mshr miss latency
+system.cpu0.dcache.ReadReq_hits               6340505                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency   21078688000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate         0.200598                       # miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses             1591057                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency  19487584500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate     0.200598                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_misses        1591057                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    849528000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses       150210                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency 12289.709716                       # average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 11289.709716                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits           127577                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency    278153000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate     0.150676                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses          22633                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency    255520000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate     0.150676                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_misses        22633                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses          4827886                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency 13885.285166                       # average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 12885.285166                       # average WriteReq mshr miss latency
 system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits              4508382                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency   4383852000                       # number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate        0.065481                       # miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses             315901                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_miss_latency   4067951000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate     0.065481                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses        315901                       # number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1297859000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_hits              4512456                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency   4379835500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate        0.065335                       # miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses             315430                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_miss_latency   4064405500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate     0.065335                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses        315430                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1305489000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu0.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu0.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs                  6.121232                       # Average number of references to valid blocks.
+system.cpu0.dcache.avg_refs                  6.135326                       # Average number of references to valid blocks.
 system.cpu0.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.demand_accesses           12744990                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 13344.708167                       # average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 12344.686678                       # average overall mshr miss latency
-system.cpu0.dcache.demand_hits               10837050                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency    25460902500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate          0.149701                       # miss rate for demand accesses
-system.cpu0.dcache.demand_misses              1907940                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_accesses           12759448                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 13353.630788                       # average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 12353.606398                       # average overall mshr miss latency
+system.cpu0.dcache.demand_hits               10852961                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency    25458523500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate          0.149418                       # miss rate for demand accesses
+system.cpu0.dcache.demand_misses              1906487                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency  23552921500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate     0.149701                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses         1907940                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_miss_latency  23551990000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate     0.149418                       # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses         1906487                       # number of demand (read+write) MSHR misses
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses          12744990                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 13344.708167                       # average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 12344.686678                       # average overall mshr miss latency
+system.cpu0.dcache.overall_accesses          12759448                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 13353.630788                       # average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 12353.606398                       # average overall mshr miss latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits              10837050                       # number of overall hits
-system.cpu0.dcache.overall_miss_latency   25460902500                       # number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate         0.149701                       # miss rate for overall accesses
-system.cpu0.dcache.overall_misses             1907940                       # number of overall misses
+system.cpu0.dcache.overall_hits              10852961                       # number of overall hits
+system.cpu0.dcache.overall_miss_latency   25458523500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate         0.149418                       # miss rate for overall accesses
+system.cpu0.dcache.overall_misses             1906487                       # number of overall misses
 system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency  23552921500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate     0.149701                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses        1907940                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency   2144803000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_miss_latency  23551990000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate     0.149418                       # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses        1906487                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency   2155017000                       # number of overall MSHR uncacheable cycles
 system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -97,69 +97,69 @@ system.cpu0.dcache.prefetcher.num_hwpf_issued            0
 system.cpu0.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu0.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu0.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.dcache.replacements               1829212                       # number of replacements
-system.cpu0.dcache.sampled_refs               1829724                       # Sample count of references to valid blocks.
+system.cpu0.dcache.replacements               1827780                       # number of replacements
+system.cpu0.dcache.sampled_refs               1828292                       # Sample count of references to valid blocks.
 system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.tagsinuse               497.900810                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                11200165                       # Total number of references to valid blocks.
+system.cpu0.dcache.tagsinuse               497.873184                       # Cycle average of tags in use
+system.cpu0.dcache.total_refs                11217167                       # Total number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              58293000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.writebacks                  322933                       # number of writebacks
-system.cpu0.dtb.accesses                       725071                       # DTB accesses
-system.cpu0.dtb.acv                               305                       # DTB access violations
-system.cpu0.dtb.hits                         13035385                       # DTB hits
-system.cpu0.dtb.misses                           8682                       # DTB misses
-system.cpu0.dtb.read_accesses                  527638                       # DTB read accesses
-system.cpu0.dtb.read_acv                          184                       # DTB read access violations
-system.cpu0.dtb.read_hits                     8058540                       # DTB read hits
-system.cpu0.dtb.read_misses                      7858                       # DTB read misses
-system.cpu0.dtb.write_accesses                 197433                       # DTB write accesses
-system.cpu0.dtb.write_acv                         121                       # DTB write access violations
-system.cpu0.dtb.write_hits                    4976845                       # DTB write hits
-system.cpu0.dtb.write_misses                      824                       # DTB write misses
-system.cpu0.icache.ReadReq_accesses          51081135                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_avg_miss_latency 12048.344860                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11047.036239                       # average ReadReq mshr miss latency
-system.cpu0.icache.ReadReq_hits              50399501                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_miss_latency    8212561500                       # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_rate         0.013344                       # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_misses              681634                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_mshr_miss_latency   7530035500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate     0.013344                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_misses         681634                       # number of ReadReq MSHR misses
+system.cpu0.dcache.writebacks                  322471                       # number of writebacks
+system.cpu0.dtb.accesses                       719860                       # DTB accesses
+system.cpu0.dtb.acv                               289                       # DTB access violations
+system.cpu0.dtb.hits                         13051211                       # DTB hits
+system.cpu0.dtb.misses                           8485                       # DTB misses
+system.cpu0.dtb.read_accesses                  524201                       # DTB read accesses
+system.cpu0.dtb.read_acv                          174                       # DTB read access violations
+system.cpu0.dtb.read_hits                     8070179                       # DTB read hits
+system.cpu0.dtb.read_misses                      7687                       # DTB read misses
+system.cpu0.dtb.write_accesses                 195659                       # DTB write accesses
+system.cpu0.dtb.write_acv                         115                       # DTB write access violations
+system.cpu0.dtb.write_hits                    4981032                       # DTB write hits
+system.cpu0.dtb.write_misses                      798                       # DTB write misses
+system.cpu0.icache.ReadReq_accesses          51129549                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_avg_miss_latency 12049.200476                       # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11047.896012                       # average ReadReq mshr miss latency
+system.cpu0.icache.ReadReq_hits              50446893                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_miss_latency    8225459000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_rate         0.013351                       # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_misses              682656                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_mshr_miss_latency   7541912500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate     0.013351                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_mshr_misses         682656                       # number of ReadReq MSHR misses
 system.cpu0.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu0.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_refs                 73.953888                       # Average number of references to valid blocks.
+system.cpu0.icache.avg_refs                 73.909880                       # Average number of references to valid blocks.
 system.cpu0.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.demand_accesses           51081135                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_avg_miss_latency 12048.344860                       # average overall miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11047.036239                       # average overall mshr miss latency
-system.cpu0.icache.demand_hits               50399501                       # number of demand (read+write) hits
-system.cpu0.icache.demand_miss_latency     8212561500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_rate          0.013344                       # miss rate for demand accesses
-system.cpu0.icache.demand_misses               681634                       # number of demand (read+write) misses
+system.cpu0.icache.demand_accesses           51129549                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_avg_miss_latency 12049.200476                       # average overall miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency 11047.896012                       # average overall mshr miss latency
+system.cpu0.icache.demand_hits               50446893                       # number of demand (read+write) hits
+system.cpu0.icache.demand_miss_latency     8225459000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_rate          0.013351                       # miss rate for demand accesses
+system.cpu0.icache.demand_misses               682656                       # number of demand (read+write) misses
 system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_miss_latency   7530035500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_rate     0.013344                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_misses          681634                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_miss_latency   7541912500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_rate     0.013351                       # mshr miss rate for demand accesses
+system.cpu0.icache.demand_mshr_misses          682656                       # number of demand (read+write) MSHR misses
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.icache.overall_accesses          51081135                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_avg_miss_latency 12048.344860                       # average overall miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11047.036239                       # average overall mshr miss latency
+system.cpu0.icache.overall_accesses          51129549                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_avg_miss_latency 12049.200476                       # average overall miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency 11047.896012                       # average overall mshr miss latency
 system.cpu0.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu0.icache.overall_hits              50399501                       # number of overall hits
-system.cpu0.icache.overall_miss_latency    8212561500                       # number of overall miss cycles
-system.cpu0.icache.overall_miss_rate         0.013344                       # miss rate for overall accesses
-system.cpu0.icache.overall_misses              681634                       # number of overall misses
+system.cpu0.icache.overall_hits              50446893                       # number of overall hits
+system.cpu0.icache.overall_miss_latency    8225459000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_rate         0.013351                       # miss rate for overall accesses
+system.cpu0.icache.overall_misses              682656                       # number of overall misses
 system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.icache.overall_mshr_miss_latency   7530035500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_rate     0.013344                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_misses         681634                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_miss_latency   7541912500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_rate     0.013351                       # mshr miss rate for overall accesses
+system.cpu0.icache.overall_mshr_misses         682656                       # number of overall MSHR misses
 system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu0.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -171,190 +171,190 @@ system.cpu0.icache.prefetcher.num_hwpf_issued            0
 system.cpu0.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu0.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu0.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.icache.replacements                680987                       # number of replacements
-system.cpu0.icache.sampled_refs                681499                       # Sample count of references to valid blocks.
+system.cpu0.icache.replacements                682034                       # number of replacements
+system.cpu0.icache.sampled_refs                682546                       # Sample count of references to valid blocks.
 system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.tagsinuse               508.821605                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                50399501                       # Total number of references to valid blocks.
+system.cpu0.icache.tagsinuse               508.823840                       # Cycle average of tags in use
+system.cpu0.icache.total_refs                50446893                       # Total number of references to valid blocks.
 system.cpu0.icache.warmup_cycle           35300494000                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.writebacks                       0                       # number of writebacks
-system.cpu0.idle_fraction                    0.949890                       # Percentage of idle cycles
-system.cpu0.itb.accesses                      3593148                       # ITB accesses
-system.cpu0.itb.acv                               161                       # ITB acv
-system.cpu0.itb.hits                          3589202                       # ITB hits
-system.cpu0.itb.misses                           3946                       # ITB misses
-system.cpu0.kern.callpal                       145952                       # number of callpals executed
+system.cpu0.idle_fraction                    0.949821                       # Percentage of idle cycles
+system.cpu0.itb.accesses                      3574000                       # ITB accesses
+system.cpu0.itb.acv                               143                       # ITB acv
+system.cpu0.itb.hits                          3570159                       # ITB hits
+system.cpu0.itb.misses                           3841                       # ITB misses
+system.cpu0.kern.callpal                       146588                       # number of callpals executed
 system.cpu0.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu0.kern.callpal_wripir                   536      0.37%      0.37% # number of callpals executed
-system.cpu0.kern.callpal_wrmces                     1      0.00%      0.37% # number of callpals executed
-system.cpu0.kern.callpal_wrfen                      1      0.00%      0.37% # number of callpals executed
+system.cpu0.kern.callpal_wripir                   532      0.36%      0.36% # number of callpals executed
+system.cpu0.kern.callpal_wrmces                     1      0.00%      0.36% # number of callpals executed
+system.cpu0.kern.callpal_wrfen                      1      0.00%      0.36% # number of callpals executed
 system.cpu0.kern.callpal_wrvptptr                   1      0.00%      0.37% # number of callpals executed
-system.cpu0.kern.callpal_swpctx                  3014      2.07%      2.44% # number of callpals executed
-system.cpu0.kern.callpal_tbi                       46      0.03%      2.47% # number of callpals executed
-system.cpu0.kern.callpal_wrent                      7      0.00%      2.47% # number of callpals executed
-system.cpu0.kern.callpal_swpipl                131018     89.77%     92.24% # number of callpals executed
-system.cpu0.kern.callpal_rdps                    6493      4.45%     96.69% # number of callpals executed
-system.cpu0.kern.callpal_wrkgp                      1      0.00%     96.69% # number of callpals executed
-system.cpu0.kern.callpal_wrusp                      4      0.00%     96.69% # number of callpals executed
-system.cpu0.kern.callpal_rdusp                      8      0.01%     96.70% # number of callpals executed
-system.cpu0.kern.callpal_whami                      2      0.00%     96.70% # number of callpals executed
-system.cpu0.kern.callpal_rti                     4302      2.95%     99.65% # number of callpals executed
-system.cpu0.kern.callpal_callsys                  368      0.25%     99.90% # number of callpals executed
+system.cpu0.kern.callpal_swpctx                  2987      2.04%      2.40% # number of callpals executed
+system.cpu0.kern.callpal_tbi                       44      0.03%      2.43% # number of callpals executed
+system.cpu0.kern.callpal_wrent                      7      0.00%      2.44% # number of callpals executed
+system.cpu0.kern.callpal_swpipl                131596     89.77%     92.21% # number of callpals executed
+system.cpu0.kern.callpal_rdps                    6643      4.53%     96.74% # number of callpals executed
+system.cpu0.kern.callpal_wrkgp                      1      0.00%     96.74% # number of callpals executed
+system.cpu0.kern.callpal_wrusp                      4      0.00%     96.75% # number of callpals executed
+system.cpu0.kern.callpal_rdusp                      7      0.00%     96.75% # number of callpals executed
+system.cpu0.kern.callpal_whami                      2      0.00%     96.75% # number of callpals executed
+system.cpu0.kern.callpal_rti                     4256      2.90%     99.66% # number of callpals executed
+system.cpu0.kern.callpal_callsys                  356      0.24%     99.90% # number of callpals executed
 system.cpu0.kern.callpal_imb                      149      0.10%    100.00% # number of callpals executed
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.hwrei                    161590                       # number of hwrei instructions executed
-system.cpu0.kern.inst.quiesce                    6598                       # number of quiesce instructions executed
-system.cpu0.kern.ipl_count                     137863                       # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_0                    55298     40.11%     40.11% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_21                     131      0.10%     40.21% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_22                    1969      1.43%     41.63% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_30                     442      0.32%     41.95% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count_31                   80023     58.05%    100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_good                      111708                       # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_0                     54804     49.06%     49.06% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.inst.hwrei                    161890                       # number of hwrei instructions executed
+system.cpu0.kern.inst.quiesce                    6605                       # number of quiesce instructions executed
+system.cpu0.kern.ipl_count                     138395                       # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_0                    55551     40.14%     40.14% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_21                     131      0.09%     40.23% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_22                    1968      1.42%     41.66% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_30                     443      0.32%     41.98% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count_31                   80302     58.02%    100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_good                      112213                       # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_0                     55057     49.06%     49.06% # number of times we switched to this ipl from a different ipl
 system.cpu0.kern.ipl_good_21                      131      0.12%     49.18% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_22                     1969      1.76%     50.94% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_30                      442      0.40%     51.34% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good_31                    54362     48.66%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks               1951366621000                       # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_0             1898503749000     97.29%     97.29% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_21                76310500      0.00%     97.29% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_22               547835000      0.03%     97.32% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_30               278789500      0.01%     97.34% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks_31             51959937000      2.66%    100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_used_0                  0.991067                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_good_22                     1968      1.75%     50.94% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_30                      443      0.39%     51.33% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good_31                    54614     48.67%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks               1950342497000                       # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_0             1897380648000     97.28%     97.28% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_21                76995000      0.00%     97.29% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_22               547402000      0.03%     97.32% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_30               279389000      0.01%     97.33% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks_31             52058063000      2.67%    100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_used_0                  0.991107                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_21                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu0.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used_31                 0.679330                       # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.mode_good_kernel                1275                      
-system.cpu0.kern.mode_good_user                  1276                      
+system.cpu0.kern.ipl_used_31                 0.680108                       # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.mode_good_kernel                1230                      
+system.cpu0.kern.mode_good_user                  1231                      
 system.cpu0.kern.mode_good_idle                     0                      
-system.cpu0.kern.mode_switch_kernel              6846                       # number of protection mode switches
-system.cpu0.kern.mode_switch_user                1276                       # number of protection mode switches
+system.cpu0.kern.mode_switch_kernel              6774                       # number of protection mode switches
+system.cpu0.kern.mode_switch_user                1231                       # number of protection mode switches
 system.cpu0.kern.mode_switch_idle                   0                       # number of protection mode switches
 system.cpu0.kern.mode_switch_good        <err: div-0>                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good_kernel     0.186240                       # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good_kernel     0.181577                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
 system.cpu0.kern.mode_switch_good_idle   <err: div-0>                       # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks_kernel       1948118613000     99.83%     99.83% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks_user           3248006000      0.17%    100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_kernel       1947142058000     99.84%     99.84% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks_user           3200437000      0.16%    100.00% # number of ticks spent at the given mode
 system.cpu0.kern.mode_ticks_idle                    0      0.00%    100.00% # number of ticks spent at the given mode
-system.cpu0.kern.swap_context                    3015                       # number of times the context was actually changed
-system.cpu0.kern.syscall                          228                       # number of syscalls executed
-system.cpu0.kern.syscall_2                          7      3.07%      3.07% # number of syscalls executed
-system.cpu0.kern.syscall_3                         19      8.33%     11.40% # number of syscalls executed
-system.cpu0.kern.syscall_4                          3      1.32%     12.72% # number of syscalls executed
-system.cpu0.kern.syscall_6                         31     13.60%     26.32% # number of syscalls executed
-system.cpu0.kern.syscall_12                         1      0.44%     26.75% # number of syscalls executed
-system.cpu0.kern.syscall_15                         1      0.44%     27.19% # number of syscalls executed
-system.cpu0.kern.syscall_17                        10      4.39%     31.58% # number of syscalls executed
-system.cpu0.kern.syscall_19                         6      2.63%     34.21% # number of syscalls executed
-system.cpu0.kern.syscall_20                         4      1.75%     35.96% # number of syscalls executed
-system.cpu0.kern.syscall_23                         2      0.88%     36.84% # number of syscalls executed
-system.cpu0.kern.syscall_24                         4      1.75%     38.60% # number of syscalls executed
-system.cpu0.kern.syscall_33                         8      3.51%     42.11% # number of syscalls executed
-system.cpu0.kern.syscall_41                         2      0.88%     42.98% # number of syscalls executed
-system.cpu0.kern.syscall_45                        39     17.11%     60.09% # number of syscalls executed
-system.cpu0.kern.syscall_47                         4      1.75%     61.84% # number of syscalls executed
-system.cpu0.kern.syscall_48                         8      3.51%     65.35% # number of syscalls executed
-system.cpu0.kern.syscall_54                         9      3.95%     69.30% # number of syscalls executed
-system.cpu0.kern.syscall_58                         1      0.44%     69.74% # number of syscalls executed
-system.cpu0.kern.syscall_59                         6      2.63%     72.37% # number of syscalls executed
-system.cpu0.kern.syscall_71                        32     14.04%     86.40% # number of syscalls executed
-system.cpu0.kern.syscall_73                         3      1.32%     87.72% # number of syscalls executed
-system.cpu0.kern.syscall_74                         9      3.95%     91.67% # number of syscalls executed
-system.cpu0.kern.syscall_87                         1      0.44%     92.11% # number of syscalls executed
-system.cpu0.kern.syscall_90                         2      0.88%     92.98% # number of syscalls executed
-system.cpu0.kern.syscall_92                         7      3.07%     96.05% # number of syscalls executed
-system.cpu0.kern.syscall_97                         2      0.88%     96.93% # number of syscalls executed
-system.cpu0.kern.syscall_98                         2      0.88%     97.81% # number of syscalls executed
-system.cpu0.kern.syscall_132                        2      0.88%     98.68% # number of syscalls executed
-system.cpu0.kern.syscall_144                        1      0.44%     99.12% # number of syscalls executed
-system.cpu0.kern.syscall_147                        2      0.88%    100.00% # number of syscalls executed
-system.cpu0.not_idle_fraction                0.050110                       # Percentage of non-idle cycles
-system.cpu0.numCycles                    1951367346000                       # number of cpu cycles simulated
-system.cpu0.num_insts                        51081134                       # Number of instructions executed
-system.cpu0.num_refs                         13268864                       # Number of memory references
-system.cpu1.dcache.LoadLockedReq_accesses        61056                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency  9095.192614                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  8095.192614                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_hits           51633                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_miss_latency     85704000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_rate     0.154334                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_misses          9423                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     76281000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate     0.154334                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_misses         9423                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.ReadReq_accesses           2457845                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_avg_miss_latency 11653.965886                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10653.909138                       # average ReadReq mshr miss latency
+system.cpu0.kern.swap_context                    2988                       # number of times the context was actually changed
+system.cpu0.kern.syscall                          224                       # number of syscalls executed
+system.cpu0.kern.syscall_2                          6      2.68%      2.68% # number of syscalls executed
+system.cpu0.kern.syscall_3                         19      8.48%     11.16% # number of syscalls executed
+system.cpu0.kern.syscall_4                          3      1.34%     12.50% # number of syscalls executed
+system.cpu0.kern.syscall_6                         30     13.39%     25.89% # number of syscalls executed
+system.cpu0.kern.syscall_12                         1      0.45%     26.34% # number of syscalls executed
+system.cpu0.kern.syscall_15                         1      0.45%     26.79% # number of syscalls executed
+system.cpu0.kern.syscall_17                        10      4.46%     31.25% # number of syscalls executed
+system.cpu0.kern.syscall_19                         6      2.68%     33.93% # number of syscalls executed
+system.cpu0.kern.syscall_20                         4      1.79%     35.71% # number of syscalls executed
+system.cpu0.kern.syscall_23                         2      0.89%     36.61% # number of syscalls executed
+system.cpu0.kern.syscall_24                         4      1.79%     38.39% # number of syscalls executed
+system.cpu0.kern.syscall_33                         8      3.57%     41.96% # number of syscalls executed
+system.cpu0.kern.syscall_41                         2      0.89%     42.86% # number of syscalls executed
+system.cpu0.kern.syscall_45                        39     17.41%     60.27% # number of syscalls executed
+system.cpu0.kern.syscall_47                         4      1.79%     62.05% # number of syscalls executed
+system.cpu0.kern.syscall_48                         7      3.12%     65.18% # number of syscalls executed
+system.cpu0.kern.syscall_54                         9      4.02%     69.20% # number of syscalls executed
+system.cpu0.kern.syscall_58                         1      0.45%     69.64% # number of syscalls executed
+system.cpu0.kern.syscall_59                         5      2.23%     71.88% # number of syscalls executed
+system.cpu0.kern.syscall_71                        32     14.29%     86.16% # number of syscalls executed
+system.cpu0.kern.syscall_73                         3      1.34%     87.50% # number of syscalls executed
+system.cpu0.kern.syscall_74                         9      4.02%     91.52% # number of syscalls executed
+system.cpu0.kern.syscall_87                         1      0.45%     91.96% # number of syscalls executed
+system.cpu0.kern.syscall_90                         2      0.89%     92.86% # number of syscalls executed
+system.cpu0.kern.syscall_92                         7      3.12%     95.98% # number of syscalls executed
+system.cpu0.kern.syscall_97                         2      0.89%     96.87% # number of syscalls executed
+system.cpu0.kern.syscall_98                         2      0.89%     97.77% # number of syscalls executed
+system.cpu0.kern.syscall_132                        2      0.89%     98.66% # number of syscalls executed
+system.cpu0.kern.syscall_144                        1      0.45%     99.11% # number of syscalls executed
+system.cpu0.kern.syscall_147                        2      0.89%    100.00% # number of syscalls executed
+system.cpu0.not_idle_fraction                0.050179                       # Percentage of non-idle cycles
+system.cpu0.numCycles                    1950343222000                       # number of cpu cycles simulated
+system.cpu0.num_insts                        51129548                       # Number of instructions executed
+system.cpu0.num_refs                         13284144                       # Number of memory references
+system.cpu1.dcache.LoadLockedReq_accesses        60655                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency  9128.994709                       # average LoadLockedReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  8128.994709                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_hits           51205                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_miss_latency     86269000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_rate     0.155799                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_misses          9450                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     76819000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate     0.155799                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_misses         9450                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.ReadReq_accesses           2449421                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_avg_miss_latency 11681.277239                       # average ReadReq miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 10681.237034                       # average ReadReq mshr miss latency
 system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.ReadReq_hits               2334493                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_miss_latency    1437540000                       # number of ReadReq miss cycles
-system.cpu1.dcache.ReadReq_miss_rate         0.050187                       # miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_misses              123352                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency   1314181000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate     0.050187                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_misses         123352                       # number of ReadReq MSHR misses
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     16729500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.StoreCondReq_accesses        60551                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_avg_miss_latency 10960.125479                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency  9960.125479                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_hits            46206                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_miss_latency    157223000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_rate     0.236908                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_misses          14345                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency    142878000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate     0.236908                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_misses        14345                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.WriteReq_accesses          1792743                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_avg_miss_latency 13398.121192                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 12398.121192                       # average WriteReq mshr miss latency
+system.cpu1.dcache.ReadReq_hits               2325059                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_miss_latency    1452707000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_rate         0.050772                       # miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_misses              124362                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency   1328340000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate     0.050772                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_misses         124362                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     14269500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.StoreCondReq_accesses        60151                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_avg_miss_latency 11012.226290                       # average StoreCondReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 10012.226290                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_hits            45674                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_miss_latency    159424000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_rate     0.240678                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_misses          14477                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency    144947000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate     0.240678                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_misses        14477                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.WriteReq_accesses          1790109                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_avg_miss_latency 13411.570283                       # average WriteReq miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 12411.570283                       # average WriteReq mshr miss latency
 system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_hits              1700344                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_miss_latency   1237973000                       # number of WriteReq miss cycles
-system.cpu1.dcache.WriteReq_miss_rate        0.051541                       # miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_misses              92399                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_mshr_miss_latency   1145574000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_rate     0.051541                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_misses         92399                       # number of WriteReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    421374000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_hits              1696922                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_miss_latency   1249784000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_rate        0.052057                       # miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_misses              93187                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_mshr_miss_latency   1156597000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_rate     0.052057                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_misses         93187                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    412881500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu1.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu1.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_refs                 23.577992                       # Average number of references to valid blocks.
+system.cpu1.dcache.avg_refs                 23.244686                       # Average number of references to valid blocks.
 system.cpu1.dcache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.demand_accesses            4250588                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_avg_miss_latency 12400.929776                       # average overall miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 11400.897331                       # average overall mshr miss latency
-system.cpu1.dcache.demand_hits                4034837                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_miss_latency     2675513000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.demand_miss_rate          0.050758                       # miss rate for demand accesses
-system.cpu1.dcache.demand_misses               215751                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_accesses            4239530                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_avg_miss_latency 12422.447357                       # average overall miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency 11422.424373                       # average overall mshr miss latency
+system.cpu1.dcache.demand_hits                4021981                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_miss_latency     2702491000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_rate          0.051314                       # miss rate for demand accesses
+system.cpu1.dcache.demand_misses               217549                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.demand_mshr_miss_latency   2459755000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_rate     0.050758                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_misses          215751                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_miss_latency   2484937000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_rate     0.051314                       # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_misses          217549                       # number of demand (read+write) MSHR misses
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.overall_accesses           4250588                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_avg_miss_latency 12400.929776                       # average overall miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 11400.897331                       # average overall mshr miss latency
+system.cpu1.dcache.overall_accesses           4239530                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_avg_miss_latency 12422.447357                       # average overall miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency 11422.424373                       # average overall mshr miss latency
 system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.overall_hits               4034837                       # number of overall hits
-system.cpu1.dcache.overall_miss_latency    2675513000                       # number of overall miss cycles
-system.cpu1.dcache.overall_miss_rate         0.050758                       # miss rate for overall accesses
-system.cpu1.dcache.overall_misses              215751                       # number of overall misses
+system.cpu1.dcache.overall_hits               4021981                       # number of overall hits
+system.cpu1.dcache.overall_miss_latency    2702491000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_rate         0.051314                       # miss rate for overall accesses
+system.cpu1.dcache.overall_misses              217549                       # number of overall misses
 system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.dcache.overall_mshr_miss_latency   2459755000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_rate     0.050758                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_misses         215751                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_latency    438103500                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_miss_latency   2484937000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_rate     0.051314                       # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_misses         217549                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_uncacheable_latency    427151000                       # number of overall MSHR uncacheable cycles
 system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu1.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu1.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -365,69 +365,69 @@ system.cpu1.dcache.prefetcher.num_hwpf_issued            0
 system.cpu1.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu1.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu1.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.dcache.replacements                176474                       # number of replacements
-system.cpu1.dcache.sampled_refs                176909                       # Sample count of references to valid blocks.
+system.cpu1.dcache.replacements                178566                       # number of replacements
+system.cpu1.dcache.sampled_refs                178968                       # Sample count of references to valid blocks.
 system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.tagsinuse               471.274557                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 4171159                       # Total number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle          1917859097000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.writebacks                   93260                       # number of writebacks
-system.cpu1.dtb.accesses                       296718                       # DTB accesses
-system.cpu1.dtb.acv                                62                       # DTB access violations
-system.cpu1.dtb.hits                          4358656                       # DTB hits
-system.cpu1.dtb.misses                           2867                       # DTB misses
-system.cpu1.dtb.read_accesses                  201817                       # DTB read accesses
-system.cpu1.dtb.read_acv                           26                       # DTB read access violations
-system.cpu1.dtb.read_hits                     2507309                       # DTB read hits
-system.cpu1.dtb.read_misses                      2546                       # DTB read misses
-system.cpu1.dtb.write_accesses                  94901                       # DTB write accesses
-system.cpu1.dtb.write_acv                          36                       # DTB write access violations
-system.cpu1.dtb.write_hits                    1851347                       # DTB write hits
-system.cpu1.dtb.write_misses                      321                       # DTB write misses
-system.cpu1.icache.ReadReq_accesses          13758345                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_avg_miss_latency 12026.498126                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11026.342473                       # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_hits              13421057                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_miss_latency    4056393500                       # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_rate         0.024515                       # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_misses              337288                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_mshr_miss_latency   3719053000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate     0.024515                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_misses         337288                       # number of ReadReq MSHR misses
+system.cpu1.dcache.tagsinuse               471.348087                       # Cycle average of tags in use
+system.cpu1.dcache.total_refs                 4160055                       # Total number of references to valid blocks.
+system.cpu1.dcache.warmup_cycle          1934175560000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.writebacks                   94428                       # number of writebacks
+system.cpu1.dtb.accesses                       302878                       # DTB accesses
+system.cpu1.dtb.acv                                84                       # DTB access violations
+system.cpu1.dtb.hits                          4346335                       # DTB hits
+system.cpu1.dtb.misses                           3106                       # DTB misses
+system.cpu1.dtb.read_accesses                  205838                       # DTB read accesses
+system.cpu1.dtb.read_acv                           36                       # DTB read access violations
+system.cpu1.dtb.read_hits                     2498134                       # DTB read hits
+system.cpu1.dtb.read_misses                      2750                       # DTB read misses
+system.cpu1.dtb.write_accesses                  97040                       # DTB write accesses
+system.cpu1.dtb.write_acv                          48                       # DTB write access violations
+system.cpu1.dtb.write_hits                    1848201                       # DTB write hits
+system.cpu1.dtb.write_misses                      356                       # DTB write misses
+system.cpu1.icache.ReadReq_accesses          13719733                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_avg_miss_latency 12024.874815                       # average ReadReq miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11024.732219                       # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_hits              13386625                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_miss_latency    4005582000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_rate         0.024279                       # miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_misses              333108                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_mshr_miss_latency   3672426500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate     0.024279                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.ReadReq_mshr_misses         333108                       # number of ReadReq MSHR misses
 system.cpu1.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu1.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_refs                 39.794511                       # Average number of references to valid blocks.
+system.cpu1.icache.avg_refs                 40.190058                       # Average number of references to valid blocks.
 system.cpu1.icache.blocked_no_mshrs                 0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_no_targets               0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.demand_accesses           13758345                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_avg_miss_latency 12026.498126                       # average overall miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11026.342473                       # average overall mshr miss latency
-system.cpu1.icache.demand_hits               13421057                       # number of demand (read+write) hits
-system.cpu1.icache.demand_miss_latency     4056393500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_rate          0.024515                       # miss rate for demand accesses
-system.cpu1.icache.demand_misses               337288                       # number of demand (read+write) misses
+system.cpu1.icache.demand_accesses           13719733                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_avg_miss_latency 12024.874815                       # average overall miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency 11024.732219                       # average overall mshr miss latency
+system.cpu1.icache.demand_hits               13386625                       # number of demand (read+write) hits
+system.cpu1.icache.demand_miss_latency     4005582000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_rate          0.024279                       # miss rate for demand accesses
+system.cpu1.icache.demand_misses               333108                       # number of demand (read+write) misses
 system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.demand_mshr_miss_latency   3719053000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_rate     0.024515                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_misses          337288                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_miss_latency   3672426500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_rate     0.024279                       # mshr miss rate for demand accesses
+system.cpu1.icache.demand_mshr_misses          333108                       # number of demand (read+write) MSHR misses
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.icache.overall_accesses          13758345                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_avg_miss_latency 12026.498126                       # average overall miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11026.342473                       # average overall mshr miss latency
+system.cpu1.icache.overall_accesses          13719733                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_avg_miss_latency 12024.874815                       # average overall miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency 11024.732219                       # average overall mshr miss latency
 system.cpu1.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu1.icache.overall_hits              13421057                       # number of overall hits
-system.cpu1.icache.overall_miss_latency    4056393500                       # number of overall miss cycles
-system.cpu1.icache.overall_miss_rate         0.024515                       # miss rate for overall accesses
-system.cpu1.icache.overall_misses              337288                       # number of overall misses
+system.cpu1.icache.overall_hits              13386625                       # number of overall hits
+system.cpu1.icache.overall_miss_latency    4005582000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_rate         0.024279                       # miss rate for overall accesses
+system.cpu1.icache.overall_misses              333108                       # number of overall misses
 system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.icache.overall_mshr_miss_latency   3719053000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_rate     0.024515                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_misses         337288                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_miss_latency   3672426500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_rate     0.024279                       # mshr miss rate for overall accesses
+system.cpu1.icache.overall_mshr_misses         333108                       # number of overall MSHR misses
 system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu1.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -439,98 +439,98 @@ system.cpu1.icache.prefetcher.num_hwpf_issued            0
 system.cpu1.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu1.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu1.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.icache.replacements                336747                       # number of replacements
-system.cpu1.icache.sampled_refs                337259                       # Sample count of references to valid blocks.
+system.cpu1.icache.replacements                332571                       # number of replacements
+system.cpu1.icache.sampled_refs                333083                       # Sample count of references to valid blocks.
 system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.tagsinuse               445.859240                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                13421057                       # Total number of references to valid blocks.
-system.cpu1.icache.warmup_cycle          1946103109000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tagsinuse               445.823850                       # Cycle average of tags in use
+system.cpu1.icache.total_refs                13386625                       # Total number of references to valid blocks.
+system.cpu1.icache.warmup_cycle          1934417088000                       # Cycle when the warmup percentage was hit.
 system.cpu1.icache.writebacks                       0                       # number of writebacks
-system.cpu1.idle_fraction                    0.987201                       # Percentage of idle cycles
-system.cpu1.itb.accesses                      1878768                       # ITB accesses
-system.cpu1.itb.acv                                23                       # ITB acv
-system.cpu1.itb.hits                          1877648                       # ITB hits
-system.cpu1.itb.misses                           1120                       # ITB misses
-system.cpu1.kern.callpal                        75334                       # number of callpals executed
+system.cpu1.idle_fraction                    0.987236                       # Percentage of idle cycles
+system.cpu1.itb.accesses                      1902426                       # ITB accesses
+system.cpu1.itb.acv                                41                       # ITB acv
+system.cpu1.itb.hits                          1901180                       # ITB hits
+system.cpu1.itb.misses                           1246                       # ITB misses
+system.cpu1.kern.callpal                        74762                       # number of callpals executed
 system.cpu1.kern.callpal_cserve                     1      0.00%      0.00% # number of callpals executed
-system.cpu1.kern.callpal_wripir                   442      0.59%      0.59% # number of callpals executed
-system.cpu1.kern.callpal_wrmces                     1      0.00%      0.59% # number of callpals executed
-system.cpu1.kern.callpal_wrfen                      1      0.00%      0.59% # number of callpals executed
-system.cpu1.kern.callpal_swpctx                  2091      2.78%      3.37% # number of callpals executed
-system.cpu1.kern.callpal_tbi                        7      0.01%      3.38% # number of callpals executed
-system.cpu1.kern.callpal_wrent                      7      0.01%      3.38% # number of callpals executed
-system.cpu1.kern.callpal_swpipl                 66409     88.15%     91.54% # number of callpals executed
-system.cpu1.kern.callpal_rdps                    2344      3.11%     94.65% # number of callpals executed
-system.cpu1.kern.callpal_wrkgp                      1      0.00%     94.65% # number of callpals executed
-system.cpu1.kern.callpal_wrusp                      3      0.00%     94.65% # number of callpals executed
-system.cpu1.kern.callpal_rdusp                      1      0.00%     94.66% # number of callpals executed
-system.cpu1.kern.callpal_whami                      3      0.00%     94.66% # number of callpals executed
-system.cpu1.kern.callpal_rti                     3844      5.10%     99.76% # number of callpals executed
-system.cpu1.kern.callpal_callsys                  147      0.20%     99.96% # number of callpals executed
+system.cpu1.kern.callpal_wripir                   443      0.59%      0.59% # number of callpals executed
+system.cpu1.kern.callpal_wrmces                     1      0.00%      0.60% # number of callpals executed
+system.cpu1.kern.callpal_wrfen                      1      0.00%      0.60% # number of callpals executed
+system.cpu1.kern.callpal_swpctx                  2123      2.84%      3.44% # number of callpals executed
+system.cpu1.kern.callpal_tbi                       10      0.01%      3.45% # number of callpals executed
+system.cpu1.kern.callpal_wrent                      7      0.01%      3.46% # number of callpals executed
+system.cpu1.kern.callpal_swpipl                 65888     88.13%     91.59% # number of callpals executed
+system.cpu1.kern.callpal_rdps                    2193      2.93%     94.52% # number of callpals executed
+system.cpu1.kern.callpal_wrkgp                      1      0.00%     94.52% # number of callpals executed
+system.cpu1.kern.callpal_wrusp                      3      0.00%     94.53% # number of callpals executed
+system.cpu1.kern.callpal_rdusp                      2      0.00%     94.53% # number of callpals executed
+system.cpu1.kern.callpal_whami                      3      0.00%     94.53% # number of callpals executed
+system.cpu1.kern.callpal_rti                     3893      5.21%     99.74% # number of callpals executed
+system.cpu1.kern.callpal_callsys                  161      0.22%     99.96% # number of callpals executed
 system.cpu1.kern.callpal_imb                       31      0.04%    100.00% # number of callpals executed
 system.cpu1.kern.callpal_rdunique                   1      0.00%    100.00% # number of callpals executed
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.hwrei                     81908                       # number of hwrei instructions executed
-system.cpu1.kern.inst.quiesce                    2770                       # number of quiesce instructions executed
-system.cpu1.kern.ipl_count                      72754                       # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_0                    28089     38.61%     38.61% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_22                    1964      2.70%     41.31% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_30                     536      0.74%     42.04% # number of times we switched to this ipl
-system.cpu1.kern.ipl_count_31                   42165     57.96%    100.00% # number of times we switched to this ipl
-system.cpu1.kern.ipl_good                       56376                       # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_0                     27206     48.26%     48.26% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_22                     1964      3.48%     51.74% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_30                      536      0.95%     52.69% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_good_31                    26670     47.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks               1951174446000                       # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_0             1904796411500     97.62%     97.62% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_22               499877500      0.03%     97.65% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_30               327859000      0.02%     97.67% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks_31             45550298000      2.33%    100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_used_0                  0.968564                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.inst.hwrei                     81736                       # number of hwrei instructions executed
+system.cpu1.kern.inst.quiesce                    2750                       # number of quiesce instructions executed
+system.cpu1.kern.ipl_count                      72277                       # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_0                    27874     38.57%     38.57% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_22                    1963      2.72%     41.28% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_30                     532      0.74%     42.02% # number of times we switched to this ipl
+system.cpu1.kern.ipl_count_31                   41908     57.98%    100.00% # number of times we switched to this ipl
+system.cpu1.kern.ipl_good                       55945                       # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_0                     26991     48.25%     48.25% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_22                     1963      3.51%     51.75% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_30                      532      0.95%     52.71% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_good_31                    26459     47.29%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu1.kern.ipl_ticks               1950198195000                       # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_0             1903911128000     97.63%     97.63% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_22               499586000      0.03%     97.65% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_30               325119000      0.02%     97.67% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks_31             45462362000      2.33%    100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_used_0                  0.968322                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used_22                        1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu1.kern.ipl_used_30                        1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.ipl_used_31                 0.632515                       # fraction of swpipl calls that actually changed the ipl
-system.cpu1.kern.mode_good_kernel                 924                      
-system.cpu1.kern.mode_good_user                   463                      
-system.cpu1.kern.mode_good_idle                   461                      
-system.cpu1.kern.mode_switch_kernel              2120                       # number of protection mode switches
-system.cpu1.kern.mode_switch_user                 463                       # number of protection mode switches
-system.cpu1.kern.mode_switch_idle                2943                       # number of protection mode switches
-system.cpu1.kern.mode_switch_good            1.592492                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_kernel     0.435849                       # fraction of useful protection mode switches
+system.cpu1.kern.ipl_used_31                 0.631359                       # fraction of swpipl calls that actually changed the ipl
+system.cpu1.kern.mode_good_kernel                 973                      
+system.cpu1.kern.mode_good_user                   516                      
+system.cpu1.kern.mode_good_idle                   457                      
+system.cpu1.kern.mode_switch_kernel              2210                       # number of protection mode switches
+system.cpu1.kern.mode_switch_user                 516                       # number of protection mode switches
+system.cpu1.kern.mode_switch_idle                2933                       # number of protection mode switches
+system.cpu1.kern.mode_switch_good            1.596085                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_switch_good_kernel     0.440271                       # fraction of useful protection mode switches
 system.cpu1.kern.mode_switch_good_user              1                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_switch_good_idle       0.156643                       # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks_kernel        18594859000      0.95%      0.95% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_user           1499702000      0.08%      1.03% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks_idle         1930131145000     98.97%    100.00% # number of ticks spent at the given mode
-system.cpu1.kern.swap_context                    2092                       # number of times the context was actually changed
-system.cpu1.kern.syscall                           98                       # number of syscalls executed
-system.cpu1.kern.syscall_2                          1      1.02%      1.02% # number of syscalls executed
-system.cpu1.kern.syscall_3                         11     11.22%     12.24% # number of syscalls executed
-system.cpu1.kern.syscall_4                          1      1.02%     13.27% # number of syscalls executed
-system.cpu1.kern.syscall_6                         11     11.22%     24.49% # number of syscalls executed
-system.cpu1.kern.syscall_17                         5      5.10%     29.59% # number of syscalls executed
-system.cpu1.kern.syscall_19                         4      4.08%     33.67% # number of syscalls executed
-system.cpu1.kern.syscall_20                         2      2.04%     35.71% # number of syscalls executed
-system.cpu1.kern.syscall_23                         2      2.04%     37.76% # number of syscalls executed
-system.cpu1.kern.syscall_24                         2      2.04%     39.80% # number of syscalls executed
-system.cpu1.kern.syscall_33                         3      3.06%     42.86% # number of syscalls executed
-system.cpu1.kern.syscall_45                        15     15.31%     58.16% # number of syscalls executed
-system.cpu1.kern.syscall_47                         2      2.04%     60.20% # number of syscalls executed
-system.cpu1.kern.syscall_48                         2      2.04%     62.24% # number of syscalls executed
-system.cpu1.kern.syscall_54                         1      1.02%     63.27% # number of syscalls executed
-system.cpu1.kern.syscall_59                         1      1.02%     64.29% # number of syscalls executed
-system.cpu1.kern.syscall_71                        22     22.45%     86.73% # number of syscalls executed
-system.cpu1.kern.syscall_74                         7      7.14%     93.88% # number of syscalls executed
-system.cpu1.kern.syscall_90                         1      1.02%     94.90% # number of syscalls executed
-system.cpu1.kern.syscall_92                         2      2.04%     96.94% # number of syscalls executed
-system.cpu1.kern.syscall_132                        2      2.04%     98.98% # number of syscalls executed
-system.cpu1.kern.syscall_144                        1      1.02%    100.00% # number of syscalls executed
-system.cpu1.not_idle_fraction                0.012799                       # Percentage of non-idle cycles
-system.cpu1.numCycles                    1951174476000                       # number of cpu cycles simulated
-system.cpu1.num_insts                        13758345                       # Number of instructions executed
-system.cpu1.num_refs                          4385954                       # Number of memory references
+system.cpu1.kern.mode_switch_good_idle       0.155813                       # fraction of useful protection mode switches
+system.cpu1.kern.mode_ticks_kernel        18488731000      0.95%      0.95% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_user           1533794000      0.08%      1.03% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks_idle         1929494996000     98.97%    100.00% # number of ticks spent at the given mode
+system.cpu1.kern.swap_context                    2124                       # number of times the context was actually changed
+system.cpu1.kern.syscall                          102                       # number of syscalls executed
+system.cpu1.kern.syscall_2                          2      1.96%      1.96% # number of syscalls executed
+system.cpu1.kern.syscall_3                         11     10.78%     12.75% # number of syscalls executed
+system.cpu1.kern.syscall_4                          1      0.98%     13.73% # number of syscalls executed
+system.cpu1.kern.syscall_6                         12     11.76%     25.49% # number of syscalls executed
+system.cpu1.kern.syscall_17                         5      4.90%     30.39% # number of syscalls executed
+system.cpu1.kern.syscall_19                         4      3.92%     34.31% # number of syscalls executed
+system.cpu1.kern.syscall_20                         2      1.96%     36.27% # number of syscalls executed
+system.cpu1.kern.syscall_23                         2      1.96%     38.24% # number of syscalls executed
+system.cpu1.kern.syscall_24                         2      1.96%     40.20% # number of syscalls executed
+system.cpu1.kern.syscall_33                         3      2.94%     43.14% # number of syscalls executed
+system.cpu1.kern.syscall_45                        15     14.71%     57.84% # number of syscalls executed
+system.cpu1.kern.syscall_47                         2      1.96%     59.80% # number of syscalls executed
+system.cpu1.kern.syscall_48                         3      2.94%     62.75% # number of syscalls executed
+system.cpu1.kern.syscall_54                         1      0.98%     63.73% # number of syscalls executed
+system.cpu1.kern.syscall_59                         2      1.96%     65.69% # number of syscalls executed
+system.cpu1.kern.syscall_71                        22     21.57%     87.25% # number of syscalls executed
+system.cpu1.kern.syscall_74                         7      6.86%     94.12% # number of syscalls executed
+system.cpu1.kern.syscall_90                         1      0.98%     95.10% # number of syscalls executed
+system.cpu1.kern.syscall_92                         2      1.96%     97.06% # number of syscalls executed
+system.cpu1.kern.syscall_132                        2      1.96%     99.02% # number of syscalls executed
+system.cpu1.kern.syscall_144                        1      0.98%    100.00% # number of syscalls executed
+system.cpu1.not_idle_fraction                0.012764                       # Percentage of non-idle cycles
+system.cpu1.numCycles                    1950198225000                       # number of cpu cycles simulated
+system.cpu1.num_insts                        13719733                       # Number of instructions executed
+system.cpu1.num_refs                          4374283                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -543,79 +543,149 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.l2c.ReadExReq_accesses                  297979                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency    12000.808782                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 11000.808782                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency          3575989000                       # number of ReadExReq miss cycles
+system.iocache.ReadReq_accesses                   174                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_avg_miss_latency  61942.517241                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 60942.517241                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency          10777998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses                     174                       # number of ReadReq misses
+system.iocache.ReadReq_mshr_miss_latency     10603998                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate               1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_misses                174                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_avg_miss_latency 55516.962023                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 54516.962023                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       2306840806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
+system.iocache.WriteReq_mshr_miss_latency   2265288806                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_rate              1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
+system.iocache.avg_blocked_cycles_no_mshrs  4139.072214                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs                 10455                       # number of cycles access was blocked
+system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs       43274000                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.demand_accesses                  41726                       # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency   55543.756986                       # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 54543.756986                       # average overall mshr miss latency
+system.iocache.demand_hits                          0                       # number of demand (read+write) hits
+system.iocache.demand_miss_latency         2317618804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
+system.iocache.demand_misses                    41726                       # number of demand (read+write) misses
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency    2275892804                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate                1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses               41726                       # number of demand (read+write) MSHR misses
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_accesses                 41726                       # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency  55543.756986                       # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 54543.756986                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.iocache.overall_hits                         0                       # number of overall hits
+system.iocache.overall_miss_latency        2317618804                       # number of overall miss cycles
+system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
+system.iocache.overall_misses                   41726                       # number of overall misses
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency   2275892804                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate               1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses              41726                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements                     41694                       # number of replacements
+system.iocache.sampled_refs                     41710                       # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse                     0.551457                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.warmup_cycle              1746599945000                       # Cycle when the warmup percentage was hit.
+system.iocache.writebacks                       41520                       # number of writebacks
+system.l2c.ReadExReq_accesses                  298324                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency    12003.110712                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 11003.110712                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency          3580816000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses                    297979                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency     3278010000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_misses                    298324                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency     3282492000                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_rate                 1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               297979                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses                   2726406                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency      12000.355770                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 11000.235046                       # average ReadReq mshr miss latency
+system.l2c.ReadExReq_mshr_misses               298324                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses                   2723731                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency      12011.836900                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 11011.716218                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits                       1633004                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           13121213000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate                 0.401042                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses                     1093402                       # number of ReadReq misses
+system.l2c.ReadReq_hits                       1629948                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           13138343000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate                 0.401575                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses                     1093783                       # number of ReadReq misses
 system.l2c.ReadReq_mshr_hits                       12                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency      12027679000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate            0.401042                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                1093402                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    779744500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses                 125211                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency   11388.943463                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 11003.410244                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency         1426021000                       # number of UpgradeReq miss cycles
+system.l2c.ReadReq_mshr_miss_latency      12044428000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate            0.401575                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses                1093783                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    779851500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses                 125534                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency   11396.557905                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 11005.795243                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency         1430655500                       # number of UpgradeReq miss cycles
 system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses                   125211                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency    1377748000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_misses                   125534                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency    1381601500                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_rate                1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses              125211                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses              125534                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1551434500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses                  416193                       # number of Writeback accesses(hits+misses)
+system.l2c.WriteReq_mshr_uncacheable_latency   1550658000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses                  416899                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_miss_rate                      1                       # miss rate for Writeback accesses
-system.l2c.Writeback_misses                    416193                       # number of Writeback misses
+system.l2c.Writeback_misses                    416899                       # number of Writeback misses
 system.l2c.Writeback_mshr_miss_rate                 1                       # mshr miss rate for Writeback accesses
-system.l2c.Writeback_mshr_misses               416193                       # number of Writeback MSHR misses
+system.l2c.Writeback_mshr_misses               416899                       # number of Writeback MSHR misses
 system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          1.713697                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          1.716036                       # Average number of references to valid blocks.
 system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
 system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses                    3024385                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency       12000.452788                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  11000.357918                       # average overall mshr miss latency
-system.l2c.demand_hits                        1633004                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            16697202000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate                  0.460054                       # miss rate for demand accesses
-system.l2c.demand_misses                      1391381                       # number of demand (read+write) misses
+system.l2c.demand_accesses                    3022055                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency       12009.966906                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency  11009.872086                       # average overall mshr miss latency
+system.l2c.demand_hits                        1629948                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            16719159000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate                  0.460649                       # miss rate for demand accesses
+system.l2c.demand_misses                      1392107                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                        12                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       15305689000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate             0.460054                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                 1391381                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_miss_latency       15326920000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate             0.460649                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                 1392107                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.overall_accesses                   3024385                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency      12000.452788                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 11000.357918                       # average overall mshr miss latency
+system.l2c.overall_accesses                   3022055                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency      12009.966906                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 11009.872086                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits                       1633004                       # number of overall hits
-system.l2c.overall_miss_latency           16697202000                       # number of overall miss cycles
-system.l2c.overall_miss_rate                 0.460054                       # miss rate for overall accesses
-system.l2c.overall_misses                     1391381                       # number of overall misses
+system.l2c.overall_hits                       1629948                       # number of overall hits
+system.l2c.overall_miss_latency           16719159000                       # number of overall miss cycles
+system.l2c.overall_miss_rate                 0.460649                       # miss rate for overall accesses
+system.l2c.overall_misses                     1392107                       # number of overall misses
 system.l2c.overall_mshr_hits                       12                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      15305689000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate            0.460054                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                1391381                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   2331179000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency      15326920000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate            0.460649                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                1392107                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   2330509500                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -626,11 +696,11 @@ system.l2c.prefetcher.num_hwpf_issued               0                       # nu
 system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements                        947502                       # number of replacements
-system.l2c.sampled_refs                        965785                       # Sample count of references to valid blocks.
+system.l2c.replacements                        947805                       # number of replacements
+system.l2c.sampled_refs                        965383                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     16369.951624                       # Cycle average of tags in use
-system.l2c.total_refs                         1655063                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     16367.051710                       # Cycle average of tags in use
+system.l2c.total_refs                         1656632                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                    5421925000                       # Cycle when the warmup percentage was hit.
 system.l2c.writebacks                               0                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
index e6ad9b469..50b440aad 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr
@@ -1,5 +1,5 @@
-Listening for system connection on port 3457
+Listening for system connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
 0: system.remote_gdb.listener: listening for remote gdb on port 7001
-0: system.remote_gdb.listener: listening for remote gdb on port 7002
 warn: Entering event queue @ 0.  Starting simulation...
 warn: 427086000: Trying to launch CPU number 1!
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
index 99539f3ea..1e296342a 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  3 2007 04:02:11
-M5 started Fri Aug  3 04:25:10 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 10 2007 16:03:34
+M5 started Fri Aug 10 16:05:34 2007
+M5 executing on zeep
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 1951367346000 because m5_exit instruction encountered
+Exiting @ tick 1950343222000 because m5_exit instruction encountered
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index 1992f65a2..24a7dfec3 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -5,7 +5,7 @@ dummy=0
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus l2c membus physmem sim_console simple_disk toL2Bus tsunami
+children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem sim_console simple_disk toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
 console=/dist/m5/system/binaries/console
@@ -22,8 +22,8 @@ system_type=34
 [system.bridge]
 type=Bridge
 delay=50000
-fix_partial_write_a=false
-fix_partial_write_b=true
+filter_ranges_a=0:18446744073709551615
+filter_ranges_b=0:8589934591
 nack_delay=4000
 req_size_a=16
 req_size_b=16
@@ -63,10 +63,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=4
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -101,10 +103,12 @@ type=BaseCache
 addr_range=0:18446744073709551615
 assoc=1
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=1000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=4
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -187,17 +191,55 @@ clock=1000
 responder_set=true
 width=64
 default=system.tsunami.pciconfig.pio
-port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.console.pio system.tsunami.ide.pio system.tsunami.ethernet.pio system.iocache.cpu_side system.tsunami.ethernet.config system.tsunami.ethernet.dma system.tsunami.ide.config system.tsunami.ide.dma
+
+[system.iocache]
+type=BaseCache
+addr_range=0:18446744073709551615
+assoc=8
+block_size=64
+cpu_side_filter_ranges=549755813888:18446744073709551615
+hash_delay=1
+latency=50000
+lifo=false
+max_miss_count=0
+mem_side_filter_ranges=0:18446744073709551615
+mshrs=20
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=500000
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+repl=Null
+size=1024
+split=false
+split_size=0
+subblock_size=0
+tgts_per_mshr=12
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.iobus.port[28]
+mem_side=system.membus.port[2]
 
 [system.l2c]
 type=BaseCache
 addr_range=0:18446744073709551615
 assoc=8
 block_size=64
+cpu_side_filter_ranges=
 hash_delay=1
 latency=10000
 lifo=false
 max_miss_count=0
+mem_side_filter_ranges=
 mshrs=92
 prefetch_access=false
 prefetch_cache_check_push=true
@@ -221,7 +263,7 @@ trace_addr=0
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.port[0]
-mem_side=system.membus.port[2]
+mem_side=system.membus.port[3]
 
 [system.membus]
 type=Bus
@@ -232,7 +274,7 @@ clock=1000
 responder_set=false
 width=64
 default=system.membus.responder.pio
-port=system.bridge.side_b system.physmem.port[0] system.l2c.mem_side
+port=system.bridge.side_b system.physmem.port[0] system.iocache.mem_side system.l2c.mem_side
 
 [system.membus.responder]
 type=IsaFake
@@ -366,8 +408,8 @@ system=system
 tx_delay=1000000
 tx_fifo_size=524288
 tx_thread=false
-config=system.iobus.port[28]
-dma=system.iobus.port[29]
+config=system.iobus.port[29]
+dma=system.iobus.port[30]
 pio=system.iobus.port[27]
 
 [system.tsunami.ethernet.configdata]
@@ -732,8 +774,8 @@ pci_func=0
 pio_latency=1000
 platform=system.tsunami
 system=system
-config=system.iobus.port[30]
-dma=system.iobus.port[31]
+config=system.iobus.port[31]
+dma=system.iobus.port[32]
 pio=system.iobus.port[26]
 
 [system.tsunami.ide.configdata]
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
index 5461cc4ab..7930e9e46 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/console.system.sim_console
@@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
hdb: M5 IDE Disk, ATA DISK drive
 
ide0 at 0x8410-0x8417,0x8422 on irq 31
 
hda: max request size: 128KiB
-
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
+
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
 
hda: cache flushes not supported
 
 hda: hda1
 
hdb: max request size: 128KiB
@@ -99,6 +99,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
All bugs added by David S. Miller <davem@redhat.com>
 
VFS: Mounted root (ext2 filesystem) readonly.
 
Freeing unused kernel memory: 224k freed
-

init started:  BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
-mounting filesystems...
-loading script...
+

init started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary

+mounting filesystems...

+EXT2-fs warning: checktime reached, running e2fsck is recommended
+
loading script...

diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
index 958246a30..bf5eb8731 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt
@@ -1,92 +1,92 @@
 
 ---------- Begin Simulation Statistics ----------
-host_inst_rate                                 631972                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 219140                       # Number of bytes of host memory used
-host_seconds                                    95.00                       # Real time elapsed on the host
-host_tick_rate                            20109299069                       # Simulator tick rate (ticks/s)
+host_inst_rate                                1028480                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 285368                       # Number of bytes of host memory used
+host_seconds                                    58.37                       # Real time elapsed on the host
+host_tick_rate                            32711130426                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                    60034774                       # Number of instructions simulated
-sim_seconds                                  1.910310                       # Number of seconds simulated
-sim_ticks                                1910309711000                       # Number of ticks simulated
-system.cpu.dcache.LoadLockedReq_accesses       200211                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 13960.656682                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12960.656682                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_hits           182851                       # number of LoadLockedReq hits
-system.cpu.dcache.LoadLockedReq_miss_latency    242357000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_rate     0.086709                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_misses          17360                       # number of LoadLockedReq misses
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency    224997000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.086709                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_misses        17360                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.ReadReq_accesses            9525872                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency 13240.454388                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12240.427719                       # average ReadReq mshr miss latency
+sim_insts                                    60031203                       # Number of instructions simulated
+sim_seconds                                  1.909320                       # Number of seconds simulated
+sim_ticks                                1909320028000                       # Number of ticks simulated
+system.cpu.dcache.LoadLockedReq_accesses       200196                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_avg_miss_latency 13961.565057                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 12961.565057                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_hits           182842                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_miss_latency    242289000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_rate     0.086685                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_misses          17354                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency    224935000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.086685                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_misses        17354                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.ReadReq_accesses            9525051                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency 13247.769109                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12247.742435                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.ReadReq_hits                7801048                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency    22837453500                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.181067                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1724824                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  21112583500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.181067                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1724824                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_hits                7800516                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency    22846241500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.181053                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              1724535                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency  21121660500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.181053                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         1724535                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency    830826000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.StoreCondReq_accesses        199189                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_avg_miss_latency 14000.798456                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 13000.798456                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_accesses        199174                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_avg_miss_latency 14002.263422                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 13002.263422                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_hits            169131                       # number of StoreCondReq hits
-system.cpu.dcache.StoreCondReq_miss_latency    420836000                       # number of StoreCondReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_rate     0.150902                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_misses           30058                       # number of StoreCondReq misses
-system.cpu.dcache.StoreCondReq_mshr_miss_latency    390778000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_rate     0.150902                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_misses        30058                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.WriteReq_accesses           6151132                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency 14000.947966                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13000.947966                       # average WriteReq mshr miss latency
+system.cpu.dcache.StoreCondReq_miss_latency    420670000                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_rate     0.150838                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_misses           30043                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_mshr_miss_latency    390627000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_rate     0.150838                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_misses        30043                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.WriteReq_accesses           6150630                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency 14004.147760                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13004.147760                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_hits               5750801                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency    5605013500                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.065082                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses              400331                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency   5204682500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.065082                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses         400331                       # number of WriteReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1164414500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_hits               5750414                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency    5604684000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.065069                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses              400216                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency   5204468000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.065069                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses         400216                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1164291500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                   6.854770                       # Average number of references to valid blocks.
+system.cpu.dcache.avg_refs                   6.855501                       # Average number of references to valid blocks.
 system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses            15677004                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency 13383.714129                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12383.692484                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits                13551849                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency     28442467000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.135559                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               2125155                       # number of demand (read+write) misses
+system.cpu.dcache.demand_accesses            15675681                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency 13390.239845                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency 12390.218195                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits                13550930                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency     28450925500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.135544                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               2124751                       # number of demand (read+write) misses
 system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency  26317266000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.135559                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          2125155                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_miss_latency  26326128500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.135544                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          2124751                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses           15677004                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency 13383.714129                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12383.692484                       # average overall mshr miss latency
+system.cpu.dcache.overall_accesses           15675681                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency 13390.239845                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency 12390.218195                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits               13551849                       # number of overall hits
-system.cpu.dcache.overall_miss_latency    28442467000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.135559                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              2125155                       # number of overall misses
+system.cpu.dcache.overall_hits               13550930                       # number of overall hits
+system.cpu.dcache.overall_miss_latency    28450925500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.135544                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              2124751                       # number of overall misses
 system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency  26317266000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.135559                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         2125155                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency   1995240500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_miss_latency  26326128500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.135544                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         2124751                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency   1995117500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -97,69 +97,69 @@ system.cpu.dcache.prefetcher.num_hwpf_issued            0
 system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements                2046194                       # number of replacements
-system.cpu.dcache.sampled_refs                2046706                       # Sample count of references to valid blocks.
+system.cpu.dcache.replacements                2045831                       # number of replacements
+system.cpu.dcache.sampled_refs                2046343                       # Sample count of references to valid blocks.
 system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse                511.987834                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                 14029698                       # Total number of references to valid blocks.
+system.cpu.dcache.tagsinuse                511.987794                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                 14028706                       # Total number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               58297000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                   429991                       # number of writebacks
+system.cpu.dcache.writebacks                   429859                       # number of writebacks
 system.cpu.dtb.accesses                       1020787                       # DTB accesses
 system.cpu.dtb.acv                                367                       # DTB access violations
-system.cpu.dtb.hits                          16056951                       # DTB hits
+system.cpu.dtb.hits                          16055629                       # DTB hits
 system.cpu.dtb.misses                           11471                       # DTB misses
 system.cpu.dtb.read_accesses                   728856                       # DTB read accesses
 system.cpu.dtb.read_acv                           210                       # DTB read access violations
-system.cpu.dtb.read_hits                      9706492                       # DTB read hits
+system.cpu.dtb.read_hits                      9705676                       # DTB read hits
 system.cpu.dtb.read_misses                      10329                       # DTB read misses
 system.cpu.dtb.write_accesses                  291931                       # DTB write accesses
 system.cpu.dtb.write_acv                          157                       # DTB write access violations
-system.cpu.dtb.write_hits                     6350459                       # DTB write hits
+system.cpu.dtb.write_hits                     6349953                       # DTB write hits
 system.cpu.dtb.write_misses                      1142                       # DTB write misses
-system.cpu.icache.ReadReq_accesses           60034775                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency 12033.060657                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11032.326155                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits               59106935                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency    11164755000                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.015455                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses               927840                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency  10236233500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.015455                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses          927840                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_accesses           60031204                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency 12033.101057                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency 11032.368005                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits               59103575                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency    11162253500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.015452                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses               927629                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency  10233944500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.015452                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses          927629                       # number of ReadReq MSHR misses
 system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0>                       # average number of cycles each access was blocked
 system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs                  63.714789                       # Average number of references to valid blocks.
+system.cpu.icache.avg_refs                  63.725661                       # Average number of references to valid blocks.
 system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
 system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses            60034775                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency 12033.060657                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11032.326155                       # average overall mshr miss latency
-system.cpu.icache.demand_hits                59106935                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency     11164755000                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.015455                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                927840                       # number of demand (read+write) misses
+system.cpu.icache.demand_accesses            60031204                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency 12033.101057                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency 11032.368005                       # average overall mshr miss latency
+system.cpu.icache.demand_hits                59103575                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency     11162253500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.015452                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                927629                       # number of demand (read+write) misses
 system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency  10236233500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.015455                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses           927840                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_miss_latency  10233944500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.015452                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses           927629                       # number of demand (read+write) MSHR misses
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses           60034775                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency 12033.060657                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11032.326155                       # average overall mshr miss latency
+system.cpu.icache.overall_accesses           60031204                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency 12033.101057                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency 11032.368005                       # average overall mshr miss latency
 system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits               59106935                       # number of overall hits
-system.cpu.icache.overall_miss_latency    11164755000                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.015455                       # miss rate for overall accesses
-system.cpu.icache.overall_misses               927840                       # number of overall misses
+system.cpu.icache.overall_hits               59103575                       # number of overall hits
+system.cpu.icache.overall_miss_latency    11162253500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.015452                       # miss rate for overall accesses
+system.cpu.icache.overall_misses               927629                       # number of overall misses
 system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency  10236233500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.015455                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses          927840                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_miss_latency  10233944500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.015452                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses          927629                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
 system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
@@ -171,71 +171,71 @@ system.cpu.icache.prefetcher.num_hwpf_issued            0
 system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements                 927169                       # number of replacements
-system.cpu.icache.sampled_refs                 927680                       # Sample count of references to valid blocks.
+system.cpu.icache.replacements                 926958                       # number of replacements
+system.cpu.icache.sampled_refs                 927469                       # Sample count of references to valid blocks.
 system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse                508.749374                       # Cycle average of tags in use
-system.cpu.icache.total_refs                 59106935                       # Total number of references to valid blocks.
+system.cpu.icache.tagsinuse                508.747859                       # Cycle average of tags in use
+system.cpu.icache.total_refs                 59103575                       # Total number of references to valid blocks.
 system.cpu.icache.warmup_cycle            35000367000                       # Cycle when the warmup percentage was hit.
 system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                     0.939637                       # Percentage of idle cycles
-system.cpu.itb.accesses                       4978395                       # ITB accesses
+system.cpu.idle_fraction                     0.939605                       # Percentage of idle cycles
+system.cpu.itb.accesses                       4978081                       # ITB accesses
 system.cpu.itb.acv                                184                       # ITB acv
-system.cpu.itb.hits                           4973389                       # ITB hits
+system.cpu.itb.hits                           4973075                       # ITB hits
 system.cpu.itb.misses                            5006                       # ITB misses
-system.cpu.kern.callpal                        192813                       # number of callpals executed
+system.cpu.kern.callpal                        192799                       # number of callpals executed
 system.cpu.kern.callpal_cserve                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrmces                      1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrfen                       1      0.00%      0.00% # number of callpals executed
 system.cpu.kern.callpal_wrvptptr                    1      0.00%      0.00% # number of callpals executed
-system.cpu.kern.callpal_swpctx                   4176      2.17%      2.17% # number of callpals executed
-system.cpu.kern.callpal_tbi                        54      0.03%      2.20% # number of callpals executed
+system.cpu.kern.callpal_swpctx                   4172      2.16%      2.17% # number of callpals executed
+system.cpu.kern.callpal_tbi                        54      0.03%      2.19% # number of callpals executed
 system.cpu.kern.callpal_wrent                       7      0.00%      2.20% # number of callpals executed
-system.cpu.kern.callpal_swpipl                 175877     91.22%     93.42% # number of callpals executed
-system.cpu.kern.callpal_rdps                     6828      3.54%     96.96% # number of callpals executed
+system.cpu.kern.callpal_swpipl                 175869     91.22%     93.42% # number of callpals executed
+system.cpu.kern.callpal_rdps                     6827      3.54%     96.96% # number of callpals executed
 system.cpu.kern.callpal_wrkgp                       1      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal_wrusp                       7      0.00%     96.96% # number of callpals executed
 system.cpu.kern.callpal_rdusp                       9      0.00%     96.97% # number of callpals executed
 system.cpu.kern.callpal_whami                       2      0.00%     96.97% # number of callpals executed
-system.cpu.kern.callpal_rti                      5152      2.67%     99.64% # number of callpals executed
+system.cpu.kern.callpal_rti                      5151      2.67%     99.64% # number of callpals executed
 system.cpu.kern.callpal_callsys                   515      0.27%     99.91% # number of callpals executed
 system.cpu.kern.callpal_imb                       181      0.09%    100.00% # number of callpals executed
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
-system.cpu.kern.inst.hwrei                     211901                       # number of hwrei instructions executed
-system.cpu.kern.inst.quiesce                     6181                       # number of quiesce instructions executed
-system.cpu.kern.ipl_count                      183088                       # number of times we switched to this ipl
-system.cpu.kern.ipl_count_0                     74875     40.90%     40.90% # number of times we switched to this ipl
+system.cpu.kern.inst.hwrei                     211886                       # number of hwrei instructions executed
+system.cpu.kern.inst.quiesce                     6177                       # number of quiesce instructions executed
+system.cpu.kern.ipl_count                      183078                       # number of times we switched to this ipl
+system.cpu.kern.ipl_count_0                     74873     40.90%     40.90% # number of times we switched to this ipl
 system.cpu.kern.ipl_count_21                      131      0.07%     40.97% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_22                     1927      1.05%     42.02% # number of times we switched to this ipl
-system.cpu.kern.ipl_count_31                   106155     57.98%    100.00% # number of times we switched to this ipl
-system.cpu.kern.ipl_good                       149074                       # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_0                      73508     49.31%     49.31% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_count_22                     1926      1.05%     42.02% # number of times we switched to this ipl
+system.cpu.kern.ipl_count_31                   106148     57.98%    100.00% # number of times we switched to this ipl
+system.cpu.kern.ipl_good                       149069                       # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_0                      73506     49.31%     49.31% # number of times we switched to this ipl from a different ipl
 system.cpu.kern.ipl_good_21                       131      0.09%     49.40% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_22                      1927      1.29%     50.69% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_good_31                     73508     49.31%    100.00% # number of times we switched to this ipl from a different ipl
-system.cpu.kern.ipl_ticks                1910308997000                       # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_0              1853401678500     97.02%     97.02% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_21                 78202500      0.00%     97.03% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_22                538133000      0.03%     97.05% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_ticks_31              56290983000      2.95%    100.00% # number of cycles we spent at this ipl
-system.cpu.kern.ipl_used_0                   0.981743                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.ipl_good_22                      1926      1.29%     50.69% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_good_31                     73506     49.31%    100.00% # number of times we switched to this ipl from a different ipl
+system.cpu.kern.ipl_ticks                1909319316000                       # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_0              1852420057000     97.02%     97.02% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_21                 77949500      0.00%     97.02% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_22                537776500      0.03%     97.05% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_ticks_31              56283533000      2.95%    100.00% # number of cycles we spent at this ipl
+system.cpu.kern.ipl_used_0                   0.981742                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_21                         1                       # fraction of swpipl calls that actually changed the ipl
 system.cpu.kern.ipl_used_22                         1                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.ipl_used_31                  0.692459                       # fraction of swpipl calls that actually changed the ipl
-system.cpu.kern.mode_good_kernel                 1908                      
-system.cpu.kern.mode_good_user                   1738                      
-system.cpu.kern.mode_good_idle                    170                      
-system.cpu.kern.mode_switch_kernel               5896                       # number of protection mode switches
-system.cpu.kern.mode_switch_user                 1738                       # number of protection mode switches
-system.cpu.kern.mode_switch_idle                 2098                       # number of protection mode switches
-system.cpu.kern.mode_switch_good             1.404639                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_kernel      0.323609                       # fraction of useful protection mode switches
+system.cpu.kern.ipl_used_31                  0.692486                       # fraction of swpipl calls that actually changed the ipl
+system.cpu.kern.mode_good_kernel                 1907                      
+system.cpu.kern.mode_good_user                   1739                      
+system.cpu.kern.mode_good_idle                    168                      
+system.cpu.kern.mode_switch_kernel               5895                       # number of protection mode switches
+system.cpu.kern.mode_switch_user                 1739                       # number of protection mode switches
+system.cpu.kern.mode_switch_idle                 2094                       # number of protection mode switches
+system.cpu.kern.mode_switch_good             1.403724                       # fraction of useful protection mode switches
+system.cpu.kern.mode_switch_good_kernel      0.323494                       # fraction of useful protection mode switches
 system.cpu.kern.mode_switch_good_user               1                       # fraction of useful protection mode switches
-system.cpu.kern.mode_switch_good_idle        0.081030                       # fraction of useful protection mode switches
-system.cpu.kern.mode_ticks_kernel         43115749000      2.26%      2.26% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_user            4716926000      0.25%      2.50% # number of ticks spent at the given mode
-system.cpu.kern.mode_ticks_idle          1862476320000     97.50%    100.00% # number of ticks spent at the given mode
-system.cpu.kern.swap_context                     4177                       # number of times the context was actually changed
+system.cpu.kern.mode_switch_good_idle        0.080229                       # fraction of useful protection mode switches
+system.cpu.kern.mode_ticks_kernel         43141321000      2.26%      2.26% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_user            4716637000      0.25%      2.51% # number of ticks spent at the given mode
+system.cpu.kern.mode_ticks_idle          1861461356000     97.49%    100.00% # number of ticks spent at the given mode
+system.cpu.kern.swap_context                     4173                       # number of times the context was actually changed
 system.cpu.kern.syscall                           326                       # number of syscalls executed
 system.cpu.kern.syscall_2                           8      2.45%      2.45% # number of syscalls executed
 system.cpu.kern.syscall_3                          30      9.20%     11.66% # number of syscalls executed
@@ -267,10 +267,10 @@ system.cpu.kern.syscall_98                          2      0.61%     97.55% # nu
 system.cpu.kern.syscall_132                         4      1.23%     98.77% # number of syscalls executed
 system.cpu.kern.syscall_144                         2      0.61%     99.39% # number of syscalls executed
 system.cpu.kern.syscall_147                         2      0.61%    100.00% # number of syscalls executed
-system.cpu.not_idle_fraction                 0.060363                       # Percentage of non-idle cycles
-system.cpu.numCycles                     1910309711000                       # number of cpu cycles simulated
-system.cpu.num_insts                         60034774                       # Number of instructions executed
-system.cpu.num_refs                          16305091                       # Number of memory references
+system.cpu.not_idle_fraction                 0.060395                       # Percentage of non-idle cycles
+system.cpu.numCycles                     1909320028000                       # number of cpu cycles simulated
+system.cpu.num_insts                         60031203                       # Number of instructions executed
+system.cpu.num_refs                          16303737                       # Number of memory references
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_txs                           1                       # Number of DMA read transactions (not PRD).
@@ -283,78 +283,148 @@ system.disk2.dma_read_txs                           0                       # Nu
 system.disk2.dma_write_bytes                     8192                       # Number of bytes transfered via DMA writes.
 system.disk2.dma_write_full_pages                   1                       # Number of full page size DMA writes.
 system.disk2.dma_write_txs                          1                       # Number of DMA write transactions.
-system.l2c.ReadExReq_accesses                  304522                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency    12000.719160                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 11000.719160                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency          3654483000                       # number of ReadExReq miss cycles
+system.iocache.ReadReq_accesses                   173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_avg_miss_latency  61832.358382                       # average ReadReq miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency 60832.358382                       # average ReadReq mshr miss latency
+system.iocache.ReadReq_miss_latency          10696998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_rate                    1                       # miss rate for ReadReq accesses
+system.iocache.ReadReq_misses                     173                       # number of ReadReq misses
+system.iocache.ReadReq_mshr_miss_latency     10523998                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate               1                       # mshr miss rate for ReadReq accesses
+system.iocache.ReadReq_mshr_misses                173                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_accesses                41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_avg_miss_latency 55508.947969                       # average WriteReq miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency 54508.947969                       # average WriteReq mshr miss latency
+system.iocache.WriteReq_miss_latency       2306507806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_rate                   1                       # miss rate for WriteReq accesses
+system.iocache.WriteReq_misses                  41552                       # number of WriteReq misses
+system.iocache.WriteReq_mshr_miss_latency   2264955806                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_rate              1                       # mshr miss rate for WriteReq accesses
+system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
+system.iocache.avg_blocked_cycles_no_mshrs  4134.747706                       # average number of cycles each access was blocked
+system.iocache.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
+system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
+system.iocache.blocked_no_mshrs                 10464                       # number of cycles access was blocked
+system.iocache.blocked_no_targets                   0                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_mshrs       43266000                       # number of cycles access was blocked
+system.iocache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.iocache.cache_copies                         0                       # number of cache copies performed
+system.iocache.demand_accesses                  41725                       # number of demand (read+write) accesses
+system.iocache.demand_avg_miss_latency   55535.166064                       # average overall miss latency
+system.iocache.demand_avg_mshr_miss_latency 54535.166064                       # average overall mshr miss latency
+system.iocache.demand_hits                          0                       # number of demand (read+write) hits
+system.iocache.demand_miss_latency         2317204804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_rate                     1                       # miss rate for demand accesses
+system.iocache.demand_misses                    41725                       # number of demand (read+write) misses
+system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
+system.iocache.demand_mshr_miss_latency    2275479804                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_rate                1                       # mshr miss rate for demand accesses
+system.iocache.demand_mshr_misses               41725                       # number of demand (read+write) MSHR misses
+system.iocache.fast_writes                          0                       # number of fast writes performed
+system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
+system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
+system.iocache.overall_accesses                 41725                       # number of overall (read+write) accesses
+system.iocache.overall_avg_miss_latency  55535.166064                       # average overall miss latency
+system.iocache.overall_avg_mshr_miss_latency 54535.166064                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_uncacheable_latency <err: div-0>                       # average overall mshr uncacheable latency
+system.iocache.overall_hits                         0                       # number of overall hits
+system.iocache.overall_miss_latency        2317204804                       # number of overall miss cycles
+system.iocache.overall_miss_rate                    1                       # miss rate for overall accesses
+system.iocache.overall_misses                   41725                       # number of overall misses
+system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
+system.iocache.overall_mshr_miss_latency   2275479804                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_rate               1                       # mshr miss rate for overall accesses
+system.iocache.overall_mshr_misses              41725                       # number of overall MSHR misses
+system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.iocache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.iocache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.iocache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.iocache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.iocache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.iocache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.iocache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.iocache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.iocache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.iocache.replacements                     41685                       # number of replacements
+system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
+system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.tagsinuse                     1.326249                       # Cycle average of tags in use
+system.iocache.total_refs                           0                       # Total number of references to valid blocks.
+system.iocache.warmup_cycle              1746583798000                       # Cycle when the warmup percentage was hit.
+system.iocache.writebacks                       41512                       # number of writebacks
+system.l2c.ReadExReq_accesses                  304456                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency    12004.125391                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 11004.125391                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency          3654728000                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses                    304522                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_miss_latency     3349961000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_misses                    304456                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_miss_latency     3350272000                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_rate                 1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses               304522                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses                   2670005                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency      12000.233269                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 11000.233269                       # average ReadReq mshr miss latency
+system.l2c.ReadExReq_mshr_misses               304456                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses                   2669499                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency      12011.481535                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 11011.481535                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits                       1568273                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency           13221041000                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate                 0.412633                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses                     1101732                       # number of ReadReq misses
-system.l2c.ReadReq_mshr_miss_latency      12119309000                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate            0.412633                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                1101732                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_hits                       1567817                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency           13232833000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate                 0.412692                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses                     1101682                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_miss_latency      12131151000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate            0.412692                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses                1101682                       # number of ReadReq MSHR misses
 system.l2c.ReadReq_mshr_uncacheable_latency    750102000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses                 125867                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency   11999.892744                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 11000.750793                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency         1510390500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_accesses                 125803                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency   12002.178008                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 11003.036494                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency         1509910000                       # number of UpgradeReq miss cycles
 system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses                   125867                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_miss_latency    1384631500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_misses                   125803                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_miss_latency    1384215000                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_rate                1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses              125867                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses              125803                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency   1051110500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses                  429991                       # number of Writeback accesses(hits+misses)
+system.l2c.WriteReq_mshr_uncacheable_latency   1050999500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses                  429859                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_miss_rate                      1                       # miss rate for Writeback accesses
-system.l2c.Writeback_misses                    429991                       # number of Writeback misses
+system.l2c.Writeback_misses                    429859                       # number of Writeback misses
 system.l2c.Writeback_mshr_miss_rate                 1                       # mshr miss rate for Writeback accesses
-system.l2c.Writeback_mshr_misses               429991                       # number of Writeback MSHR misses
+system.l2c.Writeback_mshr_misses               429859                       # number of Writeback MSHR misses
 system.l2c.avg_blocked_cycles_no_mshrs   <err: div-0>                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          1.660842                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          1.660129                       # Average number of references to valid blocks.
 system.l2c.blocked_no_mshrs                         0                       # number of cycles access was blocked
 system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_mshrs                  0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses                    2974527                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency       12000.338488                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  11000.338488                       # average overall mshr miss latency
-system.l2c.demand_hits                        1568273                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency            16875524000                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate                  0.472766                       # miss rate for demand accesses
-system.l2c.demand_misses                      1406254                       # number of demand (read+write) misses
+system.l2c.demand_accesses                    2973955                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency       12009.888788                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency  11009.888788                       # average overall mshr miss latency
+system.l2c.demand_hits                        1567817                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency            16887561000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate                  0.472818                       # miss rate for demand accesses
+system.l2c.demand_misses                      1406138                       # number of demand (read+write) misses
 system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency       15469270000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate             0.472766                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                 1406254                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_miss_latency       15481423000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate             0.472818                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                 1406138                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.overall_accesses                   2974527                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency      12000.338488                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 11000.338488                       # average overall mshr miss latency
+system.l2c.overall_accesses                   2973955                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency      12009.888788                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 11009.888788                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits                       1568273                       # number of overall hits
-system.l2c.overall_miss_latency           16875524000                       # number of overall miss cycles
-system.l2c.overall_miss_rate                 0.472766                       # miss rate for overall accesses
-system.l2c.overall_misses                     1406254                       # number of overall misses
+system.l2c.overall_hits                       1567817                       # number of overall hits
+system.l2c.overall_miss_latency           16887561000                       # number of overall miss cycles
+system.l2c.overall_miss_rate                 0.472818                       # miss rate for overall accesses
+system.l2c.overall_misses                     1406138                       # number of overall misses
 system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency      15469270000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate            0.472766                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                1406254                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   1801212500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_miss_latency      15481423000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate            0.472818                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                1406138                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   1801101500                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -365,11 +435,11 @@ system.l2c.prefetcher.num_hwpf_issued               0                       # nu
 system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements                        947259                       # number of replacements
-system.l2c.sampled_refs                        965538                       # Sample count of references to valid blocks.
+system.l2c.replacements                        947227                       # number of replacements
+system.l2c.sampled_refs                        965496                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                     15874.904757                       # Cycle average of tags in use
-system.l2c.total_refs                         1603606                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                     15873.138648                       # Cycle average of tags in use
+system.l2c.total_refs                         1602848                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                    4106790000                       # Cycle when the warmup percentage was hit.
 system.l2c.writebacks                               0                       # number of writebacks
 system.tsunami.ethernet.coalescedRxDesc  <err: div-0>                       # average number of RxDesc's coalesced into each post
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
index 32120d9d6..072cb6c8c 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr
@@ -1,3 +1,3 @@
-Listening for system connection on port 3457
-0: system.remote_gdb.listener: listening for remote gdb on port 7001
+Listening for system connection on port 3456
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
 warn: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
index 69f3594a5..59e425d24 100644
--- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
+++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  3 2007 04:02:11
-M5 started Fri Aug  3 04:23:34 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 10 2007 16:03:34
+M5 started Fri Aug 10 16:04:35 2007
+M5 executing on zeep
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/10.linux-boot/alpha/linux/tsunami-simple-timing tests/run.py quick/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 1910309711000 because m5_exit instruction encountered
+Exiting @ tick 1909320028000 because m5_exit instruction encountered
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index 4cbaaf71e..3385f4fea 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -14,7 +14,7 @@ kernel=/dist/m5/system/binaries/vmlinux
 mem_mode=atomic
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=drivesys.physmem
-readfile=/z/stever/hg/m5.stever/configs/boot/netperf-server.rcS
+readfile=/z/saidi/work/m5.bb/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -22,8 +22,8 @@ system_type=34
 [drivesys.bridge]
 type=Bridge
 delay=50000
-fix_partial_write_a=false
-fix_partial_write_b=true
+filter_ranges_a=
+filter_ranges_b=
 nack_delay=4000
 req_size_a=16
 req_size_b=16
@@ -708,7 +708,7 @@ kernel=/dist/m5/system/binaries/vmlinux
 mem_mode=atomic
 pal=/dist/m5/system/binaries/ts_osfpal
 physmem=testsys.physmem
-readfile=/z/stever/hg/m5.stever/configs/boot/netperf-stream-client.rcS
+readfile=/z/saidi/work/m5.bb/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -716,8 +716,8 @@ system_type=34
 [testsys.bridge]
 type=Bridge
 delay=50000
-fix_partial_write_a=false
-fix_partial_write_b=true
+filter_ranges_a=
+filter_ranges_b=
 nack_delay=4000
 req_size_a=16
 req_size_b=16
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console
index aa129d6a7..89c68d228 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.drivesys.sim_console
@@ -58,7 +58,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
eth0: ns83820.c: 0x22c: 00000000, subsystem: 0000:0000
 
eth0: enabling optical transceiver
 
eth0: using 64 bit addressing.
-
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:02 io=0x09000000 irq=30 f=h,sg
+
eth0: ns83820 v0.22: DP83820 v1.3: 00:90:00:00:00:01 io=0x09000000 irq=30 f=h,sg
 
tun: Universal TUN/TAP device driver, 1.6
 
tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
 
Uniform Multi-Platform E-IDE driver Revision: 7.00alpha2
@@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
hdb: M5 IDE Disk, ATA DISK drive
 
ide0 at 0x8410-0x8417,0x8422 on irq 31
 
hda: max request size: 128KiB
-
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
+
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
 
hda: cache flushes not supported
 
 hda: hda1
 
hdb: max request size: 128KiB
@@ -99,13 +99,14 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
All bugs added by David S. Miller <davem@redhat.com>
 
VFS: Mounted root (ext2 filesystem) readonly.
 
Freeing unused kernel memory: 224k freed
-

init started:  BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
-mounting filesystems...
-loading script...
-setting up network...
+

init started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary

+mounting filesystems...

+EXT2-fs warning: checktime reached, running e2fsck is recommended
+
loading script...

+setting up network...

 eth0: link now 1000F mbps, full duplex and up.
-
running netserver...
-Starting netserver at port 12865
-signal client to begin...done.
-starting bash...
+
running netserver...

+Starting netserver at port 12865

+signal client to begin...done.

+starting bash...

 # 
\ No newline at end of file
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console
index b8f1a6cae..c1cb6aad0 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/console.testsys.sim_console
@@ -72,7 +72,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
hdb: M5 IDE Disk, ATA DISK drive
 
ide0 at 0x8410-0x8417,0x8422 on irq 31
 
hda: max request size: 128KiB
-
hda: 511056 sectors (261 MB), CHS=507/16/63, UDMA(33)
+
hda: 101808 sectors (52 MB), CHS=101/16/63, UDMA(33)
 
hda: cache flushes not supported
 
 hda: hda1
 
hdb: max request size: 128KiB
@@ -99,22 +99,23 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
All bugs added by David S. Miller <davem@redhat.com>
 
VFS: Mounted root (ext2 filesystem) readonly.
 
Freeing unused kernel memory: 224k freed
-

init started:  BusyBox v1.1.0 (2006.08.17-02:54+0000) multi-call binary
-mounting filesystems...
-loading script...
-setting up network...
+

init started:  BusyBox v1.1.0 (2007.03.04-01:07+0000) multi-call binary

+mounting filesystems...

+EXT2-fs warning: checktime reached, running e2fsck is recommended
+
loading script...

+setting up network...

 eth0: link now 1000F mbps, full duplex and up.
-
waiting for server...server ready
-starting test...
-netperf warmup
-/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -l -100k
-TCP STREAM TEST to 10.0.0.1 : dirty data
-Recv   Send    Send                          
-Socket Socket  Message  Elapsed              
-Size   Size    Size     Time     Throughput  
-bytes  bytes   bytes    secs.    10^6bits/sec  
-
-5000000 5000000 5000000    1.29       30.91   
-netperf benchmark
-/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144
-TCP STREAM TEST to 10.0.0.1 : dirty data
+
waiting for server...server ready

+starting test...

+netperf warmup

+/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -l -100k

+TCP STREAM TEST to 10.0.0.1 : dirty data

+Recv   Send    Send                          

+Socket Socket  Message  Elapsed              

+Size   Size    Size     Time     Throughput  

+bytes  bytes   bytes    secs.    10^6bits/sec  

+

+5000000 5000000 5000000    1.29       30.91   

+netperf benchmark

+/benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144

+TCP STREAM TEST to 10.0.0.1 : dirty data

diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
index 719430102..c63520549 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/m5stats.txt
@@ -139,10 +139,10 @@ drivesys.tsunami.ethernet.txPPS                    25                       # Pa
 drivesys.tsunami.ethernet.txPackets                 5                       # Number of Packets Transmitted
 drivesys.tsunami.ethernet.txTcpChecksums            2                       # Number of tx TCP Checksums done by device
 drivesys.tsunami.ethernet.txUdpChecksums            0                       # Number of tx UDP Checksums done by device
-host_inst_rate                               51081325                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 406704                       # Number of bytes of host memory used
-host_seconds                                     5.35                       # Real time elapsed on the host
-host_tick_rate                            37372483621                       # Simulator tick rate (ticks/s)
+host_inst_rate                              109126509                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 477016                       # Number of bytes of host memory used
+host_seconds                                     2.51                       # Real time elapsed on the host
+host_tick_rate                            79838467246                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273348482                       # Number of instructions simulated
 sim_seconds                                  0.200001                       # Number of seconds simulated
@@ -381,10 +381,10 @@ drivesys.tsunami.ethernet.totalSwi                  0                       # to
 drivesys.tsunami.ethernet.totalTxDesc               0                       # total number of TxDesc written to ISR
 drivesys.tsunami.ethernet.totalTxIdle               0                       # total number of TxIdle written to ISR
 drivesys.tsunami.ethernet.totalTxOk                 0                       # total number of TxOk written to ISR
-host_inst_rate                            71036507796                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 406704                       # Number of bytes of host memory used
+host_inst_rate                           139108642239                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 477016                       # Number of bytes of host memory used
 host_seconds                                     0.00                       # Real time elapsed on the host
-host_tick_rate                              191282064                       # Simulator tick rate (ticks/s)
+host_tick_rate                              375168496                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_insts                                   273348482                       # Number of instructions simulated
 sim_seconds                                  0.000001                       # Number of seconds simulated
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
index 4f6a93597..891b3e205 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stderr
@@ -1,6 +1,6 @@
-Listening for testsys connection on port 3457
-Listening for drivesys connection on port 3458
-0: testsys.remote_gdb.listener: listening for remote gdb on port 7001
-0: drivesys.remote_gdb.listener: listening for remote gdb on port 7002
+Listening for testsys connection on port 3456
+Listening for drivesys connection on port 3457
+0: testsys.remote_gdb.listener: listening for remote gdb on port 7000
+0: drivesys.remote_gdb.listener: listening for remote gdb on port 7001
 warn: Entering event queue @ 0.  Starting simulation...
 warn: Obsolete M5 instruction ivlb encountered.
diff --git a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
index 3b074da7f..345be7558 100644
--- a/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
+++ b/tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug  3 2007 04:02:11
-M5 started Fri Aug  3 04:26:58 2007
-M5 executing on zizzer.eecs.umich.edu
+M5 compiled Aug 10 2007 16:03:34
+M5 started Fri Aug 10 16:06:35 2007
+M5 executing on zeep
 command line: build/ALPHA_FS/m5.fast -d build/ALPHA_FS/tests/fast/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic tests/run.py quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 Exiting @ tick 4300235844056 because checkpoint
diff --git a/util/statetrace/arch/tracechild_amd64.cc b/util/statetrace/arch/tracechild_amd64.cc
index 222923972..112ee793e 100644
--- a/util/statetrace/arch/tracechild_amd64.cc
+++ b/util/statetrace/arch/tracechild_amd64.cc
@@ -317,7 +317,15 @@ bool AMD64TraceChild::step()
         ptrace(PTRACE_POKEDATA, pid, ripAfterSyscall, buf);
     }
     else
-        ptraceSingleStep();
+    {
+        //Get all the way past repe and repne string instructions in one shot.
+        uint64_t newPC, origPC = getPC();
+        do
+        {
+            ptraceSingleStep();
+            newPC = getPC();
+        } while(newPC == origPC);
+    }
 }
 
 TraceChild * genTraceChild()