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authorHoa Nguyen <hoanguyen@ucdavis.edu>2019-02-28 18:26:07 -0800
committerHoa Nguyen <hoanguyen@ucdavis.edu>2019-04-12 06:15:27 +0000
commit6b81e087c239e74a84405805bc8a3f6f3c1798a4 (patch)
treeeddf7b5eb3875aa7928c278c5d59a41713f3c4fc
parent04bc162f152b4a67aad921b4965353cb73cbc820 (diff)
downloadgem5-6b81e087c239e74a84405805bc8a3f6f3c1798a4.tar.xz
tests: add riscv to cpu tests
Change-Id: Id8e767afbb74f79b980d8160eefc13e7f529f1c3 Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16889 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com>
-rw-r--r--tests/gem5/cpu_tests/test.py1
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/gem5/cpu_tests/test.py b/tests/gem5/cpu_tests/test.py
index 6fb68a9db..f34b23d07 100644
--- a/tests/gem5/cpu_tests/test.py
+++ b/tests/gem5/cpu_tests/test.py
@@ -38,6 +38,7 @@ workloads = ('Bubblesort','FloatMM')
valid_isas = {
'x86': ('AtomicSimpleCPU', 'TimingSimpleCPU', 'DerivO3CPU'),
'arm': ('AtomicSimpleCPU', 'TimingSimpleCPU', 'MinorCPU', 'DerivO3CPU'),
+ 'riscv': ('AtomicSimpleCPU', 'TimingSimpleCPU', 'MinorCPU', 'DerivO3CPU'),
}