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authorGabe Black <gblack@eecs.umich.edu>2008-06-12 00:54:12 -0400
committerGabe Black <gblack@eecs.umich.edu>2008-06-12 00:54:12 -0400
commit6b8d0363ee271a1b36dd03e3bac5e62efc52aad4 (patch)
tree3a4d71f9ebb2cdc968708b13c9f6ad764e368cbf
parentb10742ee2b01213999ba9a3706093f5946097341 (diff)
downloadgem5-6b8d0363ee271a1b36dd03e3bac5e62efc52aad4.tar.xz
X86: Rename the divide count register to divide configuration.
-rw-r--r--src/arch/x86/miscregfile.cc7
-rw-r--r--src/arch/x86/miscregs.hh4
-rw-r--r--src/arch/x86/tlb.cc2
3 files changed, 5 insertions, 8 deletions
diff --git a/src/arch/x86/miscregfile.cc b/src/arch/x86/miscregfile.cc
index 1e02391e6..64dac6147 100644
--- a/src/arch/x86/miscregfile.cc
+++ b/src/arch/x86/miscregfile.cc
@@ -158,9 +158,6 @@ MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
case MISCREG_APIC_CURRENT_COUNT:
panic("Local APIC Current Count register unimplemented.\n");
break;
- case MISCREG_APIC_DIVIDE_COUNT:
- panic("Local APIC Divide Count register unimplemented.\n");
- break;
}
}
switch (miscReg) {
@@ -270,8 +267,8 @@ void MiscRegFile::setReg(int miscReg,
case MISCREG_APIC_CURRENT_COUNT:
panic("Local APIC Current Count register unimplemented.\n");
break;
- case MISCREG_APIC_DIVIDE_COUNT:
- panic("Local APIC Divide Count register unimplemented.\n");
+ case MISCREG_APIC_DIVIDE_CONFIGURATION:
+ newVal = val & 0xB;
break;
}
setRegNoEffect(miscReg, newVal);
diff --git a/src/arch/x86/miscregs.hh b/src/arch/x86/miscregs.hh
index caa1e817b..5a6ee752d 100644
--- a/src/arch/x86/miscregs.hh
+++ b/src/arch/x86/miscregs.hh
@@ -397,8 +397,8 @@ namespace X86ISA
MISCREG_APIC_LVT_ERROR,
MISCREG_APIC_INITIAL_COUNT,
MISCREG_APIC_CURRENT_COUNT,
- MISCREG_APIC_DIVIDE_COUNT,
- MISCREG_APIC_END = MISCREG_APIC_DIVIDE_COUNT,
+ MISCREG_APIC_DIVIDE_CONFIGURATION,
+ MISCREG_APIC_END = MISCREG_APIC_DIVIDE_CONFIGURATION,
MISCREG_APIC_INTERNAL_STATE,
diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index ba8f63a0e..692d6d022 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -780,7 +780,7 @@ TLB::translate(RequestPtr &req, ThreadContext *tc, bool write, bool execute)
regNum = MISCREG_APIC_CURRENT_COUNT;
break;
case 0x3E0:
- regNum = MISCREG_APIC_DIVIDE_COUNT;
+ regNum = MISCREG_APIC_DIVIDE_CONFIGURATION;
break;
default:
// A reserved register field.