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| author | Jack Whitman <jack-m5ml2@cs.york.ac.uk> | 2009-06-23 23:23:25 -0700 |
|---|---|---|
| committer | Jack Whitman <jack-m5ml2@cs.york.ac.uk> | 2009-06-23 23:23:25 -0700 |
| commit | 6dd42728040751dec6f83d7bd89a2b33f2339fc6 (patch) | |
| tree | fc3525af49967dced6f40e66451150d11c35b203 | |
| parent | fa63af110c69ef56b2d0ca98f79b480250d24835 (diff) | |
| download | gem5-6dd42728040751dec6f83d7bd89a2b33f2339fc6.tar.xz | |
ARM: Added unimplemented load/store multiple instructions.
| -rw-r--r-- | src/arch/arm/isa/formats/macromem.isa | 25 |
1 files changed, 9 insertions, 16 deletions
diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa index 942c444fd..df52f9413 100644 --- a/src/arch/arm/isa/formats/macromem.isa +++ b/src/arch/arm/isa/formats/macromem.isa @@ -58,44 +58,37 @@ inline %(class_name)s::%(class_name)s(ExtMachInst machInst) switch (puswl) { + case 0x00: // stmda case 0x01: // L ldmda_l - start_addr = (ones << 2) - 4; - end_addr = 0; - break; + case 0x02: // W stmda_w case 0x03: // WL ldmda_wl start_addr = (ones << 2) - 4; end_addr = 0; break; case 0x08: // U stmia_u - start_addr = 0; - end_addr = (ones << 2) - 4; - break; case 0x09: // U L ldmia_ul - start_addr = 0; - end_addr = (ones << 2) - 4; - break; + case 0x0a: // U W stmia case 0x0b: // U WL ldmia start_addr = 0; end_addr = (ones << 2) - 4; break; + case 0x10: // P stmdb case 0x11: // P L ldmdb - start_addr = (ones << 2); // U-bit is already 0 for subtract - end_addr = 4; // negative 4 - break; case 0x12: // P W stmdb + case 0x13: // P WL ldmdb start_addr = (ones << 2); // U-bit is already 0 for subtract end_addr = 4; // negative 4 break; case 0x18: // PU stmib - start_addr = 4; - end_addr = (ones << 2) + 4; - break; case 0x19: // PU L ldmib + case 0x1a: // PU W stmib + case 0x1b: // PU WL ldmib start_addr = 4; end_addr = (ones << 2) + 4; break; default: - panic("Unhandled Load/Store Multiple Instruction"); + panic("Unhandled Load/Store Multiple Instruction, " + "puswl = 0x%x", (unsigned) puswl); break; } |