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author | Gabe Black <gblack@eecs.umich.edu> | 2006-10-15 20:37:28 -0400 |
---|---|---|
committer | Gabe Black <gblack@eecs.umich.edu> | 2006-10-15 20:37:28 -0400 |
commit | 7009d0e52339036e1b282b15a29e71863ada020c (patch) | |
tree | 57f315b91a0a3302ff574dc3b2070aae90b2176b | |
parent | 92fd211a07356a9dec8cb822675c359355e22621 (diff) | |
download | gem5-7009d0e52339036e1b282b15a29e71863ada020c.tar.xz |
Fix how additional template parameters are handled. Non string parameters are not processed as code.
src/arch/isa_parser.py:
Changed the way the extra template parameters are specified. MIPS might need to be adjusted.
src/arch/sparc/isa/decoder.isa:
Changed how Frd_N was set up.
src/arch/sparc/isa/formats/blockmem.isa:
Fixed up handling of block memory operations
src/arch/sparc/isa/formats/integerop.isa:
src/arch/sparc/isa/formats/mem.isa:
src/arch/sparc/isa/formats/priv.isa:
Fix up extra template parameters.
--HG--
extra : convert_revision : ebf850d192193521bb84ca36b577051f74338d23
-rwxr-xr-x | src/arch/isa_parser.py | 18 | ||||
-rw-r--r-- | src/arch/sparc/isa/decoder.isa | 2 | ||||
-rw-r--r-- | src/arch/sparc/isa/formats/blockmem.isa | 46 | ||||
-rw-r--r-- | src/arch/sparc/isa/formats/integerop.isa | 6 | ||||
-rw-r--r-- | src/arch/sparc/isa/formats/mem.isa | 8 | ||||
-rw-r--r-- | src/arch/sparc/isa/formats/priv.isa | 4 |
6 files changed, 52 insertions, 32 deletions
diff --git a/src/arch/isa_parser.py b/src/arch/isa_parser.py index 4d522e18a..b235398f1 100755 --- a/src/arch/isa_parser.py +++ b/src/arch/isa_parser.py @@ -1636,7 +1636,7 @@ opClassRE = re.compile(r'.*Op|No_OpClass') class InstObjParams: def __init__(self, mnem, class_name, base_class = '', - code = None, opt_args = [], *extras): + code = None, opt_args = [], extras = {}): self.mnemonic = mnem self.class_name = class_name self.base_class = base_class @@ -1648,13 +1648,23 @@ class InstObjParams: else: origCode = code codeBlock = CodeBlock(code) - compositeCode = '\n'.join([origCode] + - [pair[1] for pair in extras]) + stringExtras = {} + otherExtras = {} + for (k, v) in extras.items(): + if type(v) == str: + stringExtras[k] = v + else: + otherExtras[k] = v + compositeCode = "\n".join([origCode] + stringExtras.values()) + # compositeCode = '\n'.join([origCode] + + # [pair[1] for pair in extras]) compositeBlock = CodeBlock(compositeCode) for code_attr in compositeBlock.__dict__.keys(): setattr(self, code_attr, getattr(compositeBlock, code_attr)) - for (key, snippet) in extras: + for (key, snippet) in stringExtras.items(): setattr(self, key, CodeBlock(snippet).code) + for (key, item) in otherExtras.items(): + setattr(self, key, item) self.code = codeBlock.code self.orig_code = origCode else: diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa index 7c135a637..03d31449c 100644 --- a/src/arch/sparc/isa/decoder.isa +++ b/src/arch/sparc/isa/decoder.isa @@ -951,7 +951,7 @@ decode OP default Unknown::unknown() //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE 0x1F: FailUnimpl::ldblockf_aiusl(); //ASI_BLOCK_PRIMARY - 0xF0: ldblockf_p({{Frd_%(micro_pc)d = Mem.udw}}); + 0xF0: ldblockf_p({{Frd_N = Mem.udw;}}); //ASI_BLOCK_SECONDARY 0xF1: FailUnimpl::ldblockf_s(); //ASI_BLOCK_PRIMARY_LITTLE diff --git a/src/arch/sparc/isa/formats/blockmem.isa b/src/arch/sparc/isa/formats/blockmem.isa index b3e99ed9a..abf5a3e52 100644 --- a/src/arch/sparc/isa/formats/blockmem.isa +++ b/src/arch/sparc/isa/formats/blockmem.isa @@ -167,8 +167,10 @@ def template BlockMemDeclare {{ //Constructor %(class_name)s(MachInst machInst); + protected: class %(class_name)s_0 : public %(base_class)sMicro { + public: //Constructor %(class_name)s_0(MachInst machInst) : %(base_class)sMicro("%(mnemonic)s[0]", @@ -179,6 +181,7 @@ def template BlockMemDeclare {{ class %(class_name)s_1 : public %(base_class)sMicro { + public: //Constructor %(class_name)s_1(MachInst machInst) : %(base_class)sMicro("%(mnemonic)s[1]", @@ -189,6 +192,7 @@ def template BlockMemDeclare {{ class %(class_name)s_2 : public %(base_class)sMicro { + public: //Constructor %(class_name)s_2(MachInst machInst) : %(base_class)sMicro("%(mnemonic)s[2]", @@ -199,6 +203,7 @@ def template BlockMemDeclare {{ class %(class_name)s_3 : public %(base_class)sMicro { + public: //Constructor %(class_name)s_3(MachInst machInst) : %(base_class)sMicro("%(mnemonic)s[3]", @@ -209,6 +214,7 @@ def template BlockMemDeclare {{ class %(class_name)s_4 : public %(base_class)sMicro { + public: //Constructor %(class_name)s_4(MachInst machInst) : %(base_class)sMicro("%(mnemonic)s[4]", @@ -219,6 +225,7 @@ def template BlockMemDeclare {{ class %(class_name)s_5 : public %(base_class)sMicro { + public: //Constructor %(class_name)s_5(MachInst machInst) : %(base_class)sMicro("%(mnemonic)s[5]", @@ -229,6 +236,7 @@ def template BlockMemDeclare {{ class %(class_name)s_6 : public %(base_class)sMicro { + public: //Constructor %(class_name)s_6(MachInst machInst) : %(base_class)sMicro("%(mnemonic)s[6]", @@ -239,6 +247,7 @@ def template BlockMemDeclare {{ class %(class_name)s_7 : public %(base_class)sMicro { + public: //Constructor %(class_name)s_7(MachInst machInst) : %(base_class)sMicro("%(mnemonic)s[7]", @@ -257,15 +266,14 @@ def template BlockMemConstructor {{ : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s) { %(constructor)s; - microOps = - {new %(class_name)s_0(machInst), - new %(class_name)s_1(machInst), - new %(class_name)s_2(machInst), - new %(class_name)s_3(machInst), - new %(class_name)s_4(machInst), - new %(class_name)s_5(machInst), - new %(class_name)s_6(machInst), - new %(class_name)s_7(machInst)} + microOps[0] = new %(class_name)s_0(machInst); + microOps[1] = new %(class_name)s_1(machInst); + microOps[2] = new %(class_name)s_2(machInst); + microOps[3] = new %(class_name)s_3(machInst); + microOps[4] = new %(class_name)s_4(machInst); + microOps[5] = new %(class_name)s_5(machInst); + microOps[6] = new %(class_name)s_6(machInst); + microOps[7] = new %(class_name)s_7(machInst); } }}; @@ -334,19 +342,21 @@ let {{ return new MemAddressNotAligned;''' addrCalcReg = 'EA = Rs1 + Rs2 + offset;' addrCalcImm = 'EA = Rs1 + imm + offset;' - iop = InstObjParams(name, Name, 'Mem', code, opt_flags) - iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code, opt_flags) + iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags) + iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags) header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm) decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm) decode_block = ROrImmDecode.subst(iop) + matcher = re.compile(r'Frd_N') + exec_output = '' for microPC in range(8): - pcedCode = code % ("micro_pc", microPC) - iop = InstObjParams(name, Name, 'Mem', pcedCode, - opt_flags, ("ea_code", addrCalcReg), - ("fault_check", faultCheck), ("micro_pc", microPC)) - iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', pcedCode, - opt_flags, ("ea_code", addrCalcImm), - ("fault_check", faultCheck), ("micro_pc", microPC)) + pcedCode = matcher.sub("Frd_%d" % microPC, code) + iop = InstObjParams(name, Name, 'BlockMem', pcedCode, + opt_flags, {"ea_code": addrCalcReg, + "fault_check": faultCheck, "micro_pc": microPC}) + iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', pcedCode, + opt_flags, {"ea_code": addrCalcImm, + "fault_check": faultCheck, "micro_pc": microPC}) exec_output += execute.subst(iop) exec_output += execute.subst(iop_imm) faultCheck = '' diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa index 0304a1064..4f8ebebcc 100644 --- a/src/arch/sparc/isa/formats/integerop.isa +++ b/src/arch/sparc/isa/formats/integerop.isa @@ -264,13 +264,13 @@ let {{ (usesImm, code, immCode, rString, iString) = splitOutImm(code) iop = InstObjParams(name, Name, 'IntOp', code, - opt_flags, ("cc_code", ccCode)) + opt_flags, {"cc_code": ccCode}) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) exec_output = IntOpExecute.subst(iop) if usesImm: imm_iop = InstObjParams(name, Name + 'Imm', 'IntOpImm' + iString, - immCode, opt_flags, ("cc_code", ccCode)) + immCode, opt_flags, {"cc_code": ccCode}) header_output += BasicDeclare.subst(imm_iop) decoder_output += BasicConstructor.subst(imm_iop) exec_output += IntOpExecute.subst(imm_iop) @@ -341,7 +341,7 @@ def format IntOpCcRes(code, *opt_flags) {{ def format SetHi(code, *opt_flags) {{ iop = InstObjParams(name, Name, 'SetHi', - code, opt_flags, ("cc_code", '')) + code, opt_flags, {"cc_code": ''}) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) exec_output = IntOpExecute.subst(iop) diff --git a/src/arch/sparc/isa/formats/mem.isa b/src/arch/sparc/isa/formats/mem.isa index 88d39d890..b046bdd1c 100644 --- a/src/arch/sparc/isa/formats/mem.isa +++ b/src/arch/sparc/isa/formats/mem.isa @@ -188,11 +188,11 @@ let {{ addrCalcReg = 'EA = Rs1 + Rs2;' addrCalcImm = 'EA = Rs1 + imm;' iop = InstObjParams(name, Name, 'Mem', code, - opt_flags, ("ea_code", addrCalcReg), - ("priv_check", priv)) + opt_flags, {"ea_code": addrCalcReg, + "priv_check": priv}) iop_imm = InstObjParams(name, Name + 'Imm', 'MemImm', code, - opt_flags, ("ea_code", addrCalcImm), - ("priv_check", priv)) + opt_flags, {"ea_code": addrCalcImm, + "priv_check": priv}) header_output = BasicDeclare.subst(iop) + BasicDeclare.subst(iop_imm) decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm) decode_block = ROrImmDecode.subst(iop) diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa index d7ee01519..2a38422a7 100644 --- a/src/arch/sparc/isa/formats/priv.isa +++ b/src/arch/sparc/isa/formats/priv.isa @@ -103,13 +103,13 @@ let {{ (usesImm, code, immCode, rString, iString) = splitOutImm(code) iop = InstObjParams(name, Name, 'Priv', code, - opt_flags, ("check", checkCode)) + opt_flags, {"check": checkCode}) header_output = BasicDeclare.subst(iop) decoder_output = BasicConstructor.subst(iop) exec_output = PrivExecute.subst(iop) if usesImm: imm_iop = InstObjParams(name, Name + 'Imm', 'PrivImm', - immCode, opt_flags, ("check", checkCode)) + immCode, opt_flags, {"check": checkCode}) header_output += BasicDeclare.subst(imm_iop) decoder_output += BasicConstructor.subst(imm_iop) exec_output += PrivExecute.subst(imm_iop) |