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authorGabe Black <gblack@eecs.umich.edu>2006-10-16 15:53:48 -0400
committerGabe Black <gblack@eecs.umich.edu>2006-10-16 15:53:48 -0400
commit7fefa2a62111e6dd91d954e3d181244323333892 (patch)
tree07dd32d55717ce3b669320ed45cd07e7e4c96686
parent546dff6b6a14cb69770769732873f72e68311ab1 (diff)
downloadgem5-7fefa2a62111e6dd91d954e3d181244323333892.tar.xz
Changed how floating point register numbers are decoded to fit with the spec.
--HG-- extra : convert_revision : 155f48c84d06619c9c1c43375beb9d0a1c7495c9
-rw-r--r--src/arch/sparc/isa/decoder.isa40
-rw-r--r--src/arch/sparc/isa/operands.isa37
2 files changed, 46 insertions, 31 deletions
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 03d31449c..16f46b715 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -441,7 +441,7 @@ decode OP default Unknown::unknown()
0x34: decode OPF{
format BasicOperate{
0x01: fmovs({{
- Frd.uw = Frs2.uw;
+ Frds.uw = Frs2s.uw;
//fsr.ftt = fsr.cexc = 0
Fsr &= ~(7 << 14);
Fsr &= ~(0x1F);
@@ -454,7 +454,7 @@ decode OP default Unknown::unknown()
}});
0x03: Trap::fmovq({{fault = new FpDisabled;}});
0x05: fnegs({{
- Frd.uw = Frs2.uw ^ (1UL << 31);
+ Frds.uw = Frs2s.uw ^ (1UL << 31);
//fsr.ftt = fsr.cexc = 0
Fsr &= ~(7 << 14);
Fsr &= ~(0x1F);
@@ -467,7 +467,7 @@ decode OP default Unknown::unknown()
}});
0x07: Trap::fnegq({{fault = new FpDisabled;}});
0x09: fabss({{
- Frd.uw = ((1UL << 31) - 1) & Frs2.uw;
+ Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
//fsr.ftt = fsr.cexc = 0
Fsr &= ~(7 << 14);
Fsr &= ~(0x1F);
@@ -479,55 +479,55 @@ decode OP default Unknown::unknown()
Fsr &= ~(0x1F);
}});
0x0B: Trap::fabsq({{fault = new FpDisabled;}});
- 0x29: fsqrts({{Frd.sf = sqrt(Frs2.sf);}});
+ 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
- 0x41: fadds({{Frd.sf = Frs1.sf + Frs2.sf;}});
+ 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
0x43: Trap::faddq({{fault = new FpDisabled;}});
- 0x45: fsubs({{Frd.sf = Frs1.sf - Frs2.sf;}});
+ 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
0x47: Trap::fsubq({{fault = new FpDisabled;}});
- 0x49: fmuls({{Frd.sf = Frs1.sf * Frs2.sf;}});
+ 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
0x4B: Trap::fmulq({{fault = new FpDisabled;}});
- 0x4D: fdivs({{Frd.sf = Frs1.sf / Frs2.sf;}});
+ 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
0x4F: Trap::fdivq({{fault = new FpDisabled;}});
- 0x69: fsmuld({{Frd.df = Frs1.sf * Frs2.sf;}});
+ 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
0x81: fstox({{
- Frd.df = (double)static_cast<int64_t>(Frs2.sf);
+ Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
}});
0x82: fdtox({{
Frd.df = (double)static_cast<int64_t>(Frs2.df);
}});
0x83: Trap::fqtox({{fault = new FpDisabled;}});
0x84: fxtos({{
- Frd.sf = static_cast<float>((int64_t)Frs2.df);
+ Frds.sf = static_cast<float>((int64_t)Frs2.df);
}});
0x88: fxtod({{
Frd.df = static_cast<double>((int64_t)Frs2.df);
}});
0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
0xC4: fitos({{
- Frd.sf = static_cast<float>((int32_t)Frs2.sf);
+ Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
}});
- 0xC6: fdtos({{Frd.sf = Frs2.df;}});
+ 0xC6: fdtos({{Frds.sf = Frs2.df;}});
0xC7: Trap::fqtos({{fault = new FpDisabled;}});
0xC8: fitod({{
- Frd.df = static_cast<double>((int32_t)Frs2.sf);
+ Frd.df = static_cast<double>((int32_t)Frs2s.sf);
}});
- 0xC9: fstod({{Frd.df = Frs2.sf;}});
+ 0xC9: fstod({{Frd.df = Frs2s.sf;}});
0xCB: Trap::fqtod({{fault = new FpDisabled;}});
0xCC: Trap::fitoq({{fault = new FpDisabled;}});
0xCD: Trap::fstoq({{fault = new FpDisabled;}});
0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
0xD1: fstoi({{
- Frd.sf = (float)static_cast<int32_t>(Frs2.sf);
+ Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
}});
0xD2: fdtoi({{
- Frd.sf = (float)static_cast<int32_t>(Frs2.df);
+ Frds.sf = (float)static_cast<int32_t>(Frs2.df);
}});
0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
default: Trap::fpop1({{fault = new FpDisabled;}});
@@ -620,7 +620,7 @@ decode OP default Unknown::unknown()
0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
0x60: BasicOperate::fzero({{Frd.df = 0;}});
- 0x61: BasicOperate::fzeros({{Frd.sf = 0;}});
+ 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
0x62: Trap::fnor({{fault = new IllegalInstruction;}});
0x63: Trap::fnors({{fault = new IllegalInstruction;}});
0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
@@ -629,7 +629,7 @@ decode OP default Unknown::unknown()
Frd.df = (double)(~((uint64_t)Frs2.df));
}});
0x67: BasicOperate::fnot2s({{
- Frd.sf = (float)(~((uint32_t)Frs2.sf));
+ Frds.sf = (float)(~((uint32_t)Frs2s.sf));
}});
0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
@@ -637,7 +637,7 @@ decode OP default Unknown::unknown()
Frd.df = (double)(~((uint64_t)Frs1.df));
}});
0x6B: BasicOperate::fnot1s({{
- Frd.sf = (float)(~((uint32_t)Frs1.sf));
+ Frds.sf = (float)(~((uint32_t)Frs1s.sf));
}});
0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
diff --git a/src/arch/sparc/isa/operands.isa b/src/arch/sparc/isa/operands.isa
index b01443d5b..9dcd73598 100644
--- a/src/arch/sparc/isa/operands.isa
+++ b/src/arch/sparc/isa/operands.isa
@@ -42,6 +42,16 @@ def operand_types {{
'qf' : ('float', 128)
}};
+output header {{
+ // A function to "decompress" double and quad floating point
+ // register numbers stuffed into 5 bit fields. These have their
+ // MSB put in the LSB position but are otherwise normal.
+ static inline unsigned int dfpr(unsigned int regNum)
+ {
+ return regNum | ((regNum & 1) << 5);
+ }
+}};
+
def operands {{
# Int regs default to unsigned, but code should not count on this.
# For clarity, descriptions that depend on unsigned behavior should
@@ -51,17 +61,22 @@ def operands {{
'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 3),
'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 4),
'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 5),
- 'Frd': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
- 'Frd_0': ('FloatReg', 'df', 'RD', 'IsFloating', 10),
- 'Frd_1': ('FloatReg', 'df', 'RD + 1', 'IsFloating', 10),
- 'Frd_2': ('FloatReg', 'df', 'RD + 2', 'IsFloating', 10),
- 'Frd_3': ('FloatReg', 'df', 'RD + 3', 'IsFloating', 10),
- 'Frd_4': ('FloatReg', 'df', 'RD + 4', 'IsFloating', 10),
- 'Frd_5': ('FloatReg', 'df', 'RD + 5', 'IsFloating', 10),
- 'Frd_6': ('FloatReg', 'df', 'RD + 6', 'IsFloating', 10),
- 'Frd_7': ('FloatReg', 'df', 'RD + 7', 'IsFloating', 10),
- 'Frs1': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
- 'Frs2': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
+ 'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
+ 'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+ # Each Frd_N refers to the Nth double precision register from Frd.
+ # Note that this adds twice N to the register number.
+ 'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
+ 'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
+ 'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
+ 'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
+ 'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
+ 'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
+ 'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
+ 'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
+ 'Frs1s': ('FloatReg', 'df', 'RS1', 'IsFloating', 11),
+ 'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
+ 'Frs2s': ('FloatReg', 'df', 'RS2', 'IsFloating', 12),
+ 'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
'Mem': ('Mem', 'udw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 20),
'NPC': ('NPC', 'udw', None, ( None, None, 'IsControl' ), 31),
'NNPC': ('NNPC', 'udw', None, (None, None, 'IsControl' ), 32),