diff options
| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:19 -0700 |
| commit | 826a3582ea92ea1fe2597a6cfb6853626d3c808e (patch) | |
| tree | 1dcda813bbab13f17501f4bdafc2bc105365a1ad | |
| parent | 17f0943398fb403c189dc3f6f4d0d834d56f061c (diff) | |
| download | gem5-826a3582ea92ea1fe2597a6cfb6853626d3c808e.tar.xz | |
ARM: Don't always update CPSR.
| -rw-r--r-- | src/arch/arm/isa/formats/mem.isa | 3 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/util.isa | 1 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa index a154cac60..41fd0552c 100644 --- a/src/arch/arm/isa/formats/mem.isa +++ b/src/arch/arm/isa/formats/mem.isa @@ -354,7 +354,8 @@ def template StoreCompleteAcc {{ { Fault fault = NoFault; - %(op_dest_decl)s; + %(op_decl)s; + %(op_rd)s; if (%(predicate_test)s) { diff --git a/src/arch/arm/isa/formats/util.isa b/src/arch/arm/isa/formats/util.isa index 5caab642c..ac2e077ba 100644 --- a/src/arch/arm/isa/formats/util.isa +++ b/src/arch/arm/isa/formats/util.isa @@ -35,7 +35,6 @@ def ArmGenericCodeSubs(code): # Substitute in the shifted portion of operations new_code = re.sub(r'Rm_Imm', 'shift_rm_imm(Rm, shift_size, shift, Cpsr<29:>)', code) new_code = re.sub(r'Rm_Rs', 'shift_rm_rs(Rm, Rs, shift, Cpsr<29:>)', new_code) - new_code = re.sub(r'^', 'Cpsr = Cpsr;', new_code) return new_code def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags, |