summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorNathan Binkert <binkertn@umich.edu>2004-10-23 13:11:42 -0400
committerNathan Binkert <binkertn@umich.edu>2004-10-23 13:11:42 -0400
commit833c5b5ef49b4b0ff6c1736b71b6149feee50cb5 (patch)
treec742e27ffdc72389431f40d1df0c4fe22cc6b293
parent656031b0735e27933d48f30b1c756eb45bc8b516 (diff)
downloadgem5-833c5b5ef49b4b0ff6c1736b71b6149feee50cb5.tar.xz
get rid of some unused variables
--HG-- extra : convert_revision : 187cee0e0bad09bbaff059eb60f20d7d32c1b52c
-rw-r--r--dev/ide_ctrl.cc3
-rw-r--r--dev/ns_gige.cc2
-rw-r--r--dev/tsunami.hh5
3 files changed, 1 insertions, 9 deletions
diff --git a/dev/ide_ctrl.cc b/dev/ide_ctrl.cc
index dbec6d743..787049533 100644
--- a/dev/ide_ctrl.cc
+++ b/dev/ide_ctrl.cc
@@ -63,9 +63,6 @@ IdeController::IdeController(const string &name, IntrControl *ic,
Bus *host_bus, Tick pio_latency, HierParams *hier)
: PciDev(name, mmu, cf, cd, bus_num, dev_num, func_num), tsunami(t)
{
- // put back pointer into Tsunami
- tsunami->disk_controller = this;
-
// initialize the PIO interface addresses
pri_cmd_addr = 0;
pri_cmd_size = BARSize[0];
diff --git a/dev/ns_gige.cc b/dev/ns_gige.cc
index 8eb41e5cc..3e55cf52f 100644
--- a/dev/ns_gige.cc
+++ b/dev/ns_gige.cc
@@ -119,8 +119,6 @@ NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
physmem(pmem), intctrl(i), intrTick(0), cpuPendingIntr(false),
intrEvent(0), interface(0)
{
- tsunami->ethernet = this;
-
if (header_bus) {
pioInterface = newPioInterface(name, hier, header_bus, this,
&NSGigE::cacheAccess);
diff --git a/dev/tsunami.hh b/dev/tsunami.hh
index db266d62d..4367383ff 100644
--- a/dev/tsunami.hh
+++ b/dev/tsunami.hh
@@ -62,12 +62,9 @@ class Tsunami : public Platform
/** Pointer to the system */
System *system;
+
/** Pointer to the TsunamiIO device which has the RTC */
TsunamiIO *io;
- /** Pointer to the disk controller device */
- IdeController *disk_controller;
- /** Pointer to the ethernet controller device */
- NSGigE *ethernet;
/** Pointer to the Tsunami CChip.
* The chip contains some configuration information and