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authorKevin Lim <ktlim@umich.edu>2006-06-01 15:40:06 -0400
committerKevin Lim <ktlim@umich.edu>2006-06-01 15:40:06 -0400
commit8671d927d862cdbdf851e74cd07d131679faa7ed (patch)
tree7799eb5c4466129d2a9353278054424f1c08c8ae
parent51ed3c3fd9f91a686bf87256c966991e6c57c1ff (diff)
downloadgem5-8671d927d862cdbdf851e74cd07d131679faa7ed.tar.xz
Add in comments for checker.
--HG-- extra : convert_revision : 8921907af0f18313bc66ad2a584fc182526fe1a2
-rw-r--r--cpu/checker/cpu.hh23
-rw-r--r--cpu/checker/cpu_builder.cc30
-rw-r--r--cpu/checker/exec_context.hh7
-rw-r--r--cpu/checker/o3_cpu_builder.cc30
4 files changed, 89 insertions, 1 deletions
diff --git a/cpu/checker/cpu.hh b/cpu/checker/cpu.hh
index 37fe59d95..9fcd1037f 100644
--- a/cpu/checker/cpu.hh
+++ b/cpu/checker/cpu.hh
@@ -64,13 +64,28 @@ class MemInterface;
class Checkpoint;
class Sampler;
+/**
+ * CheckerCPU class. Dynamically verifies instructions as they are
+ * completed by making sure that the instruction and its results match
+ * the independent execution of the benchmark inside the checker. The
+ * checker verifies instructions in order, regardless of the order in
+ * which instructions complete. There are certain results that can
+ * not be verified, specifically the result of a store conditional or
+ * the values of uncached accesses. In these cases, and with
+ * instructions marked as "IsUnverifiable", the checker assumes that
+ * the value from the main CPU's execution is correct and simply
+ * copies that value. It provides a CheckerExecContext (see
+ * checker/exec_context.hh) that provides hooks for updating the
+ * Checker's state through any ExecContext accesses. This allows the
+ * checker to be able to correctly verify instructions, even with
+ * external accesses to the ExecContext that change state.
+ */
class CheckerCPU : public BaseCPU
{
protected:
typedef TheISA::MachInst MachInst;
typedef TheISA::MiscReg MiscReg;
public:
- // main simulation loop (one cycle)
virtual void init();
struct Params : public BaseCPU::Params
@@ -301,6 +316,12 @@ class CheckerCPU : public BaseCPU
InstSeqNum youngestSN;
};
+/**
+ * Templated Checker class. This Checker class is templated on the
+ * DynInstPtr of the instruction type that will be verified. Proper
+ * template instantiations of the Checker must be placed at the bottom
+ * of checker/cpu.cc.
+ */
template <class DynInstPtr>
class Checker : public CheckerCPU
{
diff --git a/cpu/checker/cpu_builder.cc b/cpu/checker/cpu_builder.cc
index 397ccab14..d80daef97 100644
--- a/cpu/checker/cpu_builder.cc
+++ b/cpu/checker/cpu_builder.cc
@@ -1,3 +1,30 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
#include <string>
@@ -10,6 +37,9 @@
#include "sim/process.hh"
#include "sim/sim_object.hh"
+/**
+ * Specific non-templated derived class used for SimObject configuration.
+ */
class OzoneChecker : public Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >
{
public:
diff --git a/cpu/checker/exec_context.hh b/cpu/checker/exec_context.hh
index 38784867d..9f9fb0fd6 100644
--- a/cpu/checker/exec_context.hh
+++ b/cpu/checker/exec_context.hh
@@ -38,6 +38,13 @@ namespace Kernel {
class Statistics;
};
+/**
+ * Derived ExecContext class for use with the Checker. The template
+ * parameter is the ExecContext class used by the specific CPU being
+ * verified. This CheckerExecContext is then used by the main CPU in
+ * place of its usual ExecContext class. It handles updating the
+ * checker's state any time state is updated through the ExecContext.
+ */
template <class XC>
class CheckerExecContext : public ExecContext
{
diff --git a/cpu/checker/o3_cpu_builder.cc b/cpu/checker/o3_cpu_builder.cc
index 125bfa398..410f91352 100644
--- a/cpu/checker/o3_cpu_builder.cc
+++ b/cpu/checker/o3_cpu_builder.cc
@@ -1,3 +1,30 @@
+/*
+ * Copyright (c) 2006 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
#include <string>
@@ -10,6 +37,9 @@
#include "sim/process.hh"
#include "sim/sim_object.hh"
+/**
+ * Specific non-templated derived class used for SimObject configuration.
+ */
class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >
{
public: