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| author | Javier Setoain <javier.setoain@arm.com> | 2019-03-14 18:06:05 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-03-25 09:40:46 +0000 |
| commit | 8e1a1418188b96ad5f6b27ab82aa463fc95f4179 (patch) | |
| tree | 2fef7d24229e7c2ccea61ed13243237369a1b2bb | |
| parent | f838a332be4b98ddc039f388bef1e307567db37c (diff) | |
| download | gem5-8e1a1418188b96ad5f6b27ab82aa463fc95f4179.tar.xz | |
arch-arm: Add missing fall-through defaults
Change-Id: Ie64b83d754c4719a77c7788879be71304a9b786e
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17289
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andrea Mondelli <Andrea.Mondelli@ucf.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
| -rw-r--r-- | src/arch/arm/isa/formats/sve_2nd_level.isa | 4 | ||||
| -rw-r--r-- | src/arch/arm/isa/formats/sve_top_level.isa | 5 |
2 files changed, 9 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa index 3c5e01c6b..ff7e50ee5 100644 --- a/src/arch/arm/isa/formats/sve_2nd_level.isa +++ b/src/arch/arm/isa/formats/sve_2nd_level.isa @@ -118,6 +118,7 @@ namespace Aarch64 return new Unknown64(machInst); } } + break; } case 0x3: { @@ -532,6 +533,7 @@ namespace Aarch64 return new SveIndexII<int64_t>(machInst, zd, imm5, imm5b); } + break; } case 1: { // INDEX (scalar, immediate) @@ -552,6 +554,7 @@ namespace Aarch64 return new SveIndexRI<int64_t>(machInst, zd, zn, imm5); } + break; } case 2: { // INDEX (immediate, scalar) @@ -572,6 +575,7 @@ namespace Aarch64 return new SveIndexIR<int64_t>(machInst, zd, imm5, zm); } + break; } case 3: { // INDEX (scalars) diff --git a/src/arch/arm/isa/formats/sve_top_level.isa b/src/arch/arm/isa/formats/sve_top_level.isa index f4f1ab531..b8e1d468e 100644 --- a/src/arch/arm/isa/formats/sve_top_level.isa +++ b/src/arch/arm/isa/formats/sve_top_level.isa @@ -128,6 +128,7 @@ namespace Aarch64 return decodeSveIntArithUnaryPred(machInst); } } + break; } case 0x1: { @@ -166,6 +167,7 @@ namespace Aarch64 case 0x3: return decodeSveElemCount(machInst); } + break; } case 0x2: if (bits(machInst, 20)) { @@ -195,6 +197,7 @@ namespace Aarch64 case 0x3: return decodeSveSelVec(machInst); } + break; } case 0x4: return decodeSveIntCmpVec(machInst); @@ -279,6 +282,7 @@ namespace Aarch64 case 0x3: return decodeSveFpAccumReduc(machInst); } + break; } case 0x2: return decodeSveFpArithPred(machInst); @@ -286,6 +290,7 @@ namespace Aarch64 return decodeSveFpUnaryPred(machInst); } } + break; } case 0x3: return decodeSveFpFusedMulAdd(machInst); |