ARM: Make the decoder handle thumb instructions separately.

--HG--
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/armdecode.isa
rename : src/arch/arm/isa/decoder.isa => src/arch/arm/isa/thumbdecode.isa

3 files changed, 637 insertions, 533 deletions

diff --git a/src/arch/arm/isa/armdecode.isa b/src/arch/arm/isa/armdecode.isa
new file mode 100644
index 000000000..bf9438885
--- /dev/null
+++ b/src/arch/arm/isa/armdecode.isa
@@ -0,0 +1,574 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Copyright (c) 2007-2008 The Florida State University
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Stephen Hines
+
+////////////////////////////////////////////////////////////////////
+//
+// The actual ARM ISA decoder
+// --------------------------
+// The following instructions are specified in the ARM ISA
+// Specification. Decoding closely follows the style specified
+// in the ARM ISA specification document starting with Table B.1 or 3-1
+//
+//
+
+0: decode ENCODING {
+format DataOp {
+    0x0: decode SEVEN_AND_FOUR {
+        1: decode MISC_OPCODE {
+            0x9: decode PREPOST {
+                0: decode OPCODE {
+                    0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none);
+                    0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none);
+                    0x2: WarnUnimpl::umall();
+                    0x4: umull({{
+                        resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
+                        Rd = (uint32_t)(resTemp & 0xffffffff);
+                        Rn = (uint32_t)(resTemp >> 32);
+                    }}, llbit);
+                    0x5: smlal({{
+                        resTemp = ((int64_t)Rm) * ((int64_t)Rs);
+                        resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd);
+                        Rd = (uint32_t)(resTemp & 0xffffffff);
+                        Rn = (uint32_t)(resTemp >> 32);
+                    }}, llbit);
+                    0x6: smull({{
+                        resTemp = ((int64_t)(int32_t)Rm)*
+                                  ((int64_t)(int32_t)Rs);
+                        Rd = (int32_t)(resTemp & 0xffffffff);
+                        Rn = (int32_t)(resTemp >> 32);
+                    }}, llbit);
+                    0x7: umlal({{
+                        resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
+                        resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
+                        Rd = (uint32_t)(resTemp & 0xffffffff);
+                        Rn = (uint32_t)(resTemp >> 32);
+                    }}, llbit);
+                }
+                1: decode PUBWL {
+                    0x10: WarnUnimpl::swp();
+                    0x14: WarnUnimpl::swpb();
+                    0x18: WarnUnimpl::strex();
+                    0x19: WarnUnimpl::ldrex();
+                }
+            }
+            format AddrMode3 {
+                0xb: strh_ldrh(store, {{ Mem.uh = Rd; }},
+                               load,  {{ Rd = Mem.uh; }});
+                0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0);
+                                         Rdo = bits(Mem.ud, 63, 32); }},
+                                load, {{ Rd = Mem.sb; }});
+                0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) |
+                                                   (Rdo.ud << 32); }},
+                                load,  {{ Rd = Mem.sh; }});
+            }
+        }
+        0: decode IS_MISC {
+            0: decode OPCODE {
+                0x0: and({{ Rd = resTemp = Rn & op2; }});
+                0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
+                0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub);
+                0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb);
+                0x4: add({{ Rd = resTemp = Rn + op2; }}, add);
+                0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add);
+                0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub);
+                0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb);
+                0x8: tst({{ resTemp = Rn & op2; }});
+                0x9: teq({{ resTemp = Rn ^ op2; }});
+                0xa: cmp({{ resTemp = Rn - op2; }}, sub);
+                0xb: cmn({{ resTemp = Rn + op2; }}, add);
+                0xc: orr({{ Rd = resTemp = Rn | op2; }});
+                0xd: mov({{ Rd = resTemp = op2; }});
+                0xe: bic({{ Rd = resTemp = Rn & ~op2; }});
+                0xf: mvn({{ Rd = resTemp = ~op2; }});
+            }
+            1: decode MISC_OPCODE {
+                0x0: decode OPCODE {
+                    0x8: PredOp::mrs_cpsr({{
+                        Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
+                    }});
+                    0x9: decode USEIMM {
+                        // The mask field is the same as the RN index.
+                        0: PredOp::msr_cpsr_reg({{
+                            uint32_t newCpsr =
+                                cpsrWriteByInstr(Cpsr | CondCodes,
+                                                 Rm, RN, false);
+                            Cpsr = ~CondCodesMask & newCpsr;
+                            CondCodes = CondCodesMask & newCpsr;
+                        }});
+                        1: PredImmOp::msr_cpsr_imm({{
+                            uint32_t newCpsr =
+                                cpsrWriteByInstr(Cpsr | CondCodes,
+                                                 rotated_imm, RN, false);
+                            Cpsr = ~CondCodesMask & newCpsr;
+                            CondCodes = CondCodesMask & newCpsr;
+                        }});
+                    }
+                    0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
+                    0xb: decode USEIMM {
+                        // The mask field is the same as the RN index.
+                        0: PredOp::msr_spsr_reg({{
+                            Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
+                        }});
+                        1: PredImmOp::msr_spsr_imm({{
+                            Spsr = spsrWriteByInstr(Spsr, rotated_imm,
+                                                    RN, false);
+                        }});
+                    }
+                }
+                0x1: decode OPCODE {
+                    0x9: BranchExchange::bx({{ }});
+                    0xb: PredOp::clz({{
+                        Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
+                    }});
+                }
+                0x2: decode OPCODE {
+                    0x9: WarnUnimpl::bxj();
+                }
+                0x3: decode OPCODE {
+                    0x9: BranchExchange::blx({{ }}, Link);
+                }
+                0x5: decode OPCODE {
+                    0x8: WarnUnimpl::qadd();
+                    0x9: WarnUnimpl::qsub();
+                    0xa: WarnUnimpl::qdadd();
+                    0xb: WarnUnimpl::qdsub();
+                }
+                0x8: decode OPCODE {
+                    0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
+                    0x9: WarnUnimpl::smlalbb();
+                    0xa: WarnUnimpl::smlawb();
+                    0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none);
+                }
+                0xa: decode OPCODE {
+                    0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
+                    0x9: smulwb({{
+                        Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16);
+                    }}, none);
+                    0xa: WarnUnimpl::smlaltb();
+                    0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none);
+                }
+                0xc: decode OPCODE {
+                    0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
+                    0x9: WarnUnimpl::smlawt();
+                    0xa: WarnUnimpl::smlalbt();
+                    0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none);
+                }
+                0xe: decode OPCODE {
+                    0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
+                    0x9: smulwt({{
+                        Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16);
+                    }}, none);
+                    0xa: WarnUnimpl::smlaltt();
+                    0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none);
+                }
+            }
+        }
+    }
+    0x1: decode IS_MISC {
+        0: decode OPCODE {
+            format DataImmOp {
+                0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }});
+                0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }});
+                0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub);
+                0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb);
+                0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add);
+                0x5: adci({{
+                    Rd = resTemp = Rn + rotated_imm + CondCodes<29:>;
+                }}, add);
+                0x6: sbci({{
+                    Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>;
+                }}, sub);
+                0x7: rsci({{
+                    Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>;
+                }}, rsb);
+                0x8: tsti({{ resTemp = Rn & rotated_imm; }});
+                0x9: teqi({{ resTemp = Rn ^ rotated_imm; }});
+                0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub);
+                0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add);
+                0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }});
+                0xd: movi({{ Rd = resTemp = rotated_imm; }});
+                0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }});
+                0xf: mvni({{ Rd = resTemp = ~rotated_imm; }});
+            }
+        }
+        1: decode OPCODE {
+            // The following two instructions aren't supposed to be defined
+            0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
+            0x9: decode RN {
+                0: decode IMM {
+                    0: PredImmOp::nop({{ ; }});
+                    1: WarnUnimpl::yield();
+                    2: WarnUnimpl::wfe();
+                    3: WarnUnimpl::wfi();
+                    4: WarnUnimpl::sev();
+                }
+                default: PredImmOp::msr_i_cpsr({{
+                            uint32_t newCpsr =
+                                cpsrWriteByInstr(Cpsr | CondCodes,
+                                                 rotated_imm, RN, false);
+                            Cpsr = ~CondCodesMask & newCpsr;
+                            CondCodes = CondCodesMask & newCpsr;
+                }});
+            }
+            0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
+            0xb: PredImmOp::msr_i_spsr({{
+                       Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false);
+            }});
+        }
+    }
+    0x2: AddrMode2::addrMode2(Disp, disp);
+    0x3: decode OPCODE_4 {
+        0: AddrMode2::addrMode2(Shift, Rm_Imm);
+        1: decode MEDIA_OPCODE {
+            0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
+            0x8: decode MISC_OPCODE {
+                0x1, 0x9: WarnUnimpl::pkhbt();
+                0x7: WarnUnimpl::sxtab16();
+                0xb: WarnUnimpl::sel();
+                0x5, 0xd: WarnUnimpl::pkhtb();
+                0x3: WarnUnimpl::sign_zero_extend_add();
+            }
+            0xa, 0xb: decode SHIFT {
+                0x0, 0x2: WarnUnimpl::ssat();
+                0x1: WarnUnimpl::ssat16();
+            }
+            0xe, 0xf: decode SHIFT {
+                0x0, 0x2: WarnUnimpl::usat();
+                0x1: WarnUnimpl::usat16();
+            }
+            0x10: decode RN {
+                0xf: decode MISC_OPCODE {
+                    0x1: WarnUnimpl::smuad();
+                    0x3: WarnUnimpl::smuadx();
+                    0x5: WarnUnimpl::smusd();
+                    0x7: WarnUnimpl::smusdx();
+                }
+                default: decode MISC_OPCODE {
+                    0x1: WarnUnimpl::smlad();
+                    0x3: WarnUnimpl::smladx();
+                    0x5: WarnUnimpl::smlsd();
+                    0x7: WarnUnimpl::smlsdx();
+                }
+            }
+            0x14: decode MISC_OPCODE {
+                0x1: WarnUnimpl::smlald();
+                0x3: WarnUnimpl::smlaldx();
+                0x5: WarnUnimpl::smlsld();
+                0x7: WarnUnimpl::smlsldx();
+            }
+            0x15: decode RN {
+                0xf: decode MISC_OPCODE {
+                    0x1: WarnUnimpl::smmul();
+                    0x3: WarnUnimpl::smmulr();
+                }
+                default: decode MISC_OPCODE {
+                    0x1: WarnUnimpl::smmla();
+                    0x3: WarnUnimpl::smmlar();
+                    0xd: WarnUnimpl::smmls();
+                    0xf: WarnUnimpl::smmlsr();
+                }
+            }
+            0x18: decode RN {
+                0xf: WarnUnimpl::usada8();
+                default: WarnUnimpl::usad8();
+            }
+        }
+    }
+    0x4: decode PUSWL {
+        // Right now we only handle cases when S (PSRUSER) is not set
+        default: ArmMacroStore::ldmstm({{ }});
+    }
+    0x5: decode OPCODE_24 {
+        // Branch (and Link) Instructions
+        0: Branch::b({{ }});
+        1: Branch::bl({{ }}, Link);
+    }
+    0x6: decode CPNUM {
+        0x1: decode PUNWL {
+            0x02,0x0a: decode OPCODE_15 {
+                0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf;
+                                            Rn = Rn + disp8; }},
+                    {{ EA = Rn; }});
+                1: ArmMacroFPAOp::stfd_({{ }});
+            }
+            0x03,0x0b: decode OPCODE_15 {
+                0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf;
+                                           Rn = Rn + disp8; }},
+                    {{ EA = Rn; }});
+                1: ArmMacroFPAOp::ldfd_({{ }});
+            }
+            0x06,0x0e: decode OPCODE_15 {
+                0: ArmMacroFPAOp::stfe_nw({{ }});
+            }
+            0x07,0x0f: decode OPCODE_15 {
+                0: ArmMacroFPAOp::ldfe_nw({{ }});
+            }
+            0x10,0x18: decode OPCODE_15 {
+                0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }},
+                    {{ EA = Rn + disp8; }});
+                1: ArmMacroFPAOp::stfd_p({{ }});
+            }
+            0x11,0x19: decode OPCODE_15 {
+                0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }},
+                    {{ EA = Rn + disp8; }});
+                1: ArmMacroFPAOp::ldfd_p({{ }});
+            }
+            0x12,0x1a: decode OPCODE_15 {
+                0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf;
+                                              Rn = Rn + disp8; }},
+                    {{ EA = Rn + disp8; }});
+                1: ArmMacroFPAOp::stfd_pw({{ }});
+            }
+            0x13,0x1b: decode OPCODE_15 {
+                0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf;
+                                             Rn = Rn + disp8; }},
+                    {{ EA = Rn + disp8; }});
+                1: ArmMacroFPAOp::ldfd_pw({{ }});
+            }
+            0x14,0x1c: decode OPCODE_15 {
+                0: ArmMacroFPAOp::stfe_pn({{ }});
+            }
+            0x15,0x1d: decode OPCODE_15 {
+                0: ArmMacroFPAOp::ldfe_pn({{ }});
+            }
+            0x16,0x1e: decode OPCODE_15 {
+                0: ArmMacroFPAOp::stfe_pnw({{ }});
+            }
+            0x17,0x1f: decode OPCODE_15 {
+                0: ArmMacroFPAOp::ldfe_pnw({{ }});
+            }
+        }
+        0x2: decode PUNWL {
+            // could really just decode as a single instruction
+            0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }});
+            0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }});
+            0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }});
+            0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }});
+            0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }});
+            0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }});
+            0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }});
+            0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }});
+        }
+        0xb: decode LOADOP {
+            0x0: WarnUnimpl::fstmx();
+            0x1: WarnUnimpl::fldmx();
+        }
+    }
+    0x7: decode OPCODE_24 {
+        0: decode OPCODE_4 {
+            0: decode CPNUM {
+                format FloatOp {
+                    0x1: decode OPCODE_23_20 {
+                            0x0: decode OPCODE_15 {
+                                0: adf({{ Fd.sf = Fn.sf + Fm.sf; }});
+                                1: mvf({{ Fd.sf = Fm.sf; }});
+                            }
+                            0x1: decode OPCODE_15 {
+                                0: muf({{ Fd.sf = Fn.sf * Fm.sf; }});
+                                1: mnf({{ Fd.sf = -Fm.sf; }});
+                            }
+                            0x2: decode OPCODE_15 {
+                                0: suf({{ Fd.sf = Fn.sf - Fm.sf; }});
+                                1: abs({{ Fd.sf = fabs(Fm.sf); }});
+                            }
+                            0x3: decode OPCODE_15 {
+                                0: rsf({{ Fd.sf = Fm.sf - Fn.sf; }});
+                                1: rnd({{ Fd.sf = rint(Fm.sf); }});
+                            }
+                            0x4: decode OPCODE_15 {
+                                0: dvf({{ Fd.sf = Fn.sf / Fm.sf; }});
+                                1: sqt({{ Fd.sf = sqrt(Fm.sf); }});
+                            }
+                            0x5: decode OPCODE_15 {
+                                0: rdf({{ Fd.sf = Fm.sf / Fn.sf; }});
+                                1: log({{ Fd.sf = log10(Fm.sf); }});
+                            }
+                            0x6: decode OPCODE_15 {
+                                0: pow({{ Fd.sf = pow(Fm.sf, Fn.sf); }});
+                                1: lgn({{ Fd.sf = log(Fm.sf); }});
+                            }
+                            0x7: decode OPCODE_15 {
+                                0: rpw({{ Fd.sf = pow(Fn.sf, Fm.sf); }});
+                                1: exp({{ Fd.sf = exp(Fm.sf); }});
+                            }
+                            0x8: decode OPCODE_15 {
+                                0: rmf({{ Fd.sf = drem(Fn.sf, Fm.sf); }});
+                                1: sin({{ Fd.sf = sin(Fm.sf); }});
+                            }
+                            0x9: decode OPCODE_15 {
+                                0: fml({{ Fd.sf = Fn.sf * Fm.sf; }});
+                                1: cos({{ Fd.sf = cos(Fm.sf); }});
+                            }
+                            0xa: decode OPCODE_15 {
+                                0: fdv({{ Fd.sf = Fn.sf / Fm.sf; }});
+                                1: tan({{ Fd.sf = tan(Fm.sf); }});
+                            }
+                            0xb: decode OPCODE_15 {
+                                0: frd({{ Fd.sf = Fm.sf / Fn.sf; }});
+                                1: asn({{ Fd.sf = asin(Fm.sf); }});
+                            }
+                            0xc: decode OPCODE_15 {
+                                0: pol({{ Fd.sf = atan2(Fn.sf, Fm.sf); }});
+                                1: acs({{ Fd.sf = acos(Fm.sf); }});
+                            }
+                            0xd: decode OPCODE_15 {
+                                1: atn({{ Fd.sf = atan(Fm.sf); }});
+                            }
+                            0xe: decode OPCODE_15 {
+                                // Unnormalised Round
+                                1: FailUnimpl::urd();
+                            }
+                            0xf: decode OPCODE_15 {
+                                // Normalise
+                                1: FailUnimpl::nrm();
+                            }
+                    } // OPCODE_23_20
+                } // format FloatOp
+            } // CPNUM
+            1: decode CPNUM { // 27-24=1110,4 ==1
+                1: decode OPCODE_15_12 {
+                    format FloatOp {
+                        0xf: decode OPCODE_23_21 {
+                            format FloatCmp {
+                                0x4: cmf({{ Fn.df }}, {{ Fm.df }});
+                                0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
+                                0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
+                                0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
+                            }
+                        }
+                        default: decode OPCODE_23_20 {
+                            0x0: decode OPCODE_7 {
+                                0: flts({{ Fn.sf = (float) Rd.sw; }});
+                                1: fltd({{ Fn.df = (double) Rd.sw; }});
+                            }
+                            0x1: decode OPCODE_7 {
+                                0: fixs({{ Rd = (uint32_t) Fm.sf; }});
+                                1: fixd({{ Rd = (uint32_t) Fm.df; }});
+                            }
+                            0x2: wfs({{ Fpsr = Rd; }});
+                            0x3: rfs({{ Rd = Fpsr; }});
+                            0x4: FailUnimpl::wfc();
+                            0x5: FailUnimpl::rfc();
+                        }
+                    } // format FloatOp
+                }
+                0xa: decode MISC_OPCODE {
+                    0x1: decode MEDIA_OPCODE {
+                        0xf: decode RN {
+                            0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
+                            0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
+                            0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
+                        }
+                        0xe: decode RN {
+                            0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
+                            0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
+                            0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
+                        }
+                    } // MEDIA_OPCODE (MISC_OPCODE 0x1)
+                } // MISC_OPCODE (CPNUM 0xA)
+                0xf: decode RN {
+                    // Barrriers, Cache Maintence, NOPS
+                    7: decode OPCODE_23_21 {
+                        0: decode RM {
+                            0: decode OPC2 {
+                                4: decode OPCODE_20 {
+                                    0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
+                                }
+                            }
+                            1: WarnUnimpl::cp15_cache_maint();
+                            4: WarnUnimpl::cp15_par();
+                            5: decode OPC2 {
+                                0,1: WarnUnimpl::cp15_cache_maint2();
+                                4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
+                                6,7: WarnUnimpl::cp15_bp_maint();
+                            }
+                            6: WarnUnimpl::cp15_cache_maint3();
+                            8: WarnUnimpl::cp15_va_to_pa();
+                            10: decode OPC2 {
+                                1,2: WarnUnimpl::cp15_cache_maint3();
+                                4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
+                                5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
+                            }
+                            11: WarnUnimpl::cp15_cache_maint4();
+                            13: decode OPC2 {
+                                1: decode OPCODE_20 {
+                                    0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
+                                }
+                            }
+                            14: WarnUnimpl::cp15_cache_maint5();
+                        } // RM
+                    } // OPCODE_23_21 CR
+
+                    // Thread ID and context ID registers
+                    // Thread ID register needs cheaper access than miscreg
+                    13: WarnUnimpl::mcr_mrc_cp15_c7();
+
+                    // All the rest
+                    default: decode OPCODE_20 {
+                        0: PredOp::mcr_cp15({{
+                               fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
+                        }});
+                        1: PredOp::mrc_cp15({{
+                               fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2);
+                        }});
+                    }
+                }  // RN
+            } // CPNUM  (OP4 == 1)
+        } //OPCODE_4
+
+#if FULL_SYSTEM
+        1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
+#else
+        1: PredOp::swi({{ if (testPredicate(CondCodes, condCode))
+            {
+                if (IMMED_23_0)
+                    xc->syscall(IMMED_23_0);
+                else
+                    xc->syscall(R7);
+            }
+        }});
+#endif // FULL_SYSTEM
+    } // OPCODE_24
+
+}
+}
+
diff --git a/src/arch/arm/isa/decoder.isa b/src/arch/arm/isa/decoder.isa
index ff20c6107..3e711b655 100644
--- a/src/arch/arm/isa/decoder.isa
+++ b/src/arch/arm/isa/decoder.isa
@@ -1,6 +1,18 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2007-2008 The Florida State University
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Copyright (c) 2009 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -26,537 +38,9 @@
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 //
-// Authors: Stephen Hines
-
-////////////////////////////////////////////////////////////////////
-//
-// The actual ARM ISA decoder
-// --------------------------
-// The following instructions are specified in the ARM ISA
-// Specification. Decoding closely follows the style specified
-// in the ARM ISA specification document starting with Table B.1 or 3-1
-//
-//
-
-decode ENCODING default Unknown::unknown() {
-format DataOp {
-    0x0: decode SEVEN_AND_FOUR {
-        1: decode MISC_OPCODE {
-            0x9: decode PREPOST {
-                0: decode OPCODE {
-                    0x0: mul({{ Rn = resTemp = Rm * Rs; }}, none);
-                    0x1: mla({{ Rn = resTemp = (Rm * Rs) + Rd; }}, none);
-                    0x2: WarnUnimpl::umall();
-                    0x4: umull({{
-                        resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
-                        Rd = (uint32_t)(resTemp & 0xffffffff);
-                        Rn = (uint32_t)(resTemp >> 32);
-                    }}, llbit);
-                    0x5: smlal({{ 
-                        resTemp = ((int64_t)Rm) * ((int64_t)Rs); 
-                        resTemp += (((uint64_t)Rn) << 32) | ((uint64_t)Rd); 
-                        Rd = (uint32_t)(resTemp & 0xffffffff);
-                        Rn = (uint32_t)(resTemp >> 32);
-                    }}, llbit);
-                    0x6: smull({{
-                        resTemp = ((int64_t)(int32_t)Rm)*
-                                  ((int64_t)(int32_t)Rs);
-                        Rd = (int32_t)(resTemp & 0xffffffff);
-                        Rn = (int32_t)(resTemp >> 32);
-                    }}, llbit);
-                    0x7: umlal({{
-                        resTemp = ((uint64_t)Rm)*((uint64_t)Rs);
-                        resTemp += ((uint64_t)Rn << 32)+((uint64_t)Rd);
-                        Rd = (uint32_t)(resTemp & 0xffffffff);
-                        Rn = (uint32_t)(resTemp >> 32);
-                    }}, llbit);
-                }
-                1: decode PUBWL {
-                    0x10: WarnUnimpl::swp();
-                    0x14: WarnUnimpl::swpb();
-                    0x18: WarnUnimpl::strex();
-                    0x19: WarnUnimpl::ldrex();
-                }
-            }
-            format AddrMode3 {
-                0xb: strh_ldrh(store, {{ Mem.uh = Rd; }},
-                               load,  {{ Rd = Mem.uh; }});
-                0xd: ldrd_ldrsb(load, {{ Rde = bits(Mem.ud, 31, 0);
-                                         Rdo = bits(Mem.ud, 63, 32); }},
-                                load, {{ Rd = Mem.sb; }});
-                0xf: strd_ldrsh(store, {{ Mem.ud = (Rde.ud & mask(32)) |
-                                                   (Rdo.ud << 32); }},
-                                load,  {{ Rd = Mem.sh; }});
-            }
-        }
-        0: decode IS_MISC {
-            0: decode OPCODE {
-                0x0: and({{ Rd = resTemp = Rn & op2; }});
-                0x1: eor({{ Rd = resTemp = Rn ^ op2; }});
-                0x2: sub({{ Rd = resTemp = Rn - op2; }}, sub);
-                0x3: rsb({{ Rd = resTemp = op2 - Rn; }}, rsb);
-                0x4: add({{ Rd = resTemp = Rn + op2; }}, add);
-                0x5: adc({{ Rd = resTemp = Rn + op2 + CondCodes<29:>; }}, add);
-                0x6: sbc({{ Rd = resTemp = Rn - op2 - !CondCodes<29:>; }}, sub);
-                0x7: rsc({{ Rd = resTemp = op2 - Rn - !CondCodes<29:>; }}, rsb);
-                0x8: tst({{ resTemp = Rn & op2; }});
-                0x9: teq({{ resTemp = Rn ^ op2; }});
-                0xa: cmp({{ resTemp = Rn - op2; }}, sub);
-                0xb: cmn({{ resTemp = Rn + op2; }}, add);
-                0xc: orr({{ Rd = resTemp = Rn | op2; }});
-                0xd: mov({{ Rd = resTemp = op2; }});
-                0xe: bic({{ Rd = resTemp = Rn & ~op2; }});
-                0xf: mvn({{ Rd = resTemp = ~op2; }});
-            }
-            1: decode MISC_OPCODE {
-                0x0: decode OPCODE {
-                    0x8: PredOp::mrs_cpsr({{
-                        Rd = (Cpsr | CondCodes) & 0xF8FF03DF;
-                    }});
-                    0x9: decode USEIMM {
-                        // The mask field is the same as the RN index.
-                        0: PredOp::msr_cpsr_reg({{
-                            uint32_t newCpsr =
-                                cpsrWriteByInstr(Cpsr | CondCodes,
-                                                 Rm, RN, false);
-                            Cpsr = ~CondCodesMask & newCpsr;
-                            CondCodes = CondCodesMask & newCpsr;
-                        }});
-                        1: PredImmOp::msr_cpsr_imm({{
-                            uint32_t newCpsr =
-                                cpsrWriteByInstr(Cpsr | CondCodes,
-                                                 rotated_imm, RN, false);
-                            Cpsr = ~CondCodesMask & newCpsr;
-                            CondCodes = CondCodesMask & newCpsr;
-                        }});
-                    }
-                    0xa: PredOp::mrs_spsr({{ Rd = Spsr; }});
-                    0xb: decode USEIMM {
-                        // The mask field is the same as the RN index.
-                        0: PredOp::msr_spsr_reg({{
-                            Spsr = spsrWriteByInstr(Spsr, Rm, RN, false);
-                        }});
-                        1: PredImmOp::msr_spsr_imm({{
-                            Spsr = spsrWriteByInstr(Spsr, rotated_imm,
-                                                    RN, false);
-                        }});
-                    }
-                }
-                0x1: decode OPCODE {
-                    0x9: BranchExchange::bx({{ }});
-                    0xb: PredOp::clz({{
-                        Rd = ((Rm == 0) ? 32 : (31 - findMsbSet(Rm)));
-                    }});
-                }
-                0x2: decode OPCODE {
-                    0x9: WarnUnimpl::bxj();
-                }
-                0x3: decode OPCODE {
-                    0x9: BranchExchange::blx({{ }}, Link);
-                }
-                0x5: decode OPCODE {
-                    0x8: WarnUnimpl::qadd();
-                    0x9: WarnUnimpl::qsub();
-                    0xa: WarnUnimpl::qdadd();
-                    0xb: WarnUnimpl::qdsub();
-                }
-                0x8: decode OPCODE {
-                    0x8: smlabb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
-                    0x9: WarnUnimpl::smlalbb();
-                    0xa: WarnUnimpl::smlawb();
-                    0xb: smulbb({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<15:0>); }}, none);
-                }
-                0xa: decode OPCODE {
-                    0x8: smlatb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>) + Rd; }}, overflow);
-                    0x9: smulwb({{ 
-                        Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<15:0>), 47, 16); 
-                    }}, none);
-                    0xa: WarnUnimpl::smlaltb();
-                    0xb: smultb({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<15:0>); }}, none);
-                }
-                0xc: decode OPCODE {
-                    0x8: smlabt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
-                    0x9: WarnUnimpl::smlawt();
-                    0xa: WarnUnimpl::smlalbt();
-                    0xb: smulbt({{ Rn = resTemp = sext<16>(Rm<15:0>) * sext<16>(Rs<31:16>); }}, none);
-                }
-                0xe: decode OPCODE {
-                    0x8: smlatt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>) + Rd; }}, overflow);
-                    0x9: smulwt({{ 
-                        Rn = resTemp = bits(sext<32>(Rm) * sext<16>(Rs<31:16>), 47, 16); 
-                    }}, none);
-                    0xa: WarnUnimpl::smlaltt();
-                    0xb: smultt({{ Rn = resTemp = sext<16>(Rm<31:16>) * sext<16>(Rs<31:16>); }}, none);
-                }
-            }
-        }
-    }
-    0x1: decode IS_MISC {
-        0: decode OPCODE {
-            format DataImmOp {
-                0x0: andi({{ Rd = resTemp = Rn & rotated_imm; }});
-                0x1: eori({{ Rd = resTemp = Rn ^ rotated_imm; }});
-                0x2: subi({{ Rd = resTemp = Rn - rotated_imm; }}, sub);
-                0x3: rsbi({{ Rd = resTemp = rotated_imm - Rn; }}, rsb);
-                0x4: addi({{ Rd = resTemp = Rn + rotated_imm; }}, add);
-                0x5: adci({{
-                    Rd = resTemp = Rn + rotated_imm + CondCodes<29:>;
-                }}, add);
-                0x6: sbci({{
-                    Rd = resTemp = Rn -rotated_imm - !CondCodes<29:>;
-                }}, sub);
-                0x7: rsci({{
-                    Rd = resTemp = rotated_imm - Rn - !CondCodes<29:>;
-                }}, rsb);
-                0x8: tsti({{ resTemp = Rn & rotated_imm; }});
-                0x9: teqi({{ resTemp = Rn ^ rotated_imm; }});
-                0xa: cmpi({{ resTemp = Rn - rotated_imm; }}, sub);
-                0xb: cmni({{ resTemp = Rn + rotated_imm; }}, add);
-                0xc: orri({{ Rd = resTemp = Rn | rotated_imm; }});
-                0xd: movi({{ Rd = resTemp = rotated_imm; }});
-                0xe: bici({{ Rd = resTemp = Rn & ~rotated_imm; }});
-                0xf: mvni({{ Rd = resTemp = ~rotated_imm; }});
-            }
-        }
-        1: decode OPCODE {
-            // The following two instructions aren't supposed to be defined
-            0x8: DataOp::movw({{ Rd = IMMED_11_0 | (RN << 12) ; }});
-            0x9: decode RN {
-                0: decode IMM {
-                    0: PredImmOp::nop({{ ; }});
-                    1: WarnUnimpl::yield();
-                    2: WarnUnimpl::wfe();
-                    3: WarnUnimpl::wfi();
-                    4: WarnUnimpl::sev();
-                }
-                default: PredImmOp::msr_i_cpsr({{
-                            uint32_t newCpsr =
-                                cpsrWriteByInstr(Cpsr | CondCodes,
-                                                 rotated_imm, RN, false);
-                            Cpsr = ~CondCodesMask & newCpsr;
-                            CondCodes = CondCodesMask & newCpsr;
-                }});
-            }
-            0xa: PredOp::movt({{ Rd = IMMED_11_0 << 16 | RN << 28 | Rd<15:0>; }});
-            0xb: PredImmOp::msr_i_spsr({{
-                       Spsr = spsrWriteByInstr(Spsr, rotated_imm, RN, false); 
-            }});
-        }
-    }
-    0x2: AddrMode2::addrMode2(Disp, disp);
-    0x3: decode OPCODE_4 {
-        0: AddrMode2::addrMode2(Shift, Rm_Imm);
-        1: decode MEDIA_OPCODE {
-            0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7: WarnUnimpl::parallel_add_subtract_instructions();
-            0x8: decode MISC_OPCODE {
-                0x1, 0x9: WarnUnimpl::pkhbt();
-                0x7: WarnUnimpl::sxtab16();
-                0xb: WarnUnimpl::sel();
-                0x5, 0xd: WarnUnimpl::pkhtb();
-                0x3: WarnUnimpl::sign_zero_extend_add();
-            }
-            0xa, 0xb: decode SHIFT {
-                0x0, 0x2: WarnUnimpl::ssat();
-                0x1: WarnUnimpl::ssat16();
-            }
-            0xe, 0xf: decode SHIFT {
-                0x0, 0x2: WarnUnimpl::usat();
-                0x1: WarnUnimpl::usat16();
-            }
-            0x10: decode RN {
-                0xf: decode MISC_OPCODE {
-                    0x1: WarnUnimpl::smuad();
-                    0x3: WarnUnimpl::smuadx();
-                    0x5: WarnUnimpl::smusd();
-                    0x7: WarnUnimpl::smusdx();
-                }
-                default: decode MISC_OPCODE {
-                    0x1: WarnUnimpl::smlad();
-                    0x3: WarnUnimpl::smladx();
-                    0x5: WarnUnimpl::smlsd();
-                    0x7: WarnUnimpl::smlsdx();
-                }
-            }
-            0x14: decode MISC_OPCODE {
-                0x1: WarnUnimpl::smlald();
-                0x3: WarnUnimpl::smlaldx();
-                0x5: WarnUnimpl::smlsld();
-                0x7: WarnUnimpl::smlsldx();
-            }
-            0x15: decode RN {
-                0xf: decode MISC_OPCODE {
-                    0x1: WarnUnimpl::smmul();
-                    0x3: WarnUnimpl::smmulr();
-                }
-                default: decode MISC_OPCODE {
-                    0x1: WarnUnimpl::smmla();
-                    0x3: WarnUnimpl::smmlar();
-                    0xd: WarnUnimpl::smmls();
-                    0xf: WarnUnimpl::smmlsr();
-                }
-            }
-            0x18: decode RN {
-                0xf: WarnUnimpl::usada8();
-                default: WarnUnimpl::usad8();
-            }
-        }
-    }
-    0x4: decode PUSWL {
-        // Right now we only handle cases when S (PSRUSER) is not set
-        default: ArmMacroStore::ldmstm({{ }});
-    }
-    0x5: decode OPCODE_24 {
-        // Branch (and Link) Instructions
-        0: Branch::b({{ }});
-        1: Branch::bl({{ }}, Link);
-    }
-    0x6: decode CPNUM {
-        0x1: decode PUNWL {
-            0x02,0x0a: decode OPCODE_15 {
-                0: ArmStoreMemory::stfs_({{ Mem.sf = Fd.sf;
-                                            Rn = Rn + disp8; }},
-                    {{ EA = Rn; }});
-                1: ArmMacroFPAOp::stfd_({{ }});
-            }
-            0x03,0x0b: decode OPCODE_15 {
-                0: ArmLoadMemory::ldfs_({{ Fd.sf = Mem.sf;
-                                           Rn = Rn + disp8; }},
-                    {{ EA = Rn; }});
-                1: ArmMacroFPAOp::ldfd_({{ }});
-            }
-            0x06,0x0e: decode OPCODE_15 {
-                0: ArmMacroFPAOp::stfe_nw({{ }});
-            }
-            0x07,0x0f: decode OPCODE_15 {
-                0: ArmMacroFPAOp::ldfe_nw({{ }});
-            }
-            0x10,0x18: decode OPCODE_15 {
-                0: ArmStoreMemory::stfs_p({{ Mem.sf = Fd.sf; }},
-                    {{ EA = Rn + disp8; }});
-                1: ArmMacroFPAOp::stfd_p({{ }});
-            }
-            0x11,0x19: decode OPCODE_15 {
-                0: ArmLoadMemory::ldfs_p({{ Fd.sf = Mem.sf; }},
-                    {{ EA = Rn + disp8; }});
-                1: ArmMacroFPAOp::ldfd_p({{ }});
-            }
-            0x12,0x1a: decode OPCODE_15 {
-                0: ArmStoreMemory::stfs_pw({{ Mem.sf = Fd.sf;
-                                              Rn = Rn + disp8; }},
-                    {{ EA = Rn + disp8; }});
-                1: ArmMacroFPAOp::stfd_pw({{ }});
-            }
-            0x13,0x1b: decode OPCODE_15 {
-                0: ArmLoadMemory::ldfs_pw({{ Fd.sf = Mem.sf;
-                                             Rn = Rn + disp8; }},
-                    {{ EA = Rn + disp8; }});
-                1: ArmMacroFPAOp::ldfd_pw({{ }});
-            }
-            0x14,0x1c: decode OPCODE_15 {
-                0: ArmMacroFPAOp::stfe_pn({{ }});
-            }
-            0x15,0x1d: decode OPCODE_15 {
-                0: ArmMacroFPAOp::ldfe_pn({{ }});
-            }
-            0x16,0x1e: decode OPCODE_15 {
-                0: ArmMacroFPAOp::stfe_pnw({{ }});
-            }
-            0x17,0x1f: decode OPCODE_15 {
-                0: ArmMacroFPAOp::ldfe_pnw({{ }});
-            }
-        }
-        0x2: decode PUNWL {
-            // could really just decode as a single instruction
-            0x00,0x04,0x08,0x0c: ArmMacroFMOp::sfm_({{ }});
-            0x01,0x05,0x09,0x0d: ArmMacroFMOp::lfm_({{ }});
-            0x02,0x06,0x0a,0x0e: ArmMacroFMOp::sfm_w({{ }});
-            0x03,0x07,0x0b,0x0f: ArmMacroFMOp::lfm_w({{ }});
-            0x10,0x14,0x18,0x1c: ArmMacroFMOp::sfm_p({{ }});
-            0x11,0x15,0x19,0x1d: ArmMacroFMOp::lfm_p({{ }});
-            0x12,0x16,0x1a,0x1e: ArmMacroFMOp::sfm_pw({{ }});
-            0x13,0x17,0x1b,0x1f: ArmMacroFMOp::lfm_pw({{ }});
-        }
-        0xb: decode LOADOP {
-            0x0: WarnUnimpl::fstmx();
-            0x1: WarnUnimpl::fldmx();
-        }
-    }
-    0x7: decode OPCODE_24 {
-        0: decode OPCODE_4 {
-            0: decode CPNUM {
-                format FloatOp {
-                    0x1: decode OPCODE_23_20 {
-                            0x0: decode OPCODE_15 {
-                                0: adf({{ Fd.sf = Fn.sf + Fm.sf; }});
-                                1: mvf({{ Fd.sf = Fm.sf; }});
-                            }
-                            0x1: decode OPCODE_15 {
-                                0: muf({{ Fd.sf = Fn.sf * Fm.sf; }});
-                                1: mnf({{ Fd.sf = -Fm.sf; }});
-                            }
-                            0x2: decode OPCODE_15 {
-                                0: suf({{ Fd.sf = Fn.sf - Fm.sf; }});
-                                1: abs({{ Fd.sf = fabs(Fm.sf); }});
-                            }
-                            0x3: decode OPCODE_15 {
-                                0: rsf({{ Fd.sf = Fm.sf - Fn.sf; }});
-                                1: rnd({{ Fd.sf = rint(Fm.sf); }});
-                            }
-                            0x4: decode OPCODE_15 {
-                                0: dvf({{ Fd.sf = Fn.sf / Fm.sf; }});
-                                1: sqt({{ Fd.sf = sqrt(Fm.sf); }});
-                            }
-                            0x5: decode OPCODE_15 {
-                                0: rdf({{ Fd.sf = Fm.sf / Fn.sf; }});
-                                1: log({{ Fd.sf = log10(Fm.sf); }});
-                            }
-                            0x6: decode OPCODE_15 {
-                                0: pow({{ Fd.sf = pow(Fm.sf, Fn.sf); }});
-                                1: lgn({{ Fd.sf = log(Fm.sf); }});
-                            }
-                            0x7: decode OPCODE_15 {
-                                0: rpw({{ Fd.sf = pow(Fn.sf, Fm.sf); }});
-                                1: exp({{ Fd.sf = exp(Fm.sf); }});
-                            }
-                            0x8: decode OPCODE_15 {
-                                0: rmf({{ Fd.sf = drem(Fn.sf, Fm.sf); }});
-                                1: sin({{ Fd.sf = sin(Fm.sf); }});
-                            }
-                            0x9: decode OPCODE_15 {
-                                0: fml({{ Fd.sf = Fn.sf * Fm.sf; }});
-                                1: cos({{ Fd.sf = cos(Fm.sf); }});
-                            }
-                            0xa: decode OPCODE_15 {
-                                0: fdv({{ Fd.sf = Fn.sf / Fm.sf; }});
-                                1: tan({{ Fd.sf = tan(Fm.sf); }});
-                            }
-                            0xb: decode OPCODE_15 {
-                                0: frd({{ Fd.sf = Fm.sf / Fn.sf; }});
-                                1: asn({{ Fd.sf = asin(Fm.sf); }});
-                            }
-                            0xc: decode OPCODE_15 {
-                                0: pol({{ Fd.sf = atan2(Fn.sf, Fm.sf); }});
-                                1: acs({{ Fd.sf = acos(Fm.sf); }});
-                            }
-                            0xd: decode OPCODE_15 {
-                                1: atn({{ Fd.sf = atan(Fm.sf); }});
-                            }
-                            0xe: decode OPCODE_15 {
-                                // Unnormalised Round
-                                1: FailUnimpl::urd();
-                            }
-                            0xf: decode OPCODE_15 {
-                                // Normalise
-                                1: FailUnimpl::nrm();
-                            }
-                    } // OPCODE_23_20
-                } // format FloatOp
-            } // CPNUM
-            1: decode CPNUM { // 27-24=1110,4 ==1
-                1: decode OPCODE_15_12 {
-                    format FloatOp {
-                        0xf: decode OPCODE_23_21 {
-                            format FloatCmp {
-                                0x4: cmf({{ Fn.df }}, {{ Fm.df }});
-                                0x5: cnf({{ Fn.df }}, {{ -Fm.df }});
-                                0x6: cmfe({{ Fn.df }}, {{ Fm.df}});
-                                0x7: cnfe({{ Fn.df }}, {{ -Fm.df}});
-                            }
-                        }
-                        default: decode OPCODE_23_20 {
-                            0x0: decode OPCODE_7 {
-                                0: flts({{ Fn.sf = (float) Rd.sw; }});
-                                1: fltd({{ Fn.df = (double) Rd.sw; }});
-                            }
-                            0x1: decode OPCODE_7 {
-                                0: fixs({{ Rd = (uint32_t) Fm.sf; }});
-                                1: fixd({{ Rd = (uint32_t) Fm.df; }});
-                            }
-                            0x2: wfs({{ Fpsr = Rd; }});
-                            0x3: rfs({{ Rd = Fpsr; }});
-                            0x4: FailUnimpl::wfc();
-                            0x5: FailUnimpl::rfc();
-                        }
-                    } // format FloatOp
-                }
-                0xa: decode MISC_OPCODE {
-                    0x1: decode MEDIA_OPCODE {
-                        0xf: decode RN {
-                            0x0: FloatOp::fmrx_fpsid({{ Rd = Fpsid; }});
-                            0x1: FloatOp::fmrx_fpscr({{ Rd = Fpscr; }});
-                            0x8: FloatOp::fmrx_fpexc({{ Rd = Fpexc; }});
-                        }
-                        0xe: decode RN {
-                            0x0: FloatOp::fmxr_fpsid({{ Fpsid = Rd; }});
-                            0x1: FloatOp::fmxr_fpscr({{ Fpscr = Rd; }});
-                            0x8: FloatOp::fmxr_fpexc({{ Fpexc = Rd; }});
-                        }
-                    } // MEDIA_OPCODE (MISC_OPCODE 0x1)
-                } // MISC_OPCODE (CPNUM 0xA)
-                0xf: decode RN {
-                    // Barrriers, Cache Maintence, NOPS
-                    7: decode OPCODE_23_21 {
-                        0: decode RM {
-                            0: decode OPC2 {
-                                4: decode OPCODE_20 {
-                                    0: PredOp::mcr_cp15_nop1({{ }}); // was wfi
-                                }
-                            }
-                            1: WarnUnimpl::cp15_cache_maint();
-                            4: WarnUnimpl::cp15_par();
-                            5: decode OPC2 {
-                                0,1: WarnUnimpl::cp15_cache_maint2();
-                                4: PredOp::cp15_isb({{ ; }}, IsMemBarrier, IsSerializeBefore);
-                                6,7: WarnUnimpl::cp15_bp_maint();
-                            }
-                            6: WarnUnimpl::cp15_cache_maint3();
-                            8: WarnUnimpl::cp15_va_to_pa();
-                            10: decode OPC2 {
-                                1,2: WarnUnimpl::cp15_cache_maint3();
-                                4: PredOp::cp15_dsb({{ ; }}, IsMemBarrier, IsSerializeBefore);
-                                5: PredOp::cp15_dmb({{ ; }}, IsMemBarrier, IsSerializeBefore);
-                            }
-                            11: WarnUnimpl::cp15_cache_maint4();
-                            13: decode OPC2 {
-                                1: decode OPCODE_20 {
-                                    0: PredOp::mcr_cp15_nop2({{ }}); // was prefetch
-                                }
-                            }
-                            14: WarnUnimpl::cp15_cache_maint5();
-                        } // RM
-                    } // OPCODE_23_21 CR
-                            
-                    // Thread ID and context ID registers
-                    // Thread ID register needs cheaper access than miscreg
-                    13: WarnUnimpl::mcr_mrc_cp15_c7(); 
-
-                    // All the rest
-                    default: decode OPCODE_20 {
-                        0: PredOp::mcr_cp15({{ 
-                               fault = setCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 
-                        }});
-                        1: PredOp::mrc_cp15({{ 
-                               fault = readCp15Register(Rd, RN, OPCODE_23_21, RM, OPC2); 
-                        }});
-                    }
-                }  // RN 
-            } // CPNUM  (OP4 == 1)
-        } //OPCODE_4
-
-#if FULL_SYSTEM
-        1: PredOp::swi({{ fault = new SupervisorCall; }}, IsSerializeAfter, IsNonSpeculative, IsSyscall); 
-#else
-        1: PredOp::swi({{ if (testPredicate(CondCodes, condCode))
-            {
-                if (IMMED_23_0)
-                    xc->syscall(IMMED_23_0);
-                else
-                    xc->syscall(R7);
-            }
-        }});
-#endif // FULL_SYSTEM
-    } // OPCODE_24
+// Authors: Gabe Black
 
+decode THUMB default Unknown::unknown() {
+##include "armdecode.isa"
+##include "thumbdecode.isa"
 }
-}
-
diff --git a/src/arch/arm/isa/thumbdecode.isa b/src/arch/arm/isa/thumbdecode.isa
new file mode 100644
index 000000000..c6fd3b21f
--- /dev/null
+++ b/src/arch/arm/isa/thumbdecode.isa
@@ -0,0 +1,46 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Copyright (c) 2009 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+1: decode BIGTHUMB {
+    0: Unknown::unknown();
+    1: Unknown::unknown();
+}