diff options
| author | Korey Sewell <ksewell@umich.edu> | 2011-02-04 00:09:22 -0500 |
|---|---|---|
| committer | Korey Sewell <ksewell@umich.edu> | 2011-02-04 00:09:22 -0500 |
| commit | a48fe2729a0c7b5e269c82375b2b1810b8caac79 (patch) | |
| tree | 2e5e721909b611f49c446fd7972dc1705a1f0af9 | |
| parent | e396a34b0155d5054a099c67a91baa66c095d3d8 (diff) | |
| download | gem5-a48fe2729a0c7b5e269c82375b2b1810b8caac79.tar.xz | |
imported patch regression_updates
14 files changed, 760 insertions, 737 deletions
diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini index 29471b56d..83b3078ca 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/config.ini @@ -35,6 +35,7 @@ div8RepeatRate=1 do_checkpoint_insts=true do_statistics_insts=true dtb=system.cpu.dtb +fetchBuffSize=4 fetchMemPort=icache_port functionTrace=false functionTraceStart=0 @@ -61,7 +62,7 @@ phase=0 predType=tournament progress_interval=0 stageTracing=false -stageWidth=1 +stageWidth=4 system=system threadModel=SMT tracer=system.cpu.tracer @@ -191,7 +192,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/vortex +executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout index 132441094..38b60786d 100755 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,12 +5,12 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 22:06:02 -M5 executing on aus-bc2-b15 +M5 compiled Jan 24 2011 21:05:28 +M5 revision Unknown +M5 started Jan 24 2011 21:53:14 +M5 executing on m55-002.pool command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/50.vortex/alpha/tru64/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. -Exiting @ tick 104166942500 because target called exit() +Exiting @ tick 43686968500 because halt instruction encountered diff --git a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt index cccd9d82e..827d1ba1c 100644 --- a/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,103 +1,105 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 67514 # Simulator instruction rate (inst/s) -host_mem_usage 256704 # Number of bytes of host memory used -host_seconds 1308.48 # Real time elapsed on the host -host_tick_rate 79609109 # Simulator tick rate (ticks/s) +host_inst_rate 68116 # Simulator instruction rate (inst/s) +host_mem_usage 1627972 # Number of bytes of host memory used +host_seconds 1296.92 # Real time elapsed on the host +host_tick_rate 33685044 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 88340673 # Number of instructions simulated -sim_seconds 0.104167 # Number of seconds simulated -sim_ticks 104166942500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 34890015 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 41.015608 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 4719981 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 11507768 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 1778 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 652196 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 8920848 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 13754477 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 5723290 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 8031187 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 1659774 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 53409557 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 4.741700 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 652196 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 13102281 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 434959 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 217237 # Number of Branches Incorrectly Predicted As Taken. +sim_insts 88340674 # Number of instructions simulated +sim_seconds 0.043687 # Number of seconds simulated +sim_ticks 43686968500 # Number of ticks simulated +system.cpu.AGEN-Unit.agens 35033051 # Number of Address Generations +system.cpu.Branch-Predictor.BTBHitPct 40.125175 # BTB Hit Percentage +system.cpu.Branch-Predictor.BTBHits 4678518 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 11659807 # Number of BTB lookups +system.cpu.Branch-Predictor.RASInCorrect 1539 # Number of incorrect RAS predictions. +system.cpu.Branch-Predictor.condIncorrect 753993 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 9173158 # Number of conditional branches predicted +system.cpu.Branch-Predictor.lookups 14237669 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 6139595 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 8098074 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.usedRAS 1660495 # Number of times the RAS was used to get a target. +system.cpu.Execution-Unit.executions 53620617 # Number of Instructions Executed. +system.cpu.Execution-Unit.mispredictPct 5.481801 # Percentage of Incorrect Branches Predicts +system.cpu.Execution-Unit.mispredicted 753993 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.predicted 13000484 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.predictedNotTakenIncorrect 550902 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 203091 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 41101 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 156429280 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 103882399 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 145605016 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 93058135 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 52546881 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 2135966 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 85.354290 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 13517269 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 70.714707 # Percentage of cycles cpu is active system.cpu.comBranches 13754477 # Number of Branches instructions committed system.cpu.comFloats 151453 # Number of Floating Point instructions committed system.cpu.comInts 30791227 # Number of Integer instructions committed system.cpu.comLoads 20276638 # Number of Load instructions committed -system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed +system.cpu.comNonSpec 4584 # Number of Non-Speculative instructions committed system.cpu.comNops 8748916 # Number of Nop instructions committed system.cpu.comStores 14613377 # Number of Store instructions committed -system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 88340674 # Number of Instructions Simulated (Per-Thread) +system.cpu.committedInsts_total 88340674 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.358301 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.358301 # CPI: Total CPI of All Threads +system.cpu.cpi 0.989057 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 0.989057 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 37505.438897 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34394.916565 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 20215872 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 2279055500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 60766 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 2090041500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 43413.349504 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34421.543297 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 20182230 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4098567500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.004656 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 94408 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 33642 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 2091659500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 60766 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 52898.208639 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49865.139506 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 7595019000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 7159537000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 50157.670646 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49503.458051 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 14405989 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 10402099000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.014192 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 207388 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 63810 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 7107607500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 169.741568 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 16833.333333 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 169.264666 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 162 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 2727000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 48320.843773 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 45264.742297 # average overall mshr miss latency -system.cpu.dcache.demand_hits 34685671 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9874074500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses -system.cpu.dcache.demand_misses 204344 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 9249578500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_avg_miss_latency 48047.908190 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 45018.532475 # average overall mshr miss latency +system.cpu.dcache.demand_hits 34588219 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 14500666500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.008650 # miss rate for demand accesses +system.cpu.dcache.demand_misses 301796 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 97452 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 9199267000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 204344 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.995297 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 4076.738170 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.994103 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 4071.844776 # Average occupied blocks per context system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 48320.843773 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 45264.742297 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 48047.908190 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 45018.532475 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 34685671 # number of overall hits -system.cpu.dcache.overall_miss_latency 9874074500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses -system.cpu.dcache.overall_misses 204344 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 9249578500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 34588219 # number of overall hits +system.cpu.dcache.overall_miss_latency 14500666500 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.008650 # miss rate for overall accesses +system.cpu.dcache.overall_misses 301796 # number of overall misses +system.cpu.dcache.overall_mshr_hits 97452 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 9199267000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 204344 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -105,10 +107,10 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 200248 # number of replacements system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 4076.738170 # Cycle average of tags in use -system.cpu.dcache.total_refs 34685671 # Total number of references to valid blocks. -system.cpu.dcache.warmup_cycle 834588000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.writebacks 161221 # number of writebacks +system.cpu.dcache.tagsinuse 4071.844776 # Cycle average of tags in use +system.cpu.dcache.total_refs 34588219 # Total number of references to valid blocks. +system.cpu.dcache.warmup_cycle 497786000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.writebacks 161214 # number of writebacks system.cpu.dtb.data_accesses 34987415 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 34890015 # DTB hits @@ -125,73 +127,73 @@ system.cpu.dtb.write_accesses 14620629 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 14613377 # DTB write hits system.cpu.dtb.write_misses 7252 # DTB write misses -system.cpu.icache.ReadReq_accesses 97023272 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 19054.387931 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 15836.123818 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 96943861 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 1513128000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000818 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 79411 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 1587 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 1232430500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000802 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 77824 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 11384473 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 18619.899316 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 15557.624423 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 11286741 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 1819760000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.008585 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 97732 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 9063 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 1379479000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.007789 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 88669 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 800 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 1245.680780 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles::no_targets 18115.384615 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 127.292157 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 5 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 39 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 4000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 706500 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 97023272 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 19054.387931 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 15836.123818 # average overall mshr miss latency -system.cpu.icache.demand_hits 96943861 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 1513128000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000818 # miss rate for demand accesses -system.cpu.icache.demand_misses 79411 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 1587 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 1232430500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000802 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 77824 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 11384473 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 18619.899316 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 15557.624423 # average overall mshr miss latency +system.cpu.icache.demand_hits 11286741 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 1819760000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.008585 # miss rate for demand accesses +system.cpu.icache.demand_misses 97732 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 9063 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 1379479000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.007789 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 88669 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.914428 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1872.748134 # Average occupied blocks per context -system.cpu.icache.overall_accesses 97023272 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 19054.387931 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 15836.123818 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.918761 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1881.622790 # Average occupied blocks per context +system.cpu.icache.overall_accesses 11384473 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 18619.899316 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 15557.624423 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 96943861 # number of overall hits -system.cpu.icache.overall_miss_latency 1513128000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000818 # miss rate for overall accesses -system.cpu.icache.overall_misses 79411 # number of overall misses -system.cpu.icache.overall_mshr_hits 1587 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 1232430500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000802 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 77824 # number of overall MSHR misses +system.cpu.icache.overall_hits 11286741 # number of overall hits +system.cpu.icache.overall_miss_latency 1819760000 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.008585 # miss rate for overall accesses +system.cpu.icache.overall_misses 97732 # number of overall misses +system.cpu.icache.overall_mshr_hits 9063 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 1379479000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.007789 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 88669 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 75778 # number of replacements -system.cpu.icache.sampled_refs 77824 # Sample count of references to valid blocks. +system.cpu.icache.replacements 86622 # number of replacements +system.cpu.icache.sampled_refs 88668 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1872.748134 # Cycle average of tags in use -system.cpu.icache.total_refs 96943861 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1881.622790 # Cycle average of tags in use +system.cpu.icache.total_refs 11286741 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 30511976 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.424034 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.424034 # IPC: Total IPC of All Threads +system.cpu.idleCycles 25587714 # Number of cycles cpu's stages were not processed +system.cpu.ipc 1.011064 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 1.011064 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 97027284 # ITB accesses +system.cpu.itb.fetch_accesses 11389750 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 97023273 # ITB hits -system.cpu.itb.fetch_misses 4011 # ITB misses +system.cpu.itb.fetch_hits 11384494 # ITB hits +system.cpu.itb.fetch_misses 5256 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations system.cpu.itb.read_hits 0 # DTB read hits @@ -200,97 +202,98 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_acv 0 # DTB write access violations system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52440.979168 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.144510 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_hits 12099 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 6894887500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_rate 0.915732 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_misses 131479 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259179000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915732 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_misses 131479 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 138590 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52303.399887 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40004.932662 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 96118 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 2221430000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.306458 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 42472 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 1699089500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.306458 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 42472 # number of ReadReq MSHR misses -system.cpu.l2cache.Writeback_accesses 161221 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_hits 161221 # number of Writeback hits +system.cpu.l2cache.ReadExReq_accesses 143582 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_avg_miss_latency 52040.936228 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000.851808 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_hits 12097 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_miss_latency 6842602500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_rate 0.915748 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_misses 131485 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259512000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915748 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_misses 131485 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 149430 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52294.227145 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40025.874305 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 106453 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 2247449000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.287606 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 42977 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 1720192000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.287606 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 42977 # number of ReadReq MSHR misses +system.cpu.l2cache.Writeback_accesses 161214 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_hits 161214 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.718111 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.775484 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 282168 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52407.387713 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40001.313588 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 108217 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 9116317500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.616480 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 173951 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 293012 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52103.331958 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40007.015854 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 118550 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 9090051500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.595409 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 174462 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 6958268500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.616480 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 173951 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 6979704000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.595409 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 174462 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.086814 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.481065 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2844.720641 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 15763.536508 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 282168 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52407.387713 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40001.313588 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.093045 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.476016 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 3048.903015 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 15598.107451 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 293012 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52103.331958 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40007.015854 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 108217 # number of overall hits -system.cpu.l2cache.overall_miss_latency 9116317500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.616480 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 173951 # number of overall misses +system.cpu.l2cache.overall_hits 118550 # number of overall hits +system.cpu.l2cache.overall_miss_latency 9090051500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.595409 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 174462 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 6958268500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.616480 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 173951 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 6979704000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.595409 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 174462 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.l2cache.replacements 147575 # number of replacements -system.cpu.l2cache.sampled_refs 172919 # Sample count of references to valid blocks. +system.cpu.l2cache.replacements 148090 # number of replacements +system.cpu.l2cache.sampled_refs 173435 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 18608.257148 # Cycle average of tags in use -system.cpu.l2cache.total_refs 124175 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 18647.010465 # Cycle average of tags in use +system.cpu.l2cache.total_refs 134496 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.writebacks 120508 # number of writebacks -system.cpu.numCycles 208333886 # number of cpu cycles simulated -system.cpu.runCycles 177821910 # Number of cycles cpu stages are processed. +system.cpu.l2cache.writebacks 120516 # number of writebacks +system.cpu.numCycles 87373938 # number of cpu cycles simulated +system.cpu.runCycles 61786224 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 111306602 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 97027284 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 46.572973 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 119969888 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 88363998 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 42.414607 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 118518100 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 89815786 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 43.111463 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 173436619 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 34897267 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 16.750644 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 119993213 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 88340673 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 42.403411 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 208333886 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-0.idleCycles 42492197 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 44881741 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 51.367424 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 48180975 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 39192963 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 44.856583 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 46081271 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 41292667 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 47.259707 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 63475501 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.runCycles 23898437 # Number of cycles 1+ instructions are processed. +system.cpu.stage-3.utilization 27.351906 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 39335442 # Number of cycles 0 instructions are processed. +system.cpu.stage-4.runCycles 48038496 # Number of cycles 1+ instructions are processed. +system.cpu.stage-4.utilization 54.980349 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 69006043 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.timesIdled 289198 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini index ee561cd14..389a82884 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/config.ini @@ -35,6 +35,7 @@ div8RepeatRate=1 do_checkpoint_insts=true do_statistics_insts=true dtb=system.cpu.dtb +fetchBuffSize=4 fetchMemPort=icache_port functionTrace=false functionTraceStart=0 @@ -61,7 +62,7 @@ phase=0 predType=tournament progress_interval=0 stageTracing=false -stageWidth=1 +stageWidth=4 system=system threadModel=SMT tracer=system.cpu.tracer @@ -191,7 +192,7 @@ egid=100 env= errout=cerr euid=100 -executable=/chips/pd/randd/dist/cpu2000/binaries/alpha/tru64/twolf +executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf gid=100 input=cin max_stack_size=67108864 diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr index 67f69f09d..79a2396a6 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simerr @@ -1,5 +1,11 @@ warn: Sockets disabled, not accepting gdb connections For more information see: http://www.m5sim.org/warn/d946bea6 +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba +warn: Prefetch instrutions is Alpha do not do anything +For more information see: http://www.m5sim.org/warn/3e0eccba warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...) For more information see: http://www.m5sim.org/warn/5c5b547f hack: be nice to actually delete the event here diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout index dfb916a40..6bea6bb9d 100755 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,11 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Nov 2 2010 21:30:55 -M5 revision 0af3760102ec+ 7713+ default qtip ext/alpha_prefetch.patch tip -M5 started Nov 2 2010 21:31:02 -M5 executing on aus-bc2-b15 +M5 compiled Jan 24 2011 21:05:28 +M5 revision Unknown +M5 started Jan 24 2011 21:05:32 +M5 executing on m55-002.pool command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sav +Couldn't unlink build/ALPHA_SE/tests/fast/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2 Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. @@ -28,4 +28,4 @@ Authors: Carl Sechen, Bill Swartz 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 -122 123 124 Exiting @ tick 98335161000 because target called exit() +122 123 124 Exiting @ tick 40531473000 because halt instruction encountered diff --git a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt index 09e1aaa64..81e378671 100644 --- a/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt +++ b/tests/long/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt @@ -1,103 +1,105 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 68324 # Simulator instruction rate (inst/s) -host_mem_usage 244132 # Number of bytes of host memory used -host_seconds 1345.11 # Real time elapsed on the host -host_tick_rate 73105878 # Simulator tick rate (ticks/s) +host_inst_rate 66004 # Simulator instruction rate (inst/s) +host_mem_usage 1421192 # Number of bytes of host memory used +host_seconds 1392.38 # Real time elapsed on the host +host_tick_rate 29109416 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks -sim_insts 91903056 # Number of instructions simulated -sim_seconds 0.098335 # Number of seconds simulated -sim_ticks 98335161000 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 26497301 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 64.034182 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 5496951 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 8584401 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 174 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 2321041 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 7465012 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 10240685 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 2702033 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 7538652 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 1029596 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 64947503 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 22.664900 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 2321041 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 7919644 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 409064 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 1911977 # Number of Branches Incorrectly Predicted As Taken. +sim_insts 91903057 # Number of instructions simulated +sim_seconds 0.040531 # Number of seconds simulated +sim_ticks 40531473000 # Number of ticks simulated +system.cpu.AGEN-Unit.agens 27308571 # Number of Address Generations +system.cpu.Branch-Predictor.BTBHitPct 59.146475 # BTB Hit Percentage +system.cpu.Branch-Predictor.BTBHits 4489525 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 7590520 # Number of BTB lookups +system.cpu.Branch-Predictor.RASInCorrect 138 # Number of incorrect RAS predictions. +system.cpu.Branch-Predictor.condIncorrect 2806970 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 7883251 # Number of conditional branches predicted +system.cpu.Branch-Predictor.lookups 11539981 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 4913265 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 6626716 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.usedRAS 1029619 # Number of times the RAS was used to get a target. +system.cpu.Execution-Unit.executions 66407277 # Number of Instructions Executed. +system.cpu.Execution-Unit.mispredictPct 27.409983 # Percentage of Incorrect Branches Predicts +system.cpu.Execution-Unit.mispredicted 2806970 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.predicted 7433715 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.predictedNotTakenIncorrect 1384945 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 1422025 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 458252 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 185972268 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 117544907 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 152685933 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 84258572 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 68427361 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 2843090 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 95.462226 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 38185925 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 91.670105 # Percentage of cycles cpu is active system.cpu.comBranches 10240685 # Number of Branches instructions committed system.cpu.comFloats 3775974 # Number of Floating Point instructions committed system.cpu.comInts 43665352 # Number of Integer instructions committed system.cpu.comLoads 19996198 # Number of Load instructions committed -system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed +system.cpu.comNonSpec 390 # Number of Non-Speculative instructions committed system.cpu.comNops 7723346 # Number of Nop instructions committed system.cpu.comStores 6501103 # Number of Store instructions committed -system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread) -system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total) +system.cpu.committedInsts 91903057 # Number of Instructions Simulated (Per-Thread) +system.cpu.committedInsts_total 91903057 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 2.139976 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 2.139976 # CPI: Total CPI of All Threads +system.cpu.cpi 0.882048 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 0.882048 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 51549.473684 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48524.210526 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 24486000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.000024 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 23049000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 51751.953125 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48809.473684 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 19995686 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 26497000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.000026 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 512 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 37 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 23184500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.000024 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 475 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 55595.537757 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52592.105263 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 97181000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.000269 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 91931000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 55922.090261 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52793.478261 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 6496893 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 235432000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.000648 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 4210 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 2462 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 92283000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.000269 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 1748 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 52826.923077 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 11917.489429 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 26 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 1373500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 54730.994152 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 51722.896986 # average overall mshr miss latency -system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 121667000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.000084 # miss rate for demand accesses -system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 114980000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_avg_miss_latency 55469.927997 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 51942.195232 # average overall mshr miss latency +system.cpu.dcache.demand_hits 26492579 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 261929000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.000178 # miss rate for demand accesses +system.cpu.dcache.demand_misses 4722 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 2499 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 115467500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 2223 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.352016 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 1441.857733 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.351931 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 1441.507978 # Average occupied blocks per context system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 54730.994152 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 51722.896986 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 55469.927997 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 51942.195232 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 26495078 # number of overall hits -system.cpu.dcache.overall_miss_latency 121667000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.000084 # miss rate for overall accesses -system.cpu.dcache.overall_misses 2223 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 114980000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 26492579 # number of overall hits +system.cpu.dcache.overall_miss_latency 261929000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.000178 # miss rate for overall accesses +system.cpu.dcache.overall_misses 4722 # number of overall misses +system.cpu.dcache.overall_mshr_hits 2499 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 115467500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 2223 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -105,8 +107,8 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 157 # number of replacements system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 1441.857733 # Cycle average of tags in use -system.cpu.dcache.total_refs 26495078 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 1441.507978 # Cycle average of tags in use +system.cpu.dcache.total_refs 26492579 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 107 # number of writebacks system.cpu.dtb.data_accesses 26497334 # DTB accesses @@ -125,72 +127,72 @@ system.cpu.dtb.write_accesses 6501126 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 6501103 # DTB write hits system.cpu.dtb.write_misses 23 # DTB write misses -system.cpu.icache.ReadReq_accesses 101762751 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 27216.197508 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 23985.134662 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 101754083 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 235910000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.000085 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 8668 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 91 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 205720500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.000084 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 8577 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 9759566 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 26777.900606 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 23139.891881 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 9749163 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 278570500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.001066 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 10403 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 599 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 226863500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.001005 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 9804 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 2000 # average number of cycles each access was blocked -system.cpu.icache.avg_refs 11863.598344 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles::no_targets 18409.090909 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 994.406671 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 11 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 2000 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 202500 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 101762751 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 27216.197508 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 23985.134662 # average overall mshr miss latency -system.cpu.icache.demand_hits 101754083 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 235910000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.000085 # miss rate for demand accesses -system.cpu.icache.demand_misses 8668 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 91 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 205720500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.000084 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 8577 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 9759566 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 26777.900606 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 23139.891881 # average overall mshr miss latency +system.cpu.icache.demand_hits 9749163 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 278570500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.001066 # miss rate for demand accesses +system.cpu.icache.demand_misses 10403 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 599 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 226863500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.001005 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 9804 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.697636 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 1428.759296 # Average occupied blocks per context -system.cpu.icache.overall_accesses 101762751 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 27216.197508 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 23985.134662 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.729171 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 1493.341258 # Average occupied blocks per context +system.cpu.icache.overall_accesses 9759566 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 26777.900606 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 23139.891881 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 101754083 # number of overall hits -system.cpu.icache.overall_miss_latency 235910000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.000085 # miss rate for overall accesses -system.cpu.icache.overall_misses 8668 # number of overall misses -system.cpu.icache.overall_mshr_hits 91 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 205720500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.000084 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 8577 # number of overall MSHR misses +system.cpu.icache.overall_hits 9749163 # number of overall hits +system.cpu.icache.overall_miss_latency 278570500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.001066 # miss rate for overall accesses +system.cpu.icache.overall_misses 10403 # number of overall misses +system.cpu.icache.overall_mshr_hits 599 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 226863500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.001005 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 9804 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu.icache.replacements 6743 # number of replacements -system.cpu.icache.sampled_refs 8577 # Sample count of references to valid blocks. +system.cpu.icache.replacements 7919 # number of replacements +system.cpu.icache.sampled_refs 9804 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 1428.759296 # Cycle average of tags in use -system.cpu.icache.total_refs 101754083 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 1493.341258 # Cycle average of tags in use +system.cpu.icache.total_refs 9749163 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 8924455 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.467295 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.467295 # IPC: Total IPC of All Threads +system.cpu.idleCycles 6752458 # Number of cycles cpu's stages were not processed +system.cpu.ipc 1.133725 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 1.133725 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 101762799 # ITB accesses +system.cpu.itb.fetch_accesses 9759621 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 101762752 # ITB hits +system.cpu.itb.fetch_hits 9759574 # ITB hits system.cpu.itb.fetch_misses 47 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -201,96 +203,97 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 1748 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52216.318235 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40005.807201 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency 52356.562137 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40114.401858 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_hits 26 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_miss_latency 89916500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency 90158000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 0.985126 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 1722 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 68890000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 69077000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.985126 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 1722 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 9052 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52167.972576 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40020.078355 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_hits 5989 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 159790500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.338378 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 3063 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 122581500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.338378 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 3063 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_accesses 10279 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52322.450249 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40125.777363 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_hits 7063 # number of ReadReq hits +system.cpu.l2cache.ReadReq_miss_latency 168269000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.312871 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 3216 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 129044500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.312871 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 3216 # number of ReadReq MSHR misses system.cpu.l2cache.Writeback_accesses 107 # number of Writeback accesses(hits+misses) system.cpu.l2cache.Writeback_hits 107 # number of Writeback hits system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 1.916906 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 2.154784 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 10800 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52185.370951 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40014.942529 # average overall mshr miss latency -system.cpu.l2cache.demand_hits 6015 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 249707000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.443056 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 4785 # number of demand (read+write) misses +system.cpu.l2cache.demand_accesses 12027 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52334.345889 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40121.810450 # average overall mshr miss latency +system.cpu.l2cache.demand_hits 7089 # number of demand (read+write) hits +system.cpu.l2cache.demand_miss_latency 258427000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.410576 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 4938 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 191471500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.443056 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 4785 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 198121500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.410576 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 4938 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.063286 # Average percentage of cache occupancy -system.cpu.l2cache.occ_%::1 0.000543 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 2073.767582 # Average occupied blocks per context -system.cpu.l2cache.occ_blocks::1 17.791341 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 10800 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52185.370951 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40014.942529 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.066327 # Average percentage of cache occupancy +system.cpu.l2cache.occ_%::1 0.000542 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 2173.408404 # Average occupied blocks per context +system.cpu.l2cache.occ_blocks::1 17.762794 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 12027 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52334.345889 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40121.810450 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.l2cache.overall_hits 6015 # number of overall hits -system.cpu.l2cache.overall_miss_latency 249707000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.443056 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 4785 # number of overall misses +system.cpu.l2cache.overall_hits 7089 # number of overall hits +system.cpu.l2cache.overall_miss_latency 258427000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.410576 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 4938 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 191471500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.443056 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 4785 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 198121500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.410576 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 4938 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 3129 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 3282 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 2091.558923 # Cycle average of tags in use -system.cpu.l2cache.total_refs 5998 # Total number of references to valid blocks. +system.cpu.l2cache.tagsinuse 2191.171198 # Cycle average of tags in use +system.cpu.l2cache.total_refs 7072 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 196670323 # number of cpu cycles simulated -system.cpu.runCycles 187745868 # Number of cycles cpu stages are processed. +system.cpu.numCycles 81062947 # number of cpu cycles simulated +system.cpu.runCycles 74310489 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 94907524 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 101762799 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 51.742834 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 104509809 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 92160514 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 46.860407 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 103177839 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 93492484 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 47.537667 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 170172999 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 26497324 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 13.472965 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 104767267 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 91903056 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 46.729499 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 196670323 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-0.idleCycles 27951481 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 53111466 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 65.518795 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 33263015 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 47799932 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 58.966438 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 32674388 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 48388559 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 59.692573 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 63236669 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.runCycles 17826278 # Number of cycles 1+ instructions are processed. +system.cpu.stage-3.utilization 21.990661 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 26883449 # Number of cycles 0 instructions are processed. +system.cpu.stage-4.runCycles 54179498 # Number of cycles 1+ instructions are processed. +system.cpu.stage-4.utilization 66.836329 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 80608290 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.timesIdled 10787 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 389 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini index f516c45fc..0558e754e 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/config.ini @@ -35,6 +35,7 @@ div8RepeatRate=1 do_checkpoint_insts=true do_statistics_insts=true dtb=system.cpu.dtb +fetchBuffSize=4 fetchMemPort=icache_port functionTrace=false functionTraceStart=0 @@ -61,7 +62,7 @@ phase=0 predType=tournament progress_interval=0 stageTracing=false -stageWidth=1 +stageWidth=4 system=system threadModel=SMT tracer=system.cpu.tracer @@ -191,7 +192,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout index c90d08af7..98307cd85 100755 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing/simout -Redirecting stderr to build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 11:51:59 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 11:52:02 -M5 executing on zizzer -command line: build/ALPHA_SE/m5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing +M5 compiled Jan 24 2011 18:18:02 +M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip +M5 started Jan 24 2011 18:18:03 +M5 executing on zooks +command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/fast/quick/00.hello/alpha/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 30538000 because target called exit() +Exiting @ tick 22288500 because target called exit() diff --git a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt index 9ad72b38e..be248d562 100644 --- a/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,37 +1,37 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 4413 # Simulator instruction rate (inst/s) -host_mem_usage 204480 # Number of bytes of host memory used -host_seconds 1.45 # Real time elapsed on the host -host_tick_rate 21040041 # Simulator tick rate (ticks/s) +host_inst_rate 36108 # Simulator instruction rate (inst/s) +host_mem_usage 155860 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 125462283 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000031 # Number of seconds simulated -sim_ticks 30538000 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 2050 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 29.967427 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 92 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 307 # Number of BTB lookups +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 22288500 # Number of ticks simulated +system.cpu.AGEN-Unit.agens 2187 # Number of Address Generations +system.cpu.Branch-Predictor.BTBHitPct 23.015873 # BTB Hit Percentage +system.cpu.Branch-Predictor.BTBHits 87 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 378 # Number of BTB lookups system.cpu.Branch-Predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 529 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 750 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 1051 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 817 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 234 # Number of Branches Predicted As Taken (True). -system.cpu.Branch-Predictor.usedRAS 124 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 4354 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 50.333016 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 529 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 522 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 523 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 6 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Branch-Predictor.condIncorrect 543 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 995 # Number of conditional branches predicted +system.cpu.Branch-Predictor.lookups 1423 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 1183 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 240 # Number of Branches Predicted As Taken (True). +system.cpu.Branch-Predictor.usedRAS 125 # Number of times the RAS was used to get a target. +system.cpu.Execution-Unit.executions 4617 # Number of Instructions Executed. +system.cpu.Execution-Unit.mispredictPct 51.615970 # Percentage of Incorrect Branches Predicts +system.cpu.Execution-Unit.mispredicted 543 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.predicted 509 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.predictedNotTakenIncorrect 538 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 5 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 0 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 1 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 12573 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 7990 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 10532 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 5949 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 4583 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 311 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 22.376672 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 2845 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 16.048275 # Percentage of cycles cpu is active system.cpu.comBranches 1051 # Number of Branches instructions committed system.cpu.comFloats 2 # Number of Floating Point instructions committed system.cpu.comInts 3265 # Number of Integer instructions committed @@ -42,62 +42,64 @@ system.cpu.comStores 865 # Nu system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 9.537320 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 9.537320 # CPI: Total CPI of All Threads +system.cpu.cpi 6.960962 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 6.960962 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1185 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56384.210526 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53384.210526 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1090 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 5356500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.080169 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 95 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 5071500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 56781.250000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53784.210526 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1089 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 5451000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.081013 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 96 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 5109500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.080169 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56068.493151 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53068.493151 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 792 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 4093000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.084393 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 73 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 3874000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 56582.191781 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53561.643836 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 719 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 8261000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.168786 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 146 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 73 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 3910000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 73 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 11.202381 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 54000 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 10.761905 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 3 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 162000 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2050 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56247.023810 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53247.023810 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1882 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 9449500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.081951 # miss rate for demand accesses -system.cpu.dcache.demand_misses 168 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 8945500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_avg_miss_latency 56661.157025 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53687.500000 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1808 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 13712000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.118049 # miss rate for demand accesses +system.cpu.dcache.demand_misses 242 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 74 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 9019500 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.081951 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 168 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.025183 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 103.151125 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.024901 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 101.993452 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2050 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56247.023810 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53247.023810 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56661.157025 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53687.500000 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1882 # number of overall hits -system.cpu.dcache.overall_miss_latency 9449500 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.081951 # miss rate for overall accesses -system.cpu.dcache.overall_misses 168 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 8945500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 1808 # number of overall hits +system.cpu.dcache.overall_miss_latency 13712000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.118049 # miss rate for overall accesses +system.cpu.dcache.overall_misses 242 # number of overall misses +system.cpu.dcache.overall_mshr_hits 74 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 9019500 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.081951 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -105,8 +107,8 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 103.151125 # Cycle average of tags in use -system.cpu.dcache.total_refs 1882 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 101.993452 # Cycle average of tags in use +system.cpu.dcache.total_refs 1808 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dtb.data_accesses 2060 # DTB accesses @@ -125,72 +127,72 @@ system.cpu.dtb.write_accesses 868 # DT system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses -system.cpu.icache.ReadReq_accesses 7169 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55703.071672 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52873.684211 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 6876 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16321000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.040870 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 293 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_hits 8 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_miss_latency 15069000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.039754 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 285 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 955 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55326.979472 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53094.684385 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 614 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 18866500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.357068 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 341 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 40 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 15981500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.315183 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 301 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 24.211268 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.046667 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 7169 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55703.071672 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52873.684211 # average overall mshr miss latency -system.cpu.icache.demand_hits 6876 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16321000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.040870 # miss rate for demand accesses -system.cpu.icache.demand_misses 293 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 8 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15069000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.039754 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 285 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 955 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55326.979472 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53094.684385 # average overall mshr miss latency +system.cpu.icache.demand_hits 614 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 18866500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.357068 # miss rate for demand accesses +system.cpu.icache.demand_misses 341 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 40 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 15981500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.315183 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 301 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.063218 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 129.469682 # Average occupied blocks per context -system.cpu.icache.overall_accesses 7169 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55703.071672 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52873.684211 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.066887 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 136.984147 # Average occupied blocks per context +system.cpu.icache.overall_accesses 955 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55326.979472 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53094.684385 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 6876 # number of overall hits -system.cpu.icache.overall_miss_latency 16321000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.040870 # miss rate for overall accesses -system.cpu.icache.overall_misses 293 # number of overall misses -system.cpu.icache.overall_mshr_hits 8 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15069000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.039754 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 285 # number of overall MSHR misses +system.cpu.icache.overall_hits 614 # number of overall hits +system.cpu.icache.overall_miss_latency 18866500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.357068 # miss rate for overall accesses +system.cpu.icache.overall_misses 341 # number of overall misses +system.cpu.icache.overall_mshr_hits 40 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 15981500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.315183 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.sampled_refs 284 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 300 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 129.469682 # Cycle average of tags in use -system.cpu.icache.total_refs 6876 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 136.984147 # Cycle average of tags in use +system.cpu.icache.total_refs 614 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 47410 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.104851 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.104851 # IPC: Total IPC of All Threads +system.cpu.idleCycles 37424 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.143658 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.143658 # IPC: Total IPC of All Threads system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_hits 0 # DTB hits system.cpu.itb.data_misses 0 # DTB misses -system.cpu.itb.fetch_accesses 7186 # ITB accesses +system.cpu.itb.fetch_accesses 972 # ITB accesses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_hits 7169 # ITB hits +system.cpu.itb.fetch_hits 955 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.read_acv 0 # DTB read access violations @@ -201,91 +203,92 @@ system.cpu.itb.write_acv 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52068.493151 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40013.698630 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 3801000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52321.917808 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40267.123288 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 3819500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2921000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2939500 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 380 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52087.071240 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39947.229551 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 396 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52229.113924 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40054.430380 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 19741000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.997368 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 379 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15140000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997368 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 379 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 20630500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.997475 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 395 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 15821500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997475 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 395 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.002646 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002538 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 453 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52084.070796 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 39957.964602 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 469 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52243.589744 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40087.606838 # average overall mshr miss latency system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 23542000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.997792 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 452 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 24450000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.997868 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 468 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 18061000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.997792 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 452 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 18761000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.997868 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 468 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005668 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 185.735123 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 453 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52084.070796 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 39957.964602 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.005889 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 192.975400 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 469 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52243.589744 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40087.606838 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 1 # number of overall hits -system.cpu.l2cache.overall_miss_latency 23542000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.997792 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 452 # number of overall misses +system.cpu.l2cache.overall_miss_latency 24450000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.997868 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 468 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 18061000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.997792 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 452 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 18761000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.997868 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 468 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 378 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 394 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 185.735123 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 192.975400 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 61077 # number of cpu cycles simulated -system.cpu.runCycles 13667 # Number of cycles cpu stages are processed. +system.cpu.numCycles 44578 # number of cpu cycles simulated +system.cpu.runCycles 7154 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 53891 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 7186 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 11.765476 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 54525 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 6552 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 10.727442 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 54607 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 6470 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 10.593186 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 59024 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 2053 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.361331 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 54673 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 6404 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 10.485125 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 61077 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-0.idleCycles 39836 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 4742 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 10.637534 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 40747 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 3831 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 8.593925 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 40491 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 4087 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 9.168200 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 43168 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.runCycles 1410 # Number of cycles 1+ instructions are processed. +system.cpu.stage-3.utilization 3.162995 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 40170 # Number of cycles 0 instructions are processed. +system.cpu.stage-4.runCycles 4408 # Number of cycles 1+ instructions are processed. +system.cpu.stage-4.utilization 9.888286 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 11304 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.timesIdled 425 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 17 # Number of system calls ---------- End Simulation Statistics ---------- diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini index 8312243a4..d479ef8bf 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/config.ini @@ -89,6 +89,7 @@ div8RepeatRate=1 do_checkpoint_insts=true do_statistics_insts=true dtb=system.cpu.dtb +fetchBuffSize=4 fetchMemPort=icache_port functionTrace=false functionTraceStart=0 @@ -115,7 +116,7 @@ phase=0 predType=tournament progress_interval=0 stageTracing=false -stageWidth=1 +stageWidth=4 system=system threadModel=SMT tracer=system.cpu.tracer @@ -245,7 +246,7 @@ egid=100 env= errout=cerr euid=100 -executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello +executable=tests/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout index 4692f4932..dc388ddae 100755 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/simout @@ -1,5 +1,3 @@ -Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing/simout -Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -7,13 +5,13 @@ The Regents of The University of Michigan All Rights Reserved -M5 compiled Aug 26 2010 12:56:28 -M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix -M5 started Aug 26 2010 12:56:32 -M5 executing on zizzer -command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing +M5 compiled Jan 24 2011 18:37:16 +M5 revision 09e8ac96522d+ 7823+ default regression_updates qtip tip +M5 started Jan 24 2011 18:37:18 +M5 executing on zooks +command line: build/MIPS_SE/m5.fast -d build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/fast/quick/00.hello/mips/linux/inorder-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello World! -Exiting @ tick 28659500 because target called exit() +Exiting @ tick 21534000 because target called exit() diff --git a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt index 18095c949..170c01854 100644 --- a/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,37 +1,37 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 16536 # Simulator instruction rate (inst/s) -host_mem_usage 205460 # Number of bytes of host memory used -host_seconds 0.35 # Real time elapsed on the host -host_tick_rate 81268272 # Simulator tick rate (ticks/s) +host_inst_rate 32637 # Simulator instruction rate (inst/s) +host_mem_usage 156860 # Number of bytes of host memory used +host_seconds 0.18 # Real time elapsed on the host +host_tick_rate 120410651 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_insts 5827 # Number of instructions simulated -sim_seconds 0.000029 # Number of seconds simulated -sim_ticks 28659500 # Number of ticks simulated -system.cpu.AGEN-Unit.agens 2090 # Number of Address Generations -system.cpu.Branch-Predictor.BTBHitPct 15.000000 # BTB Hit Percentage -system.cpu.Branch-Predictor.BTBHits 24 # Number of BTB hits -system.cpu.Branch-Predictor.BTBLookups 160 # Number of BTB lookups -system.cpu.Branch-Predictor.RASInCorrect 35 # Number of incorrect RAS predictions. -system.cpu.Branch-Predictor.condIncorrect 556 # Number of conditional branches incorrect -system.cpu.Branch-Predictor.condPredicted 677 # Number of conditional branches predicted -system.cpu.Branch-Predictor.lookups 916 # Number of BP lookups -system.cpu.Branch-Predictor.predictedNotTaken 802 # Number of Branches Predicted As Not Taken (False). -system.cpu.Branch-Predictor.predictedTaken 114 # Number of Branches Predicted As Taken (True). +sim_seconds 0.000022 # Number of seconds simulated +sim_ticks 21534000 # Number of ticks simulated +system.cpu.AGEN-Unit.agens 2404 # Number of Address Generations +system.cpu.Branch-Predictor.BTBHitPct 14.054054 # BTB Hit Percentage +system.cpu.Branch-Predictor.BTBHits 26 # Number of BTB hits +system.cpu.Branch-Predictor.BTBLookups 185 # Number of BTB lookups +system.cpu.Branch-Predictor.RASInCorrect 30 # Number of incorrect RAS predictions. +system.cpu.Branch-Predictor.condIncorrect 845 # Number of conditional branches incorrect +system.cpu.Branch-Predictor.condPredicted 778 # Number of conditional branches predicted +system.cpu.Branch-Predictor.lookups 1066 # Number of BP lookups +system.cpu.Branch-Predictor.predictedNotTaken 949 # Number of Branches Predicted As Not Taken (False). +system.cpu.Branch-Predictor.predictedTaken 117 # Number of Branches Predicted As Taken (True). system.cpu.Branch-Predictor.usedRAS 86 # Number of times the RAS was used to get a target. -system.cpu.Execution-Unit.executions 3734 # Number of Instructions Executed. -system.cpu.Execution-Unit.mispredictPct 60.698690 # Percentage of Incorrect Branches Predicts -system.cpu.Execution-Unit.mispredicted 556 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predicted 360 # Number of Branches Incorrectly Predicted -system.cpu.Execution-Unit.predictedNotTakenIncorrect 519 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.Execution-Unit.predictedTakenIncorrect 37 # Number of Branches Incorrectly Predicted As Taken. +system.cpu.Execution-Unit.executions 3963 # Number of Instructions Executed. +system.cpu.Execution-Unit.mispredictPct 92.148310 # Percentage of Incorrect Branches Predicts +system.cpu.Execution-Unit.mispredicted 845 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.predicted 72 # Number of Branches Incorrectly Predicted +system.cpu.Execution-Unit.predictedNotTakenIncorrect 813 # Number of Branches Incorrectly Predicted As Not Taken). +system.cpu.Execution-Unit.predictedTakenIncorrect 32 # Number of Branches Incorrectly Predicted As Taken. system.cpu.Mult-Div-Unit.divides 1 # Number of Divide Operations Executed system.cpu.Mult-Div-Unit.multiplies 3 # Number of Multipy Operations Executed -system.cpu.RegFile-Manager.regFileAccesses 10688 # Number of Total Accesses (Read+Write) to the Register File -system.cpu.RegFile-Manager.regFileReads 7278 # Number of Reads from Register File +system.cpu.RegFile-Manager.regFileAccesses 10006 # Number of Total Accesses (Read+Write) to the Register File +system.cpu.RegFile-Manager.regFileReads 6596 # Number of Reads from Register File system.cpu.RegFile-Manager.regFileWrites 3410 # Number of Writes to Register File -system.cpu.RegFile-Manager.regForwards 25 # Number of Registers Read Through Forwarding Logic -system.cpu.activity 20.706560 # Percentage of cycles cpu is active +system.cpu.RegFile-Manager.regForwards 1378 # Number of Registers Read Through Forwarding Logic +system.cpu.activity 13.935777 # Percentage of cycles cpu is active system.cpu.comBranches 916 # Number of Branches instructions committed system.cpu.comFloats 0 # Number of Floating Point instructions committed system.cpu.comInts 2155 # Number of Integer instructions committed @@ -42,62 +42,64 @@ system.cpu.comStores 925 # Nu system.cpu.committedInsts 5827 # Number of Instructions Simulated (Per-Thread) system.cpu.committedInsts_total 5827 # Number of Instructions Simulated (Total) system.cpu.contextSwitches 1 # Number of context switches -system.cpu.cpi 9.836966 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.cpi_total 9.836966 # CPI: Total CPI of All Threads +system.cpu.cpi 7.391282 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi_total 7.391282 # CPI: Total CPI of All Threads system.cpu.dcache.ReadReq_accesses 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_avg_miss_latency 56229.885057 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53229.885057 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_hits 1077 # number of ReadReq hits -system.cpu.dcache.ReadReq_miss_latency 4892000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_rate 0.074742 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_misses 87 # number of ReadReq misses -system.cpu.dcache.ReadReq_mshr_miss_latency 4631000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_avg_miss_latency 56681.818182 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53683.908046 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_hits 1076 # number of ReadReq hits +system.cpu.dcache.ReadReq_miss_latency 4988000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_rate 0.075601 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_misses 88 # number of ReadReq misses +system.cpu.dcache.ReadReq_mshr_hits 1 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_miss_latency 4670500 # number of ReadReq MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate 0.074742 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_misses 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_accesses 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_avg_miss_latency 56254.901961 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53254.901961 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_hits 874 # number of WriteReq hits -system.cpu.dcache.WriteReq_miss_latency 2869000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_rate 0.055135 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_misses 51 # number of WriteReq misses -system.cpu.dcache.WriteReq_mshr_miss_latency 2716000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_avg_miss_latency 55935.483871 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53637.254902 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_hits 832 # number of WriteReq hits +system.cpu.dcache.WriteReq_miss_latency 5202000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_rate 0.100541 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_misses 93 # number of WriteReq misses +system.cpu.dcache.WriteReq_mshr_hits 42 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_miss_latency 2735500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_rate 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_misses 51 # number of WriteReq MSHR misses system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. +system.cpu.dcache.avg_blocked_cycles::no_targets 53100 # average number of cycles each access was blocked +system.cpu.dcache.avg_refs 13.826087 # Average number of references to valid blocks. system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 5 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 265500 # number of cycles access was blocked system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.demand_accesses 2089 # number of demand (read+write) accesses -system.cpu.dcache.demand_avg_miss_latency 56239.130435 # average overall miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency 53239.130435 # average overall mshr miss latency -system.cpu.dcache.demand_hits 1951 # number of demand (read+write) hits -system.cpu.dcache.demand_miss_latency 7761000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_rate 0.066060 # miss rate for demand accesses -system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses -system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_miss_latency 7347000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_avg_miss_latency 56298.342541 # average overall miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency 53666.666667 # average overall mshr miss latency +system.cpu.dcache.demand_hits 1908 # number of demand (read+write) hits +system.cpu.dcache.demand_miss_latency 10190000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_rate 0.086644 # miss rate for demand accesses +system.cpu.dcache.demand_misses 181 # number of demand (read+write) misses +system.cpu.dcache.demand_mshr_hits 43 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_miss_latency 7406000 # number of demand (read+write) MSHR miss cycles system.cpu.dcache.demand_mshr_miss_rate 0.066060 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.occ_%::0 0.021533 # Average percentage of cache occupancy -system.cpu.dcache.occ_blocks::0 88.199028 # Average occupied blocks per context +system.cpu.dcache.occ_%::0 0.021745 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::0 89.066455 # Average occupied blocks per context system.cpu.dcache.overall_accesses 2089 # number of overall (read+write) accesses -system.cpu.dcache.overall_avg_miss_latency 56239.130435 # average overall miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency 53239.130435 # average overall mshr miss latency +system.cpu.dcache.overall_avg_miss_latency 56298.342541 # average overall miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency 53666.666667 # average overall mshr miss latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.dcache.overall_hits 1951 # number of overall hits -system.cpu.dcache.overall_miss_latency 7761000 # number of overall miss cycles -system.cpu.dcache.overall_miss_rate 0.066060 # miss rate for overall accesses -system.cpu.dcache.overall_misses 138 # number of overall misses -system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_miss_latency 7347000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_hits 1908 # number of overall hits +system.cpu.dcache.overall_miss_latency 10190000 # number of overall miss cycles +system.cpu.dcache.overall_miss_rate 0.086644 # miss rate for overall accesses +system.cpu.dcache.overall_misses 181 # number of overall misses +system.cpu.dcache.overall_mshr_hits 43 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_miss_latency 7406000 # number of overall MSHR miss cycles system.cpu.dcache.overall_mshr_miss_rate 0.066060 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles @@ -105,8 +107,8 @@ system.cpu.dcache.overall_mshr_uncacheable_misses 0 system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.dcache.tagsinuse 88.199028 # Cycle average of tags in use -system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 89.066455 # Cycle average of tags in use +system.cpu.dcache.total_refs 1908 # Total number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.dcache.writebacks 0 # number of writebacks system.cpu.dtb.accesses 0 # DTB accesses @@ -118,64 +120,65 @@ system.cpu.dtb.read_misses 0 # DT system.cpu.dtb.write_accesses 0 # DTB write accesses system.cpu.dtb.write_hits 0 # DTB write hits system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.icache.ReadReq_accesses 5869 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_avg_miss_latency 55795.379538 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency 52795.379538 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_hits 5566 # number of ReadReq hits -system.cpu.icache.ReadReq_miss_latency 16906000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_rate 0.051627 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses -system.cpu.icache.ReadReq_mshr_miss_latency 15997000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate 0.051627 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_misses 303 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_accesses 853 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_avg_miss_latency 55526.246719 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency 53153.605016 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_hits 472 # number of ReadReq hits +system.cpu.icache.ReadReq_miss_latency 21155500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_rate 0.446659 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_misses 381 # number of ReadReq misses +system.cpu.icache.ReadReq_mshr_hits 62 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_miss_latency 16956000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate 0.373974 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_misses 319 # number of ReadReq MSHR misses system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.icache.avg_refs 18.369637 # Average number of references to valid blocks. +system.cpu.icache.avg_blocked_cycles::no_targets 31000 # average number of cycles each access was blocked +system.cpu.icache.avg_refs 1.479624 # Average number of references to valid blocks. system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 62000 # number of cycles access was blocked system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.demand_accesses 5869 # number of demand (read+write) accesses -system.cpu.icache.demand_avg_miss_latency 55795.379538 # average overall miss latency -system.cpu.icache.demand_avg_mshr_miss_latency 52795.379538 # average overall mshr miss latency -system.cpu.icache.demand_hits 5566 # number of demand (read+write) hits -system.cpu.icache.demand_miss_latency 16906000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_rate 0.051627 # miss rate for demand accesses -system.cpu.icache.demand_misses 303 # number of demand (read+write) misses -system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_miss_latency 15997000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_rate 0.051627 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_misses 303 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_accesses 853 # number of demand (read+write) accesses +system.cpu.icache.demand_avg_miss_latency 55526.246719 # average overall miss latency +system.cpu.icache.demand_avg_mshr_miss_latency 53153.605016 # average overall mshr miss latency +system.cpu.icache.demand_hits 472 # number of demand (read+write) hits +system.cpu.icache.demand_miss_latency 21155500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_rate 0.446659 # miss rate for demand accesses +system.cpu.icache.demand_misses 381 # number of demand (read+write) misses +system.cpu.icache.demand_mshr_hits 62 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_miss_latency 16956000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_rate 0.373974 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_misses 319 # number of demand (read+write) MSHR misses system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.occ_%::0 0.065748 # Average percentage of cache occupancy -system.cpu.icache.occ_blocks::0 134.651831 # Average occupied blocks per context -system.cpu.icache.overall_accesses 5869 # number of overall (read+write) accesses -system.cpu.icache.overall_avg_miss_latency 55795.379538 # average overall miss latency -system.cpu.icache.overall_avg_mshr_miss_latency 52795.379538 # average overall mshr miss latency +system.cpu.icache.occ_%::0 0.070944 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::0 145.293265 # Average occupied blocks per context +system.cpu.icache.overall_accesses 853 # number of overall (read+write) accesses +system.cpu.icache.overall_avg_miss_latency 55526.246719 # average overall miss latency +system.cpu.icache.overall_avg_mshr_miss_latency 53153.605016 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency -system.cpu.icache.overall_hits 5566 # number of overall hits -system.cpu.icache.overall_miss_latency 16906000 # number of overall miss cycles -system.cpu.icache.overall_miss_rate 0.051627 # miss rate for overall accesses -system.cpu.icache.overall_misses 303 # number of overall misses -system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.icache.overall_mshr_miss_latency 15997000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_rate 0.051627 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_misses 303 # number of overall MSHR misses +system.cpu.icache.overall_hits 472 # number of overall hits +system.cpu.icache.overall_miss_latency 21155500 # number of overall miss cycles +system.cpu.icache.overall_miss_rate 0.446659 # miss rate for overall accesses +system.cpu.icache.overall_misses 381 # number of overall misses +system.cpu.icache.overall_mshr_hits 62 # number of overall MSHR hits +system.cpu.icache.overall_mshr_miss_latency 16956000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_rate 0.373974 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_misses 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. +system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.icache.tagsinuse 134.651831 # Cycle average of tags in use -system.cpu.icache.total_refs 5566 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 145.293265 # Cycle average of tags in use +system.cpu.icache.total_refs 472 # Total number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.icache.writebacks 0 # number of writebacks -system.cpu.idleCycles 45451 # Number of cycles cpu's stages were not processed -system.cpu.ipc 0.101657 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.ipc_total 0.101657 # IPC: Total IPC of All Threads +system.cpu.idleCycles 37067 # Number of cycles cpu's stages were not processed +system.cpu.ipc 0.135295 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.ipc_total 0.135295 # IPC: Total IPC of All Threads system.cpu.itb.accesses 0 # DTB accesses system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses @@ -186,91 +189,92 @@ system.cpu.itb.write_accesses 0 # DT system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_avg_miss_latency 52254.901961 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40098.039216 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_miss_latency 2665000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_avg_miss_latency 52470.588235 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40235.294118 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_miss_latency 2676000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_mshr_miss_latency 2045000 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency 2052000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadReq_accesses 390 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_avg_miss_latency 52086.340206 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40048.969072 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_avg_miss_latency 52355.198020 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40152.227723 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_miss_latency 20209500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_rate 0.994872 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_misses 388 # number of ReadReq misses -system.cpu.l2cache.ReadReq_mshr_miss_latency 15539000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_miss_latency 21151500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses +system.cpu.l2cache.ReadReq_mshr_miss_latency 16221500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. +system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.demand_accesses 441 # number of demand (read+write) accesses -system.cpu.l2cache.demand_avg_miss_latency 52105.922551 # average overall miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency +system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses +system.cpu.l2cache.demand_avg_miss_latency 52368.131868 # average overall miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency 40161.538462 # average overall mshr miss latency system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_miss_latency 22874500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_rate 0.995465 # miss rate for demand accesses -system.cpu.l2cache.demand_misses 439 # number of demand (read+write) misses +system.cpu.l2cache.demand_miss_latency 23827500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses +system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_miss_latency 17584000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_miss_latency 18273500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.occ_%::0 0.005821 # Average percentage of cache occupancy -system.cpu.l2cache.occ_blocks::0 190.726729 # Average occupied blocks per context -system.cpu.l2cache.overall_accesses 441 # number of overall (read+write) accesses -system.cpu.l2cache.overall_avg_miss_latency 52105.922551 # average overall miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency 40054.669704 # average overall mshr miss latency +system.cpu.l2cache.occ_%::0 0.006169 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::0 202.148379 # Average occupied blocks per context +system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses +system.cpu.l2cache.overall_avg_miss_latency 52368.131868 # average overall miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency 40161.538462 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency system.cpu.l2cache.overall_hits 2 # number of overall hits -system.cpu.l2cache.overall_miss_latency 22874500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_rate 0.995465 # miss rate for overall accesses -system.cpu.l2cache.overall_misses 439 # number of overall misses +system.cpu.l2cache.overall_miss_latency 23827500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses +system.cpu.l2cache.overall_misses 455 # number of overall misses system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_miss_latency 17584000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_miss_latency 18273500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu.l2cache.tagsinuse 190.726729 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 202.148379 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.writebacks 0 # number of writebacks -system.cpu.numCycles 57320 # number of cpu cycles simulated -system.cpu.runCycles 11869 # Number of cycles cpu stages are processed. +system.cpu.numCycles 43069 # number of cpu cycles simulated +system.cpu.runCycles 6002 # Number of cycles cpu stages are processed. system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode system.cpu.smt_cpi no_value # CPI: Total SMT-CPI system.cpu.smt_ipc no_value # IPC: Total SMT-IPC -system.cpu.stage-0.idleCycles 51451 # Number of cycles 0 instructions are processed. -system.cpu.stage-0.runCycles 5869 # Number of cycles 1+ instructions are processed. -system.cpu.stage-0.utilization 10.239009 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-1.idleCycles 51492 # Number of cycles 0 instructions are processed. -system.cpu.stage-1.runCycles 5828 # Number of cycles 1+ instructions are processed. -system.cpu.stage-1.utilization 10.167481 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-2.idleCycles 51488 # Number of cycles 0 instructions are processed. -system.cpu.stage-2.runCycles 5832 # Number of cycles 1+ instructions are processed. -system.cpu.stage-2.utilization 10.174459 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-3.idleCycles 55230 # Number of cycles 0 instructions are processed. -system.cpu.stage-3.runCycles 2090 # Number of cycles 1+ instructions are processed. -system.cpu.stage-3.utilization 3.646197 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage-4.idleCycles 51493 # Number of cycles 0 instructions are processed. -system.cpu.stage-4.runCycles 5827 # Number of cycles 1+ instructions are processed. -system.cpu.stage-4.utilization 10.165736 # Percentage of cycles stage was utilized (processing insts). -system.cpu.threadCycles 57320 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.stage-0.idleCycles 39196 # Number of cycles 0 instructions are processed. +system.cpu.stage-0.runCycles 3873 # Number of cycles 1+ instructions are processed. +system.cpu.stage-0.utilization 8.992547 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-1.idleCycles 40152 # Number of cycles 0 instructions are processed. +system.cpu.stage-1.runCycles 2917 # Number of cycles 1+ instructions are processed. +system.cpu.stage-1.utilization 6.772853 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-2.idleCycles 40243 # Number of cycles 0 instructions are processed. +system.cpu.stage-2.runCycles 2826 # Number of cycles 1+ instructions are processed. +system.cpu.stage-2.utilization 6.561564 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-3.idleCycles 41749 # Number of cycles 0 instructions are processed. +system.cpu.stage-3.runCycles 1320 # Number of cycles 1+ instructions are processed. +system.cpu.stage-3.utilization 3.064849 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage-4.idleCycles 39866 # Number of cycles 0 instructions are processed. +system.cpu.stage-4.runCycles 3203 # Number of cycles 1+ instructions are processed. +system.cpu.stage-4.utilization 7.436904 # Percentage of cycles stage was utilized (processing insts). +system.cpu.threadCycles 10184 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.timesIdled 427 # Number of times that the entire CPU went into an idle state and unscheduled itself system.cpu.workload.PROG:num_syscalls 8 # Number of system calls ---------- End Simulation Statistics ---------- |