ARM: Add new templates for branch instructions.

2 files changed, 180 insertions, 0 deletions

diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
new file mode 100644
index 000000000..a666c28fa
--- /dev/null
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -0,0 +1,177 @@
+// -*- mode:c++ -*-
+
+// Copyright (c) 2010 ARM Limited
+// All rights reserved
+//
+// The license below extends only to copyright in the software and shall
+// not be construed as granting a license to any other intellectual
+// property including but not limited to intellectual property relating
+// to a hardware implementation of the functionality of the software
+// licensed hereunder.  You may use the software subject to the license
+// terms below provided that you ensure that this notice is replicated
+// unmodified and in its entirety in all distributions of the software,
+// modified or unmodified, in source code or in binary form.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Gabe Black
+
+def template BranchImmDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst, int32_t _imm);
+        %(BasicExecDeclare)s
+};
+}};
+
+def template BranchImmConstructor {{
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          int32_t _imm)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm)
+    {
+        %(constructor)s;
+    }
+}};
+
+def template BranchImmCondDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst, int32_t _imm,
+                       ConditionCode _condCode);
+        %(BasicExecDeclare)s
+};
+}};
+
+def template BranchImmCondConstructor {{
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          int32_t _imm,
+                                          ConditionCode _condCode)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+                         _imm, _condCode)
+    {
+        %(constructor)s;
+    }
+}};
+
+def template BranchRegDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
+        %(BasicExecDeclare)s
+};
+}};
+
+def template BranchRegConstructor {{
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          IntRegIndex _op1)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
+    {
+        %(constructor)s;
+    }
+}};
+
+def template BranchRegCondDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
+                       ConditionCode _condCode);
+        %(BasicExecDeclare)s
+};
+}};
+
+def template BranchRegCondConstructor {{
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          IntRegIndex _op1,
+                                          ConditionCode _condCode)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
+                         _op1, _condCode)
+    {
+        %(constructor)s;
+    }
+}};
+
+def template BranchRegRegDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst,
+                       IntRegIndex _op1, IntRegIndex _op2);
+        %(BasicExecDeclare)s
+};
+}};
+
+def template BranchTableDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst,
+                       IntRegIndex _op1, IntRegIndex _op2);
+        %(BasicExecDeclare)s
+
+        %(InitiateAccDeclare)s
+
+        %(CompleteAccDeclare)s
+};
+}};
+
+def template BranchRegRegConstructor {{
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          IntRegIndex _op1,
+                                          IntRegIndex _op2)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
+    {
+        %(constructor)s;
+    }
+}};
+
+def template BranchImmRegDeclare {{
+class %(class_name)s : public %(base_class)s
+{
+    public:
+        // Constructor
+        %(class_name)s(ExtMachInst machInst,
+                       int32_t imm, IntRegIndex _op1);
+        %(BasicExecDeclare)s
+};
+}};
+
+def template BranchImmRegConstructor {{
+    inline %(class_name)s::%(class_name)s(ExtMachInst machInst,
+                                          int32_t _imm,
+                                          IntRegIndex _op1)
+        : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
+    {
+        %(constructor)s;
+    }
+}};
diff --git a/src/arch/arm/isa/templates/templates.isa b/src/arch/arm/isa/templates/templates.isa
index 821e0f82e..505c5d6c5 100644
--- a/src/arch/arm/isa/templates/templates.isa
+++ b/src/arch/arm/isa/templates/templates.isa
@@ -45,3 +45,6 @@
 
 //Templates for microcoded memory instructions
 ##include "macromem.isa"
+
+//Templates for branches
+##include "branch.isa"