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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:49 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-05-09 18:58:49 -0400 |
| commit | aa329f4757639820f921bf4152c21e79da74c034 (patch) | |
| tree | 8b0feb741790f9339e2c4dda97c551592a42fa60 | |
| parent | 64806c4c13040832dd1e24b8fb0c347cd794398e (diff) | |
| download | gem5-aa329f4757639820f921bf4152c21e79da74c034.tar.xz | |
config: Bump DRAM sweep bus speed to match DDR4 config
This patch bumps the bus clock speed such that the interconnect does
not become a bottleneck with a DDR4-2400-x64 DRAM delivering 19.2
GByte/s theoretical max.
| -rw-r--r-- | configs/dram/sweep.py | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/configs/dram/sweep.py b/configs/dram/sweep.py index 5981d59dd..c1ee0ceca 100644 --- a/configs/dram/sweep.py +++ b/configs/dram/sweep.py @@ -67,11 +67,11 @@ if args: # at the moment we stay with the default open-adaptive page policy, # and address mapping -# start with the system itself, using a multi-layer 1 GHz +# start with the system itself, using a multi-layer 1.5 GHz # bus/crossbar, delivering 64 bytes / 5 cycles (one header cycle) -# which amounts to 12.8 GByte/s per layer and thus per port +# which amounts to 19.2 GByte/s per layer and thus per port system = System(membus = NoncoherentBus(width = 16)) -system.clk_domain = SrcClockDomain(clock = '1GHz', +system.clk_domain = SrcClockDomain(clock = '1.5GHz', voltage_domain = VoltageDomain(voltage = '1V')) |