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| author | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-10 12:07:21 -0400 |
|---|---|---|
| committer | Ron Dreslinski <rdreslin@umich.edu> | 2006-07-10 12:07:21 -0400 |
| commit | aef232a942935e01c26522c20cc7fb3609075a7d (patch) | |
| tree | dca3d251a335b33331798764d722682f7ac950ab | |
| parent | 6c9bde608b9a58ba876e5c243a896d25e50bc500 (diff) | |
| download | gem5-aef232a942935e01c26522c20cc7fb3609075a7d.tar.xz | |
Update FS configs to use cpu connectors for ports
--HG--
extra : convert_revision : 1e2e503401f92c1f30e2e487d7aeed1c7c5b7ee4
| -rw-r--r-- | configs/test/fs.py | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/configs/test/fs.py b/configs/test/fs.py index e0dd38e41..cd894ab73 100644 --- a/configs/test/fs.py +++ b/configs/test/fs.py @@ -190,6 +190,8 @@ class MyLinuxAlphaSystem(LinuxAlphaSystem): else: cpu = AtomicSimpleCPU() cpu.mem = magicbus2 + cpu.icache_port = magicbus2.port + cpu.dcache_port = magicbus2.port cpu.itb = AlphaITB() cpu.dtb = AlphaDTB() sim_console = SimConsole(listener=ConsoleListener(port=3456)) |