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authorKevin Lim <ktlim@umich.edu>2005-02-25 18:01:19 -0500
committerKevin Lim <ktlim@umich.edu>2005-02-25 18:01:19 -0500
commitbb41c21d6ae3417cfcbfa1bb5ecc9efbae1950ab (patch)
tree89104e5d242908a1792850ec60b9e0510aa45e3c
parent5c4714c1a91680a0253f866958a9db80cd8decb2 (diff)
parentd697721f570add1dce1d96f76df09e44bb4b7a99 (diff)
downloadgem5-bb41c21d6ae3417cfcbfa1bb5ecc9efbae1950ab.tar.xz
Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
into zamp.eecs.umich.edu:/z/ktlim2/m5 --HG-- extra : convert_revision : ba556bbc93275fcd920a0529383fd480bb7218de
-rw-r--r--arch/alpha/alpha_memory.cc29
-rw-r--r--arch/alpha/isa_traits.hh3
-rw-r--r--base/traceflags.py2
-rw-r--r--configs/boot/micro_memlat.rcS3
-rw-r--r--configs/boot/micro_syscall.rcS3
-rw-r--r--cpu/exetrace.cc2
-rw-r--r--objects/SimConsole.mpy2
-rw-r--r--sim/process.cc2
-rw-r--r--sim/process.hh6
-rw-r--r--sim/pyconfig/m5config.py141
-rw-r--r--sim/syscall_emul.hh4
-rwxr-xr-x[-rw-r--r--]test/genini.py8
12 files changed, 88 insertions, 117 deletions
diff --git a/arch/alpha/alpha_memory.cc b/arch/alpha/alpha_memory.cc
index 639abbeb8..8f6d7a51a 100644
--- a/arch/alpha/alpha_memory.cc
+++ b/arch/alpha/alpha_memory.cc
@@ -68,24 +68,27 @@ AlphaTLB::~AlphaTLB()
AlphaISA::PTE *
AlphaTLB::lookup(Addr vpn, uint8_t asn) const
{
- DPRINTF(TLB, "lookup %#x, asn %#x\n", vpn, (int)asn);
+ // assume not found...
+ AlphaISA::PTE *retval = NULL;
PageTable::const_iterator i = lookupTable.find(vpn);
- if (i == lookupTable.end())
- return NULL;
-
- while (i->first == vpn) {
- int index = i->second;
- AlphaISA::PTE *pte = &table[index];
- assert(pte->valid);
- if (vpn == pte->tag && (pte->asma || pte->asn == asn))
- return pte;
+ if (i != lookupTable.end()) {
+ while (i->first == vpn) {
+ int index = i->second;
+ AlphaISA::PTE *pte = &table[index];
+ assert(pte->valid);
+ if (vpn == pte->tag && (pte->asma || pte->asn == asn)) {
+ retval = pte;
+ break;
+ }
- ++i;
+ ++i;
+ }
}
- // not found...
- return NULL;
+ DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
+ retval ? "hit" : "miss", retval ? retval->ppn : 0);
+ return retval;
}
diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index bf184b875..9e286924b 100644
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -179,6 +179,9 @@ static const Addr PageOffset = PageBytes - 1;
static StaticInstPtr<AlphaISA> decodeInst(MachInst);
+ // return a no-op instruction... used for instruction fetch faults
+ static const MachInst NoopMachInst;
+
enum annotes {
ANNOTE_NONE = 0,
// An impossible number for instruction annotations
diff --git a/base/traceflags.py b/base/traceflags.py
index 496647116..8777cdb84 100644
--- a/base/traceflags.py
+++ b/base/traceflags.py
@@ -110,7 +110,7 @@ baseFlags = [
'IICMore',
'MSHR',
'Chains',
- 'Dispatch',
+ 'Pipeline',
'Stats',
'StatEvents',
'Context',
diff --git a/configs/boot/micro_memlat.rcS b/configs/boot/micro_memlat.rcS
new file mode 100644
index 000000000..50ee8efb3
--- /dev/null
+++ b/configs/boot/micro_memlat.rcS
@@ -0,0 +1,3 @@
+/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_mem_rd 512 64
+m5 exit
+
diff --git a/configs/boot/micro_syscall.rcS b/configs/boot/micro_syscall.rcS
new file mode 100644
index 000000000..0e8e209c1
--- /dev/null
+++ b/configs/boot/micro_syscall.rcS
@@ -0,0 +1,3 @@
+/benchmarks/micros/lmbench/bin/alphaev6-linux-gnu/lat_syscall null
+m5 exit
+
diff --git a/cpu/exetrace.cc b/cpu/exetrace.cc
index ff7e90c9e..048a7d283 100644
--- a/cpu/exetrace.cc
+++ b/cpu/exetrace.cc
@@ -154,7 +154,7 @@ class ExecutionTraceParamContext : public ParamContext
ExecutionTraceParamContext exeTraceParams("exetrace");
Param<bool> exe_trace_spec(&exeTraceParams, "speculative",
- "capture speculative instructions", false);
+ "capture speculative instructions", true);
Param<bool> exe_trace_print_cycle(&exeTraceParams, "print_cycle",
"print cycle number", true);
diff --git a/objects/SimConsole.mpy b/objects/SimConsole.mpy
index ab88db8c6..fb74f1775 100644
--- a/objects/SimConsole.mpy
+++ b/objects/SimConsole.mpy
@@ -8,4 +8,4 @@ simobj SimConsole(SimObject):
intr_control = Param.IntrControl(Super, "interrupt controller")
listener = Param.ConsoleListener("console listener")
number = Param.Int(0, "console number")
- output = Param.String('', "file to dump output to")
+ output = Param.String('console', "file to dump output to")
diff --git a/sim/process.cc b/sim/process.cc
index 4d860c51d..acc6762f8 100644
--- a/sim/process.cc
+++ b/sim/process.cc
@@ -287,7 +287,7 @@ LiveProcess::LiveProcess(const string &name, ObjectFile *objFile,
// Set up region for mmaps. Tru64 seems to start just above 0 and
// grow up from there.
- mmap_base = 0x10000;
+ mmap_start = mmap_end = 0x10000;
// Set pointer for next thread stack. Reserve 8M for main stack.
next_thread_stack_base = stack_base - (8 * 1024 * 1024);
diff --git a/sim/process.hh b/sim/process.hh
index 817ab656c..3bcc65da6 100644
--- a/sim/process.hh
+++ b/sim/process.hh
@@ -93,7 +93,8 @@ class Process : public SimObject
Addr next_thread_stack_base;
// Base of region for mmaps (when user doesn't specify an address).
- Addr mmap_base;
+ Addr mmap_start;
+ Addr mmap_end;
std::string prog_fname; // file name
Addr prog_entry; // entry point (initial PC)
@@ -158,7 +159,8 @@ class Process : public SimObject
{
return ((data_base <= addr && addr < brk_point) ||
((stack_base - 16*1024*1024) <= addr && addr < stack_base) ||
- (text_base <= addr && addr < (text_base + text_size)));
+ (text_base <= addr && addr < (text_base + text_size)) ||
+ (mmap_start <= addr && addr < mmap_end));
}
virtual void syscall(ExecContext *xc) = 0;
diff --git a/sim/pyconfig/m5config.py b/sim/pyconfig/m5config.py
index 9a48e2fa4..50032476c 100644
--- a/sim/pyconfig/m5config.py
+++ b/sim/pyconfig/m5config.py
@@ -35,20 +35,10 @@ except:
env = {}
env.update(os.environ)
-def panic(*args, **kwargs):
+def panic(string):
print >>sys.stderr, 'panic:', string
sys.exit(1)
-def AddToPath(path):
- path = os.path.realpath(path)
- if os.path.isdir(path) and path not in sys.path:
- sys.path.append(path)
-
-def Import(path):
- AddToPath(os.path.dirname(path))
- exec('from m5config import *')
- mpy_exec(file(path, 'r'))
-
def issequence(value):
return isinstance(value, tuple) or isinstance(value, list)
@@ -287,8 +277,7 @@ class MetaConfigNode(type):
# deal with them as params.
return super(MetaConfigNode, mcls).__new__(mcls, name, bases, priv)
- # initialization: start out with an empty _params dict (makes life
- # simpler if we can assume _params is always valid).
+ # initialization
def __init__(cls, name, bases, dict):
super(MetaConfigNode, cls).__init__(cls, name, bases, {})
@@ -396,8 +385,11 @@ class MetaConfigNode(type):
if cls._isvalue(attr):
return Value(cls, attr)
+ if attr == '_cppname' and hasattr(cls, 'type'):
+ return cls.type + '*'
+
raise AttributeError, \
- "object '%s' has no attribute '%s'" % (cls.__name__, cls)
+ "object '%s' has no attribute '%s'" % (cls.__name__, attr)
# Set attribute (called on foo.attr = value when foo is an
# instance of class cls).
@@ -577,11 +569,6 @@ class SimObject(ConfigNode):
for pname in param_names]
code += "\n".join(decls) + "\n"
code += "END_DECLARE_SIM_OBJECT_PARAMS(%s)\n\n" % name
- code += "BEGIN_INIT_SIM_OBJECT_PARAMS(%s)\n" % name
- inits = [" " + cls._params[pname].sim_init(pname) \
- for pname in param_names]
- code += ",\n".join(inits) + "\n"
- code += "END_INIT_SIM_OBJECT_PARAMS(%s)\n\n" % name
return code
_sim_code = classmethod(_sim_code)
@@ -620,14 +607,13 @@ class Node(object):
self.path = '.'.join(path)
def find(self, realtype, path):
- rtype = eval(realtype)
if not path:
- if issubclass(self.realtype, rtype):
+ if issubclass(self.realtype, realtype):
return self, True
obj = None
for child in self.children:
- if issubclass(child.realtype, rtype):
+ if issubclass(child.realtype, realtype):
if obj is not None:
raise AttributeError, \
'Super matched more than one: %s %s' % \
@@ -643,11 +629,11 @@ class Node(object):
last = path[-1]
if obj.child_names.has_key(last):
value = obj.child_names[last]
- if issubclass(value.realtype, rtype):
+ if issubclass(value.realtype, realtype):
return value, True
elif obj.param_names.has_key(last):
value = obj.param_names[last]
- rtype._convert(value.value)
+ realtype._convert(value.value)
return value.value, True
except KeyError:
pass
@@ -754,8 +740,7 @@ class Node(object):
except:
print 'exception in %s:%s' % (self.name, param.name)
raise
- ptype = eval(param.ptype)
- if isConfigNode(ptype) and string != "Null":
+ if isConfigNode(param.ptype) and string != "Null":
simobjs.append(string)
else:
label += '%s = %s\\n' % (param.name, string)
@@ -830,8 +815,10 @@ class Value(object):
# Regular parameter.
class _Param(object):
- def __init__(self, ptype, *args, **kwargs):
- self.ptype = ptype
+ def __init__(self, ptype_string, *args, **kwargs):
+ self.ptype_string = ptype_string
+ # can't eval ptype_string here to get ptype, since the type might
+ # not have been defined yet. Do it lazily in __getattr__.
if args:
if len(args) == 1:
@@ -858,44 +845,32 @@ class _Param(object):
if not hasattr(self, 'desc'):
raise TypeError, 'desc attribute missing'
+ def __getattr__(self, attr):
+ if attr == 'ptype':
+ try:
+ self.ptype = eval(self.ptype_string)
+ return self.ptype
+ except:
+ raise TypeError, 'Param.%s: undefined type' % self.ptype_string
+ else:
+ raise AttributeError, "'%s' object has no attribute '%s'" % \
+ (type(self).__name__, attr)
+
def valid(self, value):
if not isinstance(value, Proxy):
- ptype = eval(self.ptype)
- ptype._convert(value)
+ self.ptype._convert(value)
def convert(self, value):
- ptype = eval(self.ptype)
- return ptype._convert(value)
+ return self.ptype._convert(value)
def string(self, value):
- ptype = eval(self.ptype)
- return ptype._string(value)
-
- def get(self, name, instance, owner):
- # nothing to do if None or already correct type. Also allow NULL
- # pointer to be assigned where a SimObject is expected.
- try:
- if value == None or isinstance(value, self.ptype) or \
- isConfigNode(self.ptype) and \
- (isNullPointer(value) or issubclass(value, self.ptype)):
- return value
-
- except TypeError:
- # this type conversion will raise an exception if it's illegal
- return self.ptype(value)
+ return self.ptype._string(value)
def set(self, name, instance, value):
instance.__dict__[name] = value
def sim_decl(self, name):
- return 'Param<%s> %s;' % (self.ptype.__name__, name)
-
- def sim_init(self, name):
- if self.default == None:
- return 'INIT_PARAM(%s, "%s")' % (name, self.desc)
- else:
- return 'INIT_PARAM_DFLT(%s, "%s", %s)' % \
- (name, self.desc, str(self.default))
+ return '%s %s;' % (self.ptype._cppname, name)
class _ParamProxy(object):
def __init__(self, type):
@@ -931,13 +906,12 @@ class _VectorParam(_Param):
if value == None:
return True
- ptype = eval(self.ptype)
if issequence(value):
for val in value:
if not isinstance(val, Proxy):
- ptype._convert(val)
+ self.ptype._convert(val)
elif not isinstance(value, Proxy):
- ptype._convert(value)
+ self.ptype._convert(value)
# Convert assigned value to appropriate type. If the RHS is not a
# list or tuple, it generates a single-element list.
@@ -945,23 +919,21 @@ class _VectorParam(_Param):
if value == None:
return []
- ptype = eval(self.ptype)
if issequence(value):
# list: coerce each element into new list
- return [ ptype._convert(v) for v in value ]
+ return [ self.ptype._convert(v) for v in value ]
else:
# singleton: coerce & wrap in a list
- return ptype._convert(value)
+ return self.ptype._convert(value)
def string(self, value):
- ptype = eval(self.ptype)
if issequence(value):
- return ' '.join([ ptype._string(v) for v in value])
+ return ' '.join([ self.ptype._string(v) for v in value])
else:
- return ptype._string(value)
+ return self.ptype._string(value)
def sim_decl(self, name):
- return 'VectorParam<%s> %s;' % (self.ptype.__name__, name)
+ return 'std::vector<%s> %s;' % (self.ptype._cppname, name)
class _VectorParamProxy(_ParamProxy):
# E.g., VectorParam.Int(5, "number of widgets")
@@ -1008,14 +980,14 @@ class _CheckedInt(object):
_string = classmethod(_string)
class CheckedInt(type):
- def __new__(cls, name, min, max):
+ def __new__(cls, cppname, min, max):
# New class derives from _CheckedInt base with proper bounding
# parameters
- dict = { '_name' : name, '_min' : min, '_max' : max }
- return type.__new__(cls, name, (_CheckedInt, ), dict)
+ dict = { '_cppname' : cppname, '_min' : min, '_max' : max }
+ return type.__new__(cls, cppname, (_CheckedInt, ), dict)
class CheckedIntType(CheckedInt):
- def __new__(cls, name, size, unsigned):
+ def __new__(cls, cppname, size, unsigned):
dict = {}
if unsigned:
min = 0
@@ -1024,7 +996,7 @@ class CheckedIntType(CheckedInt):
min = -(2 ** (size - 1))
max = (2 ** (size - 1)) - 1
- return super(cls, CheckedIntType).__new__(cls, name, min, max)
+ return super(cls, CheckedIntType).__new__(cls, cppname, min, max)
Int = CheckedIntType('int', 32, False)
Unsigned = CheckedIntType('unsigned', 32, True)
@@ -1067,15 +1039,15 @@ def RangeSize(start, size):
class Range(type):
def __new__(cls, type):
- dict = { '_name' : 'Range<%s>' + type._name, '_type' : type }
- cname = 'Range_' + type.__name__
- return super(cls, Range).__new__(cls, cname, (_Range, ), dict)
+ dict = { '_cppname' : 'Range<%s>' % type._cppname, '_type' : type }
+ clsname = 'Range_' + type.__name__
+ return super(cls, Range).__new__(cls, clsname, (_Range, ), dict)
AddrRange = Range(Addr)
# Boolean parameter type.
class Bool(object):
- _name = 'bool'
+ _cppname = 'bool'
def _convert(value):
t = type(value)
if t == bool:
@@ -1103,7 +1075,7 @@ class Bool(object):
# String-valued parameter.
class String(object):
- _name = 'string'
+ _cppname = 'string'
# Constructor. Value must be Python string.
def _convert(cls,value):
@@ -1143,7 +1115,7 @@ class NextEthernetAddr(object):
self.addr = IncEthernetAddr(self.addr, inc)
class EthernetAddr(object):
- _name = 'EthAddr'
+ _cppname = 'EthAddr'
def _convert(cls, value):
if value == NextEthernetAddr:
@@ -1175,7 +1147,7 @@ class EthernetAddr(object):
# only one copy of a particular node
class NullSimObject(object):
__metaclass__ = Singleton
- _name = 'NULL'
+ _cppname = 'NULL'
def __call__(cls):
return cls
@@ -1278,21 +1250,6 @@ G = K*M
#####################################################################
-# Munge an arbitrary Python code string to get it to execute (mostly
-# dealing with indentation). Stolen from isa_parser.py... see
-# comments there for a more detailed description.
-#def fixPythonIndentation(s):
-# # get rid of blank lines first
-# s = re.sub(r'(?m)^\s*\n', '', s);
-# if (s != '' and re.match(r'[ \t]', s[0])):
-# s = 'if 1:\n' + s
-# return s
-
-# Hook to generate C++ parameter code.
-def gen_sim_code(file):
- for objname in sim_object_list:
- print >> file, eval("%s._sim_code()" % objname)
-
# The final hook to generate .ini files. Called from configuration
# script once config is built.
def instantiate(root):
diff --git a/sim/syscall_emul.hh b/sim/syscall_emul.hh
index 768bc3700..831708a21 100644
--- a/sim/syscall_emul.hh
+++ b/sim/syscall_emul.hh
@@ -410,8 +410,8 @@ mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
if (start == 0) {
// user didn't give an address... pick one from our "mmap region"
- start = p->mmap_base;
- p->mmap_base += RoundUp<Addr>(length, VMPageSize);
+ start = p->mmap_end;
+ p->mmap_end += RoundUp<Addr>(length, VMPageSize);
}
if (!(flags & OS::TGT_MAP_ANONYMOUS)) {
diff --git a/test/genini.py b/test/genini.py
index 73e7012f6..9c28ef361 100644..100755
--- a/test/genini.py
+++ b/test/genini.py
@@ -30,13 +30,14 @@ from os.path import join as joinpath, realpath
mypath = sys.path[0]
sys.path.append(joinpath(mypath, '..'))
-sys.path.append(joinpath(mypath, '../configs/kernel'))
sys.path.append(joinpath(mypath, '../util/pbs'))
sys.path.append(joinpath(mypath, '../sim/pyconfig'))
-from importer import mpy_exec, mpy_execfile, AddToPath
+from importer import AddToPath, LoadMpyFile
from m5config import *
+AddToPath('.')
+
try:
opts, args = getopt.getopt(sys.argv[1:], '-E:I:')
for opt,arg in opts:
@@ -55,8 +56,7 @@ except getopt.GetoptError:
sys.exit('Improper Usage')
for arg in args:
- AddToPath(os.path.dirname(arg))
- mpy_execfile(arg)
+ LoadMpyFile(arg)
if globals().has_key('root') and isinstance(root, type) \
and issubclass(root, Root):