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authorRon Dreslinski <rdreslin@umich.edu>2007-03-12 13:42:49 -0500
committerRon Dreslinski <rdreslin@umich.edu>2007-03-12 13:42:49 -0500
commitca8e95b480bfef4b97e54e22b0cbb8e8ec9513f4 (patch)
tree71e50126b6dd8a2a8b7e79c0af1e27c1d4af3821
parent885b4f26bb105bf9ad87c252b5bd24e83730fc3c (diff)
parent6415c47a5b196beb16ee56c8cb772dd3fd53b687 (diff)
downloadgem5-ca8e95b480bfef4b97e54e22b0cbb8e8ec9513f4.tar.xz
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/head --HG-- extra : convert_revision : 8651b2878853c5a6cb15f60ab92cf39d3bc30a07
-rw-r--r--src/cpu/memtest/memtest.cc2
-rw-r--r--src/mem/cache/cache_impl.hh14
2 files changed, 11 insertions, 5 deletions
diff --git a/src/cpu/memtest/memtest.cc b/src/cpu/memtest/memtest.cc
index 8b3e9a11e..607cf1066 100644
--- a/src/cpu/memtest/memtest.cc
+++ b/src/cpu/memtest/memtest.cc
@@ -369,7 +369,7 @@ MemTest::tick()
//This means we assume CPU does write forwarding to reads that alias something
//in the cpu store buffer.
if (outstandingAddrs.find(paddr) != outstandingAddrs.end()) {
- delete result;
+ delete [] result;
delete req;
return;
}
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 056f6033f..d8aab0e58 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -570,8 +570,10 @@ Cache<TagStore,Coherence>::access(PacketPtr &pkt)
}
}
while (!writebacks.empty()) {
- missQueue->doWriteback(writebacks.front());
+ PacketPtr wbPkt = writebacks.front();
+ missQueue->doWriteback(wbPkt);
writebacks.pop_front();
+ delete wbPkt;
}
DPRINTF(Cache, "%s %x %s\n", pkt->cmdString(), pkt->getAddr(),
@@ -721,8 +723,10 @@ Cache<TagStore,Coherence>::handleResponse(PacketPtr &pkt)
blk = handleFill(blk, (MSHR*)pkt->senderState,
new_state, writebacks, pkt);
while (!writebacks.empty()) {
- missQueue->doWriteback(writebacks.front());
- writebacks.pop_front();
+ PacketPtr wbPkt = writebacks.front();
+ missQueue->doWriteback(wbPkt);
+ writebacks.pop_front();
+ delete wbPkt;
}
}
missQueue->handleResponse(pkt, curTick + hitLatency);
@@ -1040,8 +1044,10 @@ return 0;
// There was a cache hit.
// Handle writebacks if needed
while (!writebacks.empty()){
- memSidePort->sendAtomic(writebacks.front());
+ PacketPtr wbPkt = writebacks.front();
+ memSidePort->sendAtomic(wbPkt);
writebacks.pop_front();
+ delete wbPkt;
}
hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;