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authorNilay Vaish <nilay@cs.wisc.edu>2014-09-01 16:55:45 -0500
committerNilay Vaish <nilay@cs.wisc.edu>2014-09-01 16:55:45 -0500
commitcee8faaad066cda6710904b5190e7287ff9356af (patch)
tree26e2e80ef32a9d82cd6f740d39d15aa229620e5a
parentb1d3873ec52692b0442666718da4175379697bb2 (diff)
downloadgem5-cee8faaad066cda6710904b5190e7287ff9356af.tar.xz
ruby: slicc: change the way configurable members are specified
There are two changes this patch makes to the way configurable members of a state machine are specified in SLICC. The first change is that the data member declarations will need to be separated by a semi-colon instead of a comma. Secondly, the default value to be assigned would now use SLICC's assignment operator i.e. ':='.
-rw-r--r--src/mem/protocol/MESI_Three_Level-L0cache.sm12
-rw-r--r--src/mem/protocol/MESI_Three_Level-L1cache.sm11
-rw-r--r--src/mem/protocol/MESI_Two_Level-L1cache.sm20
-rw-r--r--src/mem/protocol/MESI_Two_Level-L2cache.sm8
-rw-r--r--src/mem/protocol/MESI_Two_Level-dir.sm8
-rw-r--r--src/mem/protocol/MESI_Two_Level-dma.sm4
-rw-r--r--src/mem/protocol/MI_example-cache.sm10
-rw-r--r--src/mem/protocol/MI_example-dir.sm6
-rw-r--r--src/mem/protocol/MI_example-dma.sm4
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-L1cache.sm14
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-L2cache.sm6
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-dir.sm6
-rw-r--r--src/mem/protocol/MOESI_CMP_directory-dma.sm6
-rw-r--r--src/mem/protocol/MOESI_CMP_token-L1cache.sm33
-rw-r--r--src/mem/protocol/MOESI_CMP_token-L2cache.sm10
-rw-r--r--src/mem/protocol/MOESI_CMP_token-dir.sm14
-rw-r--r--src/mem/protocol/MOESI_CMP_token-dma.sm4
-rw-r--r--src/mem/protocol/MOESI_hammer-cache.sm18
-rw-r--r--src/mem/protocol/MOESI_hammer-dir.sm12
-rw-r--r--src/mem/protocol/MOESI_hammer-dma.sm4
-rw-r--r--src/mem/protocol/Network_test-cache.sm4
-rw-r--r--src/mem/slicc/ast/FormalParamAST.py1
-rw-r--r--src/mem/slicc/ast/ObjDeclAST.py3
-rw-r--r--src/mem/slicc/ast/StallAndWaitStatementAST.py2
-rw-r--r--src/mem/slicc/parser.py30
-rw-r--r--src/mem/slicc/symbols/StateMachine.py35
26 files changed, 151 insertions, 134 deletions
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm
index 5e49d5b13..f707ba963 100644
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -27,12 +27,12 @@
*/
machine(L0Cache, "MESI Directory L0 Cache")
- : Sequencer * sequencer,
- CacheMemory * Icache,
- CacheMemory * Dcache,
- Cycles request_latency = 2,
- Cycles response_latency = 2,
- bool send_evictions,
+ : Sequencer * sequencer;
+ CacheMemory * Icache;
+ CacheMemory * Dcache;
+ Cycles request_latency := 2;
+ Cycles response_latency := 2;
+ bool send_evictions;
{
// NODE L0 CACHE
// From this node's L0 cache to the network
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm
index 43daa0463..170599a51 100644
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm
@@ -27,11 +27,11 @@
*/
machine(L1Cache, "MESI Directory L1 Cache CMP")
- : CacheMemory * cache,
- int l2_select_num_bits,
- Cycles l1_request_latency = 2,
- Cycles l1_response_latency = 2,
- Cycles to_l2_latency = 1,
+ : CacheMemory * cache;
+ int l2_select_num_bits;
+ Cycles l1_request_latency := 2;
+ Cycles l1_response_latency := 2;
+ Cycles to_l2_latency := 1;
{
// From this node's L1 cache TO the network
// a local L1 -> this L2 bank, currently ordered with directory forwarded requests
@@ -40,7 +40,6 @@ machine(L1Cache, "MESI Directory L1 Cache CMP")
MessageBuffer responseToL2, network="To", virtual_network="1", ordered="false", vnet_type="response";
MessageBuffer unblockToL2, network="To", virtual_network="2", ordered="false", vnet_type="unblock";
-
// To this node's L1 cache FROM the network
// a L2 bank -> this L1
MessageBuffer requestFromL2, network="From", virtual_network="0", ordered="false", vnet_type="request";
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index a202a8deb..96c1699b7 100644
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -27,16 +27,16 @@
*/
machine(L1Cache, "MESI Directory L1 Cache CMP")
- : Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- Prefetcher * prefetcher = 'NULL',
- int l2_select_num_bits,
- Cycles l1_request_latency = 2,
- Cycles l1_response_latency = 2,
- Cycles to_l2_latency = 1,
- bool send_evictions,
- bool enable_prefetch = "False"
+ : Sequencer * sequencer;
+ CacheMemory * L1Icache;
+ CacheMemory * L1Dcache;
+ Prefetcher * prefetcher;
+ int l2_select_num_bits;
+ Cycles l1_request_latency := 2;
+ Cycles l1_response_latency := 2;
+ Cycles to_l2_latency := 1;
+ bool send_evictions;
+ bool enable_prefetch := "False";
{
// NODE L1 CACHE
// From this node's L1 cache TO the network
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm
index f69eaa9a9..f191ddccb 100644
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm
@@ -32,10 +32,10 @@
*/
machine(L2Cache, "MESI Directory L2 Cache CMP")
- : CacheMemory * L2cache,
- Cycles l2_request_latency = 2,
- Cycles l2_response_latency = 2,
- Cycles to_l1_latency = 1
+ : CacheMemory * L2cache;
+ Cycles l2_request_latency := 2;
+ Cycles l2_response_latency := 2;
+ Cycles to_l1_latency := 1;
{
// L2 BANK QUEUES
// From local bank of L2 cache TO the network
diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm
index bfd4fc475..679f2dee7 100644
--- a/src/mem/protocol/MESI_Two_Level-dir.sm
+++ b/src/mem/protocol/MESI_Two_Level-dir.sm
@@ -35,10 +35,10 @@
machine(Directory, "MESI Two Level directory protocol")
- : DirectoryMemory * directory,
- MemoryControl * memBuffer,
- Cycles to_mem_ctrl_latency = 1,
- Cycles directory_latency = 6,
+ : DirectoryMemory * directory;
+ MemoryControl * memBuffer;
+ Cycles to_mem_ctrl_latency := 1;
+ Cycles directory_latency := 6;
{
MessageBuffer requestToDir, network="From", virtual_network="0",
ordered="false", vnet_type="request";
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm
index b9bb68cbd..80c70c80a 100644
--- a/src/mem/protocol/MESI_Two_Level-dma.sm
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm
@@ -28,8 +28,8 @@
*/
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 6;
{
MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response";
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index 561de2397..9b0c18bc8 100644
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -28,11 +28,11 @@
*/
machine(L1Cache, "MI Example L1 Cache")
-: Sequencer * sequencer,
- CacheMemory * cacheMemory,
- Cycles cache_response_latency = 12,
- Cycles issue_latency = 2,
- bool send_evictions
+: Sequencer * sequencer;
+ CacheMemory * cacheMemory;
+ Cycles cache_response_latency := 12;
+ Cycles issue_latency := 2;
+ bool send_evictions;
{
// NETWORK BUFFERS
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
index 87ed57919..f0d85cba8 100644
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -28,9 +28,9 @@
*/
machine(Directory, "Directory protocol")
-: DirectoryMemory * directory,
- MemoryControl * memBuffer,
- Cycles directory_latency = 12
+: DirectoryMemory * directory;
+ MemoryControl * memBuffer;
+ Cycles directory_latency := 12;
{
MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false", vnet_type="forward";
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm
index c9da54f85..14b8c4e4a 100644
--- a/src/mem/protocol/MI_example-dma.sm
+++ b/src/mem/protocol/MI_example-dma.sm
@@ -28,8 +28,8 @@
*/
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 6;
{
MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response";
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index bf935ab65..fb74a67e4 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -27,13 +27,13 @@
*/
machine(L1Cache, "Directory protocol")
- : Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- int l2_select_num_bits,
- Cycles request_latency = 2,
- Cycles use_timeout_latency = 50,
- bool send_evictions
+ : Sequencer * sequencer;
+ CacheMemory * L1Icache;
+ CacheMemory * L1Dcache;
+ int l2_select_num_bits;
+ Cycles request_latency := 2;
+ Cycles use_timeout_latency := 50;
+ bool send_evictions;
{
// NODE L1 CACHE
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
index 5974321b7..7d81f4164 100644
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -27,9 +27,9 @@
*/
machine(L2Cache, "Token protocol")
-: CacheMemory * L2cache,
- Cycles response_latency = 2,
- Cycles request_latency = 2
+: CacheMemory * L2cache;
+ Cycles response_latency := 2;
+ Cycles request_latency := 2;
{
// L2 BANK QUEUES
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
index 336bb80ee..b403bc91c 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -27,9 +27,9 @@
*/
machine(Directory, "Directory protocol")
-: DirectoryMemory * directory,
- MemoryControl * memBuffer,
- Cycles directory_latency = 6
+: DirectoryMemory * directory;
+ MemoryControl * memBuffer;
+ Cycles directory_latency := 6;
{
// ** IN QUEUES **
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
index fd1ab6f6c..1a8b3aea9 100644
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -28,9 +28,9 @@
*/
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 14,
- Cycles response_latency = 14
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 14;
+ Cycles response_latency := 14;
{
MessageBuffer responseFromDir, network="From", virtual_network="2", ordered="false", vnet_type="response";
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index 238689efa..b1197780f 100644
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -32,22 +32,22 @@
*/
machine(L1Cache, "Token protocol")
- : Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- int l2_select_num_bits,
- int N_tokens,
-
- Cycles l1_request_latency = 2,
- Cycles l1_response_latency = 2,
- int retry_threshold = 1,
- Cycles fixed_timeout_latency = 100,
- Cycles reissue_wakeup_latency = 10,
- Cycles use_timeout_latency = 50,
-
- bool dynamic_timeout_enabled = true,
- bool no_mig_atomic = true,
- bool send_evictions
+ : Sequencer * sequencer;
+ CacheMemory * L1Icache;
+ CacheMemory * L1Dcache;
+ int l2_select_num_bits;
+ int N_tokens;
+
+ Cycles l1_request_latency := 2;
+ Cycles l1_response_latency := 2;
+ int retry_threshold := 1;
+ Cycles fixed_timeout_latency := 100;
+ Cycles reissue_wakeup_latency := 10;
+ Cycles use_timeout_latency := 50;
+
+ bool dynamic_timeout_enabled := "True";
+ bool no_mig_atomic := "True";
+ bool send_evictions;
{
// From this node's L1 cache TO the network
@@ -206,7 +206,6 @@ machine(L1Cache, "Token protocol")
Cycles averageLatencyEstimate() {
DPRINTF(RubySlicc, "%d\n",
(averageLatencyCounter >> averageLatencyHysteresis));
- //profile_average_latency_estimate( (averageLatencyCounter >> averageLatencyHysteresis) );
return averageLatencyCounter >> averageLatencyHysteresis;
}
diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
index f0fa8227d..f8bd01695 100644
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
@@ -27,11 +27,11 @@
*/
machine(L2Cache, "Token protocol")
- : CacheMemory * L2cache,
- int N_tokens,
- Cycles l2_request_latency = 5,
- Cycles l2_response_latency = 5,
- bool filtering_enabled = true
+ : CacheMemory * L2cache;
+ int N_tokens;
+ Cycles l2_request_latency := 5;
+ Cycles l2_response_latency := 5;
+ bool filtering_enabled := "True";
{
// L2 BANK QUEUES
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
index 4354d7c4c..5cb29fcc2 100644
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -27,13 +27,13 @@
*/
machine(Directory, "Token protocol")
- : DirectoryMemory * directory,
- MemoryControl * memBuffer,
- int l2_select_num_bits,
- Cycles directory_latency = 5,
- bool distributed_persistent = true,
- Cycles fixed_timeout_latency = 100,
- Cycles reissue_wakeup_latency = 10
+ : DirectoryMemory * directory;
+ MemoryControl * memBuffer;
+ int l2_select_num_bits;
+ Cycles directory_latency := 5;
+ bool distributed_persistent := "True";
+ Cycles fixed_timeout_latency := 100;
+ Cycles reissue_wakeup_latency := 10;
{
MessageBuffer dmaResponseFromDir, network="To", virtual_network="5", ordered="true", vnet_type="response";
diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm
index 812017acd..441a001fc 100644
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm
@@ -28,8 +28,8 @@
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 6;
{
MessageBuffer responseFromDir, network="From", virtual_network="5", ordered="true", vnet_type="response";
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index 514488115..7c150bda0 100644
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -34,15 +34,15 @@
*/
machine({L1Cache, L2Cache}, "AMD Hammer-like protocol")
-: Sequencer * sequencer,
- CacheMemory * L1Icache,
- CacheMemory * L1Dcache,
- CacheMemory * L2cache,
- Cycles cache_response_latency = 10,
- Cycles issue_latency = 2,
- Cycles l2_cache_hit_latency = 10,
- bool no_mig_atomic = true,
- bool send_evictions
+: Sequencer * sequencer;
+ CacheMemory * L1Icache;
+ CacheMemory * L1Dcache;
+ CacheMemory * L2cache;
+ Cycles cache_response_latency := 10;
+ Cycles issue_latency := 2;
+ Cycles l2_cache_hit_latency := 10;
+ bool no_mig_atomic := "True";
+ bool send_evictions;
{
// NETWORK BUFFERS
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index 58e4d7346..4e2f846e2 100644
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -34,12 +34,12 @@
*/
machine(Directory, "AMD Hammer-like protocol")
-: DirectoryMemory * directory,
- CacheMemory * probeFilter,
- MemoryControl * memBuffer,
- Cycles memory_controller_latency = 2,
- bool probe_filter_enabled = false,
- bool full_bit_dir_enabled = false
+: DirectoryMemory * directory;
+ CacheMemory * probeFilter;
+ MemoryControl * memBuffer;
+ Cycles memory_controller_latency := 2;
+ bool probe_filter_enabled := "False";
+ bool full_bit_dir_enabled := "False";
{
MessageBuffer forwardFromDir, network="To", virtual_network="3", ordered="false", vnet_type="forward";
diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm
index 1d0f67881..e4d26bb48 100644
--- a/src/mem/protocol/MOESI_hammer-dma.sm
+++ b/src/mem/protocol/MOESI_hammer-dma.sm
@@ -28,8 +28,8 @@
machine(DMA, "DMA Controller")
-: DMASequencer * dma_sequencer,
- Cycles request_latency = 6
+: DMASequencer * dma_sequencer;
+ Cycles request_latency := 6;
{
MessageBuffer responseFromDir, network="From", virtual_network="1", ordered="true", vnet_type="response";
diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm
index 885bbacbe..f69aecd93 100644
--- a/src/mem/protocol/Network_test-cache.sm
+++ b/src/mem/protocol/Network_test-cache.sm
@@ -32,8 +32,8 @@
machine(L1Cache, "Network_test L1 Cache")
-: Sequencer * sequencer,
- Cycles issue_latency = 2
+: Sequencer * sequencer;
+ Cycles issue_latency := 2;
{
// NETWORK BUFFERS
diff --git a/src/mem/slicc/ast/FormalParamAST.py b/src/mem/slicc/ast/FormalParamAST.py
index 6ed5bca0a..ce73304f1 100644
--- a/src/mem/slicc/ast/FormalParamAST.py
+++ b/src/mem/slicc/ast/FormalParamAST.py
@@ -51,6 +51,7 @@ class FormalParamAST(AST):
v = Var(self.symtab, self.ident, self.location, type, param,
self.pairs)
self.symtab.newSymbol(v)
+
if self.pointer or str(type) == "TBE" or (
"interface" in type and (
type["interface"] == "AbstractCacheEntry" or
diff --git a/src/mem/slicc/ast/ObjDeclAST.py b/src/mem/slicc/ast/ObjDeclAST.py
index ffd71bbb1..92ff15d52 100644
--- a/src/mem/slicc/ast/ObjDeclAST.py
+++ b/src/mem/slicc/ast/ObjDeclAST.py
@@ -29,12 +29,13 @@ from slicc.ast.DeclAST import DeclAST
from slicc.symbols import Var
class ObjDeclAST(DeclAST):
- def __init__(self, slicc, type_ast, ident, pairs, rvalue):
+ def __init__(self, slicc, type_ast, ident, pairs, rvalue, pointer):
super(ObjDeclAST, self).__init__(slicc, pairs)
self.type_ast = type_ast
self.ident = ident
self.rvalue = rvalue
+ self.pointer = pointer
def __repr__(self):
return "[ObjDecl: %r]" % self.ident
diff --git a/src/mem/slicc/ast/StallAndWaitStatementAST.py b/src/mem/slicc/ast/StallAndWaitStatementAST.py
index b87726c6a..08b0e340c 100644
--- a/src/mem/slicc/ast/StallAndWaitStatementAST.py
+++ b/src/mem/slicc/ast/StallAndWaitStatementAST.py
@@ -35,7 +35,7 @@ class StallAndWaitStatementAST(StatementAST):
self.address = address
def __repr__(self):
- return "[StallAndWaitStatementAst: %r]" % self.variable
+ return "[StallAndWaitStatementAst: %r]" % self.in_port
def generate(self, code, return_type):
self.in_port.assertType("InPort")
diff --git a/src/mem/slicc/parser.py b/src/mem/slicc/parser.py
index 04ba4640c..10dd99ece 100644
--- a/src/mem/slicc/parser.py
+++ b/src/mem/slicc/parser.py
@@ -258,11 +258,11 @@ class SLICC(Grammar):
p[0] = self.parse_file(filename)
def p_decl__machine0(self, p):
- "decl : MACHINE '(' idents ')' ':' params '{' decls '}'"
+ "decl : MACHINE '(' idents ')' ':' obj_decls '{' decls '}'"
p[0] = ast.MachineAST(self, p[3], [], p[7], p[9])
def p_decl__machine1(self, p):
- "decl : MACHINE '(' idents pairs ')' ':' params '{' decls '}'"
+ "decl : MACHINE '(' idents pairs ')' ':' obj_decls '{' decls '}'"
p[0] = ast.MachineAST(self, p[3], p[4], p[7], p[9])
def p_decl__action(self, p):
@@ -319,6 +319,14 @@ class SLICC(Grammar):
p[0] = ast.StateDeclAST(self, p[3], p[4], p[7])
# Type fields
+ def p_obj_decls__list(self, p):
+ "obj_decls : obj_decl obj_decls"
+ p[0] = [ p[1] ] + p[2]
+
+ def p_obj_decls__empty(self, p):
+ "obj_decls : empty"
+ p[0] = []
+
def p_type_members__list(self, p):
"type_members : type_member type_members"
p[0] = [ p[1] ] + p[2]
@@ -340,19 +348,21 @@ class SLICC(Grammar):
def p_obj_decl__0(self, p):
"obj_decl : type ident pairs SEMI"
- p[0] = ast.ObjDeclAST(self, p[1], p[2], p[3], None)
+ p[0] = ast.ObjDeclAST(self, p[1], p[2], p[3], None, False)
def p_obj_decl__1(self, p):
"obj_decl : type STAR ident pairs SEMI"
- p[0] = ast.ObjDeclAST(self, p[1], p[3], p[4], None)
+ p[0] = ast.ObjDeclAST(self, p[1], p[3], p[4], None, True)
def p_obj_decl__2(self, p):
"obj_decl : type ident ASSIGN expr SEMI"
- p[0] = ast.ObjDeclAST(self, p[1], p[2], ast.PairListAST(self), p[4])
+ p[0] = ast.ObjDeclAST(self, p[1], p[2], ast.PairListAST(self), p[4],
+ False)
def p_obj_decl__3(self, p):
"obj_decl : type STAR ident ASSIGN expr SEMI"
- p[0] = ast.ObjDeclAST(self, p[1], p[3], ast.PairListAST(self), p[5])
+ p[0] = ast.ObjDeclAST(self, p[1], p[3], ast.PairListAST(self), p[5],
+ True)
# Function definition and declaration
def p_decl__func_decl(self, p):
@@ -426,19 +436,19 @@ class SLICC(Grammar):
p[0] = ast.FormalParamAST(self, p[1], p[3], None, True)
def p_param__pointer_default(self, p):
- "param : type STAR ident '=' STRING"
+ "param : type STAR ident ASSIGN STRING"
p[0] = ast.FormalParamAST(self, p[1], p[3], p[5], True)
def p_param__default_number(self, p):
- "param : type ident '=' NUMBER"
+ "param : type ident ASSIGN NUMBER"
p[0] = ast.FormalParamAST(self, p[1], p[2], p[4])
def p_param__default_bool(self, p):
- "param : type ident '=' LIT_BOOL"
+ "param : type ident ASSIGN LIT_BOOL"
p[0] = ast.FormalParamAST(self, p[1], p[2], p[4])
def p_param__default_string(self, p):
- "param : type ident '=' STRING"
+ "param : type ident ASSIGN STRING"
p[0] = ast.FormalParamAST(self, p[1], p[2], p[4])
# Type
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 2cda3a49d..71fcc053f 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -56,12 +56,14 @@ class StateMachine(Symbol):
for param in config_parameters:
if param.pointer:
- var = Var(symtab, param.name, location, param.type_ast.type,
- "(*m_%s_ptr)" % param.name, {}, self)
+ var = Var(symtab, param.ident, location, param.type_ast.type,
+ "(*m_%s_ptr)" % param.ident, {}, self)
else:
- var = Var(symtab, param.name, location, param.type_ast.type,
- "m_%s" % param.name, {}, self)
- self.symtab.registerSym(param.name, var)
+ var = Var(symtab, param.ident, location, param.type_ast.type,
+ "m_%s" % param.ident, {}, self)
+
+ self.symtab.registerSym(param.ident, var)
+
if str(param.type_ast.type) == "Prefetcher":
self.prefetchers.append(var)
@@ -178,8 +180,10 @@ class StateMachine(Symbol):
def printControllerPython(self, path):
code = self.symtab.codeFormatter()
ident = self.ident
+
py_ident = "%s_Controller" % ident
c_ident = "%s_Controller" % self.ident
+
code('''
from m5.params import *
from m5.SimObject import SimObject
@@ -192,11 +196,14 @@ class $py_ident(RubyController):
code.indent()
for param in self.config_parameters:
dflt_str = ''
- if param.default is not None:
- dflt_str = str(param.default) + ', '
+
+ if param.rvalue is not None:
+ dflt_str = str(param.rvalue.inline()) + ', '
+
if python_class_map.has_key(param.type_ast.type.c_ident):
python_type = python_class_map[param.type_ast.type.c_ident]
- code('${{param.name}} = Param.${{python_type}}(${dflt_str}"")')
+ code('${{param.ident}} = Param.${{python_type}}(${dflt_str}"")')
+
else:
self.error("Unknown c++ to python class conversion for c++ " \
"type: '%s'. Please update the python_class_map " \
@@ -480,11 +487,11 @@ $c_ident::$c_ident(const Params *p)
#
for param in self.config_parameters:
if param.pointer:
- code('m_${{param.name}}_ptr = p->${{param.name}};')
+ code('m_${{param.ident}}_ptr = p->${{param.ident}};')
else:
- code('m_${{param.name}} = p->${{param.name}};')
- if re.compile("sequencer").search(param.name):
- code('m_${{param.name}}_ptr->setController(this);')
+ code('m_${{param.ident}} = p->${{param.ident}};')
+ if re.compile("sequencer").search(param.ident):
+ code('m_${{param.ident}}_ptr->setController(this);')
for var in self.objects:
if var.ident.find("mandatoryQueue") >= 0:
@@ -679,9 +686,9 @@ $vid->setDescription("[Version " + to_string(m_version) + ", ${ident}, name=${{v
seq_ident = "NULL"
for param in self.config_parameters:
- if param.name == "sequencer":
+ if param.ident == "sequencer":
assert(param.pointer)
- seq_ident = "m_%s_ptr" % param.name
+ seq_ident = "m_%s_ptr" % param.ident
code('''