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authorRon Dreslinski <rdreslin@umich.edu>2006-08-15 14:28:22 -0400
committerRon Dreslinski <rdreslin@umich.edu>2006-08-15 14:28:22 -0400
commitd0d0d7b636c20ad0fafec885c246711ec4218fff (patch)
tree59305895276c854e0055796c3ce4b134761ae5e3
parent07488510713a1df61f6cefced7677047cfc0ef66 (diff)
parentdc375e42bc739e8869a75993a93ed8afc3f294cc (diff)
downloadgem5-d0d0d7b636c20ad0fafec885c246711ec4218fff.tar.xz
Merge zizzer:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem --HG-- extra : convert_revision : 8a8d7fe59610806015c8242a2f5eacf9afce7164
-rw-r--r--src/mem/cache/base_cache.cc10
-rw-r--r--src/mem/cache/base_cache.hh2
-rw-r--r--src/mem/cache/cache_impl.hh2
3 files changed, 13 insertions, 1 deletions
diff --git a/src/mem/cache/base_cache.cc b/src/mem/cache/base_cache.cc
index 451da28e8..9b1034577 100644
--- a/src/mem/cache/base_cache.cc
+++ b/src/mem/cache/base_cache.cc
@@ -71,6 +71,11 @@ BaseCache::CachePort::deviceBlockSize()
bool
BaseCache::CachePort::recvTiming(Packet *pkt)
{
+ if (blocked)
+ {
+ mustSendRetry = true;
+ return false;
+ }
return cache->doTimingAccess(pkt, this, isCpuSide);
}
@@ -95,6 +100,11 @@ BaseCache::CachePort::setBlocked()
void
BaseCache::CachePort::clearBlocked()
{
+ if (mustSendRetry)
+ {
+ mustSendRetry = false;
+ sendRetry();
+ }
blocked = false;
}
diff --git a/src/mem/cache/base_cache.hh b/src/mem/cache/base_cache.hh
index 7f0cb56f2..9fb790cee 100644
--- a/src/mem/cache/base_cache.hh
+++ b/src/mem/cache/base_cache.hh
@@ -105,6 +105,8 @@ class BaseCache : public MemObject
bool blocked;
+ bool mustSendRetry;
+
bool isCpuSide;
};
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 56e7a4d58..b215960c4 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -69,7 +69,7 @@ doTimingAccess(Packet *pkt, CachePort *cachePort, bool isCpuSide)
else
snoop(pkt);
}
- return true; //Deal with blocking....
+ return true;
}
template<class TagStore, class Buffering, class Coherence>