finally runs dhrystone

Change-Id: I7466a825f8726682622d237460311a1c4b23b8ad

6 files changed, 14 insertions, 15 deletions

diff --git a/src/cpu/o3/inst_queue_impl.hh b/src/cpu/o3/inst_queue_impl.hh
index 0a6d309fe..a30bf7f5f 100644
--- a/src/cpu/o3/inst_queue_impl.hh
+++ b/src/cpu/o3/inst_queue_impl.hh
@@ -1182,8 +1182,12 @@ InstructionQueue<Impl>::getDeferredMemInstToExecute()
         // 2. virtual fence ahead
         // 3. not ready to expose and gets a TLB miss
         // for both (2, 3) we need to restart the translation
+
+      DPRINTF(IQ, "sn:%lli onlyWaitForFence = %d, fenceDelay = %d\n", (*it)->seqNum, (*it)->onlyWaitForFence(), (*it)->fenceDelay() );
+
         if ( (*it)->translationCompleted() 
                 || ((*it)->onlyWaitForFence() && !(*it)->fenceDelay())
+                || ((*it)->onlyWaitForExpose() && (*it)->readyToExpose())
                 || (*it)->isSquashed()) {
             DynInstPtr mem_inst = std::move(*it);
             mem_inst->onlyWaitForFence(false);
diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh
index ebc963d5b..80445e261 100644
--- a/src/cpu/o3/lsq_unit_impl.hh
+++ b/src/cpu/o3/lsq_unit_impl.hh
@@ -128,6 +128,8 @@ LSQUnit<Impl>::completeDataAccess(PacketPtr pkt)
         DPRINTF(LSQUnit, "spec load miss for inst [sn:%lli], fence it.\n",
                 inst->seqNum);
         inst->fenceDelay(true);
+    } else {
+        DPRINTF(LSQUnit, "spec load hit for inst [sn:%lli].\n");
     }
 
     assert(!cpu->switchedOut());
@@ -918,6 +920,7 @@ LSQUnit<Impl>::updateVisibleState()
     //iterate all the loads and update its fencedelay state accordingly
     while (load_idx != loadTail && loadQueue[load_idx]){
         DynInstPtr inst = loadQueue[load_idx];
+        DPRINTF(LSQUnit, "update visible state for inst [sn:%lli].\n", inst->seqNum);
 
         if (!loadInExec){
 
@@ -981,6 +984,7 @@ LSQUnit<Impl>::updateVisibleState()
                     assert(0);
                     //--loadsToVLD;
                   }
+                  DPRINTF(LSQUnit, "inst [sn:%lli] not ready to expose.\n", inst->seqNum);
                   inst->readyToExpose(false);
                 } else {
                   /* set taint for dst registers */
@@ -1370,7 +1374,10 @@ LSQUnit<Impl>::writeback(const DynInstPtr &inst, PacketPtr pkt)
 
     if (inst->fenceDelay()) {
         DPRINTF(LSQUnit, "To write back a fence delayed spec load [sn:%lli].\n", inst->seqNum);
+        assert(pkt->isSpec());
         inst->onlyWaitForFence(true);
+        inst->translationStarted(false);
+        inst->translationCompleted(false);
         iewStage->instQueue.deferMemInst(inst);
     } else if (!inst->isExecuted()) {
         inst->setExecuted();
diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh
index b729a9d00..32cfe04a1 100644
--- a/src/cpu/o3/rob_impl.hh
+++ b/src/cpu/o3/rob_impl.hh
@@ -434,6 +434,7 @@ ROB<Impl>::updateVisibleState()
 
         while (inst_it != tail_inst_it) {
             DynInstPtr inst = *inst_it++;
+            DPRINTF(ROB, "updating rob visible state for [sn:%lli]\n", inst->seqNum);
 
             assert(inst!=0);
 
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
index 8496fda61..e925057db 100644
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -1227,7 +1227,7 @@ machine(MachineType:L1Cache, "MESI Directory L1 Cache CMP")
     k_popMandatoryQueue;
   }
 
-  transition({NP,I}, SpecLoad, IX) {
+  transition({NP,I}, SpecLoad) {
     h_spec_load_miss;
     k_popMandatoryQueue;
   }
diff --git a/src/mem/ruby/system/Sequencer.cc b/src/mem/ruby/system/Sequencer.cc
index 090030f08..a0d3cab1b 100644
--- a/src/mem/ruby/system/Sequencer.cc
+++ b/src/mem/ruby/system/Sequencer.cc
@@ -237,16 +237,6 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
             RequestTable::iterator i = r.first;
             i->second = new SequencerRequest(pkt, request_type, curCycle());
             m_outstanding_count++;
-        } else if (request_type == RubyRequestType_SPEC_LD) {
-            auto i = m_readRequestTable.find(line_addr);
-            if (i->second->m_type == RubyRequestType_SPEC_LD) {
-                DPRINTFR(SpecBuffer, "%10s Merging (idx=%d-%d, addr=%#x) with %d\n", curTick(), pkt->reqIdx, pkt->isFirst()? 0 : 1, printAddress(pkt->getAddr()), i->second->pkt->reqIdx);
-                i->second->dependentSpecRequests.push_back(pkt);
-                return RequestStatus_Merged;
-            } else {
-                m_load_waiting_on_load++;
-                return RequestStatus_Aliased;
-            }
         } else {
             // There is an outstanding read request for the cache line
             m_load_waiting_on_load++;
@@ -653,9 +643,7 @@ Sequencer::makeRequest(PacketPtr pkt)
     }
 
     RequestStatus status = insertRequest(pkt, primary_type);
-    if (status == RequestStatus_Merged) {
-        return RequestStatus_Issued;
-    } else if (status != RequestStatus_Ready) {
+    if (status != RequestStatus_Ready) {
         return status;
     }
 
diff --git a/src/mem/ruby/system/Sequencer.hh b/src/mem/ruby/system/Sequencer.hh
index 8e1f08a48..d9ed62320 100644
--- a/src/mem/ruby/system/Sequencer.hh
+++ b/src/mem/ruby/system/Sequencer.hh
@@ -46,7 +46,6 @@ struct SequencerRequest
     PacketPtr pkt;
     RubyRequestType m_type;
     Cycles issue_time;
-    std::vector<PacketPtr> dependentSpecRequests;
 
     SequencerRequest(PacketPtr _pkt, RubyRequestType _m_type,
                      Cycles _issue_time)