Merge with head.

--HG--
extra : convert_revision : c4215e516c6d82ad466db898ffeefa0233ca110e

66 files changed, 1278 insertions, 1368 deletions

diff --git a/SConstruct b/SConstruct
index c87ac50f5..062df47d6 100644
--- a/SConstruct
+++ b/SConstruct
@@ -68,6 +68,8 @@ import os
 
 from os.path import isdir, join as joinpath
 
+import SCons
+
 # Check for recent-enough Python and SCons versions.  If your system's
 # default installation of Python is not recent enough, you can use a
 # non-default installation of the Python interpreter by either (1)
@@ -344,6 +346,7 @@ try:
             env.Append(CFLAGS='-arch x86_64')
             env.Append(LINKFLAGS='-arch x86_64')
             env.Append(ASFLAGS='-arch x86_64')
+            env['OSX64bit'] = True
 except:
     pass
 
@@ -472,14 +475,19 @@ all_isa_list.sort()
 all_cpu_list.sort()
 default_cpus.sort()
 
-def ExtraPathValidator(key, val, env):
+def PathListMakeAbsolute(val):
+    if not val:
+        return val
+    f = lambda p: os.path.abspath(os.path.expanduser(p))
+    return ':'.join(map(f, val.split(':')))
+
+def PathListAllExist(key, val, env):
     if not val:
         return
     paths = val.split(':')
     for path in paths:
-        path = os.path.expanduser(path)
         if not isdir(path):
-            raise AttributeError, "Invalid path: '%s'" % path
+            raise SCons.Errors.UserError("Path does not exist: '%s'" % path)
 
 sticky_opts.AddOptions(
     EnumOption('TARGET_ISA', 'Target ISA', 'alpha', all_isa_list),
@@ -509,7 +517,7 @@ sticky_opts.AddOptions(
      'Override the default PYTHONHOME for this system (use with caution)',
      '%s:%s' % (sys.prefix, sys.exec_prefix)),
     ('EXTRAS', 'Add Extra directories to the compilation', '',
-     ExtraPathValidator)
+     PathListAllExist, PathListMakeAbsolute)
     )
 
 nonsticky_opts.AddOptions(
diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index a2be27af4..37b9f5551 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -52,7 +52,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None):
     self.iobus = Bus(bus_id=0)
     self.membus = Bus(bus_id=1)
     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
-    self.physmem = PhysicalMemory(range = AddrRange('64MB'))
+    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
     self.bridge.side_a = self.iobus.port
     self.bridge.side_b = self.membus.port
     self.physmem.port = self.membus.port
@@ -189,7 +189,7 @@ def makeDualRoot(testSystem, driveSystem, dumpfile):
 
     return self
 
-def setMipsOptions(TestCPUClass.CoreParams)
+def setMipsOptions(TestCPUClass):
         #CP0 Configuration
         TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
         TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
diff --git a/ext/libelf/SConscript b/ext/libelf/SConscript
index 99c5a4f99..3d35b0c07 100644
--- a/ext/libelf/SConscript
+++ b/ext/libelf/SConscript
@@ -88,11 +88,16 @@ ElfFile('libelf_fsize.c')
 ElfFile('libelf_msize.c')
 
 m4env = Environment(ENV=os.environ)
+
 if env.get('CC'):
     m4env['CC'] = env['CC']
 if env.get('CXX'):
     m4env['CXX'] = env['CXX']
 
+if env.get('OSX64bit'):
+    m4env.Append(CFLAGS='-arch x86_64')
+    m4env.Append(LINKFLAGS='-arch x86_64')
+
 # If we have gm4 use it
 if m4env.Detect('gm4'):
     m4env['M4'] = 'gm4'
diff --git a/src/SConscript b/src/SConscript
index e66a725d3..8e6e1b45e 100644
--- a/src/SConscript
+++ b/src/SConscript
@@ -198,12 +198,12 @@ for root, dirs, files in os.walk(srcdir, topdown=True):
 extra_string = env['EXTRAS']
 if extra_string and extra_string != '' and not extra_string.isspace():
     for extra in extra_string.split(':'):
-        extra = os.path.expanduser(extra)
-        extra = os.path.normpath(extra)
+        print 'Adding', extra, 'to source directory list'
         env.Append(CPPPATH=[Dir(extra)])
         for root, dirs, files in os.walk(extra, topdown=True):
             if 'SConscript' in files:
                 subdir = root[len(os.path.dirname(extra))+1:]
+                print '  Found SConscript in', subdir
                 build_dir = joinpath(env['BUILDDIR'], subdir)
                 SConscript(joinpath(root, 'SConscript'), build_dir=build_dir)
 
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index 6ac174e48..ce8847365 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -27,6 +27,7 @@
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
 # Authors: Jaidev Patwardhan
+#          Korey Sewell
 
 from m5.SimObject import SimObject
 from m5.params import *
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 1b746d8b0..8be445c99 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -1,6 +1,6 @@
 # -*- mode:python -*-
 
-# Copyright (c) 2007 MIPS Technologies, Inc.
+# Copyright (c) 2004-2006 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/SConsopts b/src/arch/mips/SConsopts
index 97ab703a9..d19df2f5e 100644
--- a/src/arch/mips/SConsopts
+++ b/src/arch/mips/SConsopts
@@ -1,4 +1,6 @@
-# Copyright (c) 2007 MIPS Technologies, Inc.
+# -*- mode:python -*-
+
+# Copyright (c) 2004-2005 The Regents of The University of Michigan
 # All rights reserved.
 #
 # Redistribution and use in source and binary forms, with or without
@@ -24,7 +26,7 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-# Authors: Jaidev Patwardhan
+# Authors: Nathan Binkert
 
 Import('*')
 
diff --git a/src/arch/mips/bare_iron/system.cc b/src/arch/mips/bare_iron/system.cc
index 045db0dee..765dec4b0 100755
--- a/src/arch/mips/bare_iron/system.cc
+++ b/src/arch/mips/bare_iron/system.cc
@@ -1,38 +1,31 @@
 /*
- * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
  *
- * This software is part of the M5 simulator.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
  *
- * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * TO THESE TERMS AND CONDITIONS.
- *
- * Permission is granted to use, copy, create derivative works and
- * distribute this software and such derivative works for any purpose,
- * so long as (1) the copyright notice above, this grant of permission,
- * and the disclaimer below appear in all copies and derivative works
- * made, (2) the copyright notice above is augmented as appropriate to
- * reflect the addition of any new copyrightable work in a derivative
- * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
- * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
- * advertising or publicity pertaining to the use or distribution of
- * this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
- * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
- * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
- * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
- * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
- * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
- * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
- * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
- * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
- * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
- * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Jaidev Patwardhan
- *
  */
 
 #include "arch/vtophys.hh"
diff --git a/src/arch/mips/bare_iron/system.hh b/src/arch/mips/bare_iron/system.hh
index 81275ef3f..ab4e02344 100755
--- a/src/arch/mips/bare_iron/system.hh
+++ b/src/arch/mips/bare_iron/system.hh
@@ -1,38 +1,31 @@
 /*
- * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
  *
- * This software is part of the M5 simulator.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
  *
- * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * TO THESE TERMS AND CONDITIONS.
- *
- * Permission is granted to use, copy, create derivative works and
- * distribute this software and such derivative works for any purpose,
- * so long as (1) the copyright notice above, this grant of permission,
- * and the disclaimer below appear in all copies and derivative works
- * made, (2) the copyright notice above is augmented as appropriate to
- * reflect the addition of any new copyrightable work in a derivative
- * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
- * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
- * advertising or publicity pertaining to the use or distribution of
- * this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
- * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
- * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
- * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
- * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
- * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
- * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
- * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
- * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
- * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
- * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Jaidev Patwardhan
- *
  */
 
 #ifndef __ARCH_MIPS_BARE_IRON_SYSTEM_HH__
diff --git a/src/arch/mips/dsp.hh b/src/arch/mips/dsp.hh
index 163044685..fb8d5c4f6 100755
--- a/src/arch/mips/dsp.hh
+++ b/src/arch/mips/dsp.hh
@@ -1,38 +1,31 @@
 /*
- * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
  *
- * This software is part of the M5 simulator.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
  *
- * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * TO THESE TERMS AND CONDITIONS.
- *
- * Permission is granted to use, copy, create derivative works and
- * distribute this software and such derivative works for any purpose,
- * so long as (1) the copyright notice above, this grant of permission,
- * and the disclaimer below appear in all copies and derivative works
- * made, (2) the copyright notice above is augmented as appropriate to
- * reflect the addition of any new copyrightable work in a derivative
- * work (e.g., Copyright (c) <Publication Year> Copyright Owner), and (3)
- * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
- * advertising or publicity pertaining to the use or distribution of
- * this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
- * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
- * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
- * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
- * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
- * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
- * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
- * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
- * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
- * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
- * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Brett Miller
- *
  */
 
 #ifndef __ARCH_MIPS_DSP_HH__
diff --git a/src/arch/mips/dt_constants.hh b/src/arch/mips/dt_constants.hh
index ece8bbbb2..a836c86da 100755
--- a/src/arch/mips/dt_constants.hh
+++ b/src/arch/mips/dt_constants.hh
@@ -1,38 +1,31 @@
 /*
- * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
  *
- * This software is part of the M5 simulator.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
  *
- * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * TO THESE TERMS AND CONDITIONS.
- *
- * Permission is granted to use, copy, create derivative works and
- * distribute this software and such derivative works for any purpose,
- * so long as (1) the copyright notice above, this grant of permission,
- * and the disclaimer below appear in all copies and derivative works
- * made, (2) the copyright notice above is augmented as appropriate to
- * reflect the addition of any new copyrightable work in a derivative
- * work (e.g., Copyright (c) <Publication Year> Copyright Owner), and (3)
- * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
- * advertising or publicity pertaining to the use or distribution of
- * this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
- * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
- * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
- * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
- * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
- * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
- * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
- * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
- * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
- * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
- * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Jaidev Patwardhan
- *
  */
 
 #ifndef __ARCH_MIPS_DT_CONSTANTS_HH__
diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 9e552f1ec..63884e837 100644
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 75157ab92..2d98b5f71 100644
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
diff --git a/src/arch/mips/isa/base.isa b/src/arch/mips/isa/base.isa
index eb063ff1c..4e2b12fc4 100644
--- a/src/arch/mips/isa/base.isa
+++ b/src/arch/mips/isa/base.isa
@@ -82,7 +82,7 @@ output decoder {{
         // Need to find standard way to not print
         // this info. Maybe add bool variable to
         // class?
-        if (mnemonic != "syscall") {
+        if (strcmp(mnemonic, "syscall") != 0) {
             if(_numDestRegs > 0){
                 printReg(ss, _destRegIdx[0]);
             }
@@ -100,7 +100,7 @@ output decoder {{
 
         // Should we define a separate inst. class
         // just for two insts?
-        if(mnemonic == "sll" || mnemonic == "sra"){
+        if (strcmp(mnemonic, "sll") == 0 || strcmp(mnemonic, "sra") == 0) {
             ccprintf(ss,", %d",SA);
         }
 
diff --git a/src/arch/mips/isa/bitfields.isa b/src/arch/mips/isa/bitfields.isa
index 9352e80bf..85d2d96da 100644
--- a/src/arch/mips/isa/bitfields.isa
+++ b/src/arch/mips/isa/bitfields.isa
@@ -1,40 +1,33 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
-//         Jaidev Patwardhan
-
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+//          Jaidev Patwardhan
 
 ////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/mips/isa/formats/basic.isa b/src/arch/mips/isa/formats/basic.isa
index cba54bb78..92568c5fa 100644
--- a/src/arch/mips/isa/formats/basic.isa
+++ b/src/arch/mips/isa/formats/basic.isa
@@ -1,39 +1,35 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+// -*- mode:c++ -*-
 
-//Authors: Steven K. Reinhardt
-//         Korey L. Sewell
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+//          Korey Sewell
 
 // Declarations for execute() methods.
 def template BasicExecDeclare {{
diff --git a/src/arch/mips/isa/formats/branch.isa b/src/arch/mips/isa/formats/branch.isa
index c5f638ccb..78f973a70 100644
--- a/src/arch/mips/isa/formats/branch.isa
+++ b/src/arch/mips/isa/formats/branch.isa
@@ -1,38 +1,32 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -201,7 +195,7 @@ output decoder {{
 
         ccprintf(ss, "%-10s ", mnemonic);
 
-        if ( mnemonic == "jal" ) {
+        if ( strcmp(mnemonic,"jal") == 0 ) {
             Addr npc = pc + 4;
             ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
         } else if (_numSrcRegs == 0) {
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 1671b9ad7..c8eddb1ad 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -1,39 +1,33 @@
 // -*- mode:c++ -*-
 
-// Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
-//         Jaidev Patwardhan
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+//          Jaidev Patwardhan
 
 ////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 84deeb9db..1874d37b2 100755
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -1,39 +1,33 @@
 // -*- mode:c++ -*-
 
-// Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
-//         Brett Miller
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+//          Brett Miller
 
 ////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/mips/isa/formats/formats.isa b/src/arch/mips/isa/formats/formats.isa
index 476987d49..21e8d5c93 100644
--- a/src/arch/mips/isa/formats/formats.isa
+++ b/src/arch/mips/isa/formats/formats.isa
@@ -1,38 +1,32 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
 
 //Templates from this format are used later
 //Include the basic format
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index 2506e1864..74200a74a 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -1,38 +1,32 @@
 // -*- mode:c++ -*-
 
-// Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index 26adf873f..88ff5c1d3 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -1,38 +1,32 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -125,7 +119,7 @@ output header {{
                 {
                     //If Bit 15 is 1 then Sign Extend
                     int32_t temp = sextImm & 0x00008000;
-                    if (temp > 0 && mnemonic != "lui") {
+                    if (temp > 0 && strcmp(mnemonic,"lui") != 0) {
                         sextImm |= 0xFFFF0000;
                     }
                 }
@@ -319,7 +313,7 @@ output decoder {{
                 ss << ", ";
             }
 
-            if( mnemonic == "lui")
+            if(strcmp(mnemonic,"lui") == 0)
                 ccprintf(ss, "0x%x ", sextImm);
             else
                 ss << (int) sextImm;
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index ff9970fa1..f0210c29b 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -1,39 +1,33 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Steve Reinhardt
-//         Korey L. Sewell
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+//          Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index c7be7fe99..81fdc2898 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -1,38 +1,32 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -78,9 +72,9 @@ output decoder {{
     {
         std::stringstream ss;
 
-        if (mnemonic == "mttc0" || mnemonic == "mftc0") {
+        if (strcmp(mnemonic,"mttc0") == 0 || strcmp(mnemonic,"mftc0") == 0) {
             ccprintf(ss, "%-10s r%d, r%d, %d", mnemonic, RT, RD, SEL);
-        } else if (mnemonic == "mftgpr") {
+        } else if (strcmp(mnemonic,"mftgpr") == 0) {
             ccprintf(ss, "%-10s r%d, r%d", mnemonic, RD, RT);
         } else {
             ccprintf(ss, "%-10s r%d, r%d", mnemonic, RT, RD);
diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa
index de5859e2a..3aea5a9c6 100644
--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -1,38 +1,32 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa
index a9e880129..368037955 100644
--- a/src/arch/mips/isa/formats/tlbop.isa
+++ b/src/arch/mips/isa/formats/tlbop.isa
@@ -1,38 +1,32 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa
index ceed14af7..7ebe121aa 100644
--- a/src/arch/mips/isa/formats/trap.isa
+++ b/src/arch/mips/isa/formats/trap.isa
@@ -1,39 +1,33 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
-//         Jaidev Patwardhan
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
+//          Jaidev Patwardhan
 
 ////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index bf91e1fae..2cee38a4b 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -1,39 +1,32 @@
 // -*- mode:c++ -*-
 
-// Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
-
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/mips/isa/formats/util.isa b/src/arch/mips/isa/formats/util.isa
index 9dac8b571..0405aa5b3 100644
--- a/src/arch/mips/isa/formats/util.isa
+++ b/src/arch/mips/isa/formats/util.isa
@@ -1,39 +1,34 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Steven K. Reinhardt
-//         Korey L. Sewell
+// Copyright (c) 2003-2005 The Regents of The University of Michigan
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Steve Reinhardt
+//          Korey Sewell
 
 let {{
 def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
diff --git a/src/arch/mips/isa/includes.isa b/src/arch/mips/isa/includes.isa
index bdd288dd9..aa1c8d8af 100644
--- a/src/arch/mips/isa/includes.isa
+++ b/src/arch/mips/isa/includes.isa
@@ -1,38 +1,32 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/mips/isa/main.isa b/src/arch/mips/isa/main.isa
index de0205b39..1f38a4d2b 100644
--- a/src/arch/mips/isa/main.isa
+++ b/src/arch/mips/isa/main.isa
@@ -1,38 +1,32 @@
 // -*- mode:c++ -*-
 
-// Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
-
-//  This software is part of the M5 simulator.
-
-//  THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
-//  DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
-//  TO THESE TERMS AND CONDITIONS.
-
-//  Permission is granted to use, copy, create derivative works and
-//  distribute this software and such derivative works for any purpose,
-//  so long as (1) the copyright notice above, this grant of permission,
-//  and the disclaimer below appear in all copies and derivative works
-//  made, (2) the copyright notice above is augmented as appropriate to
-//  reflect the addition of any new copyrightable work in a derivative
-//  work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
-//  the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
-//  advertising or publicity pertaining to the use or distribution of
-//  this software without specific, written prior authorization.
-
-//  THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
-//  DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
-//  OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
-//  NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
-//  IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
-//  INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
-//  ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
-//  THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
-//  IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
-//  STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
-//  POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
-
-//Authors: Korey L. Sewell
+// Copyright (c) 2007 MIPS Technologies, Inc.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met: redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer;
+// redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution;
+// neither the name of the copyright holders nor the names of its
+// contributors may be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// Authors: Korey Sewell
 
 ////////////////////////////////////////////////////////////////////
 //
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index d914154ca..fe28ad601 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
diff --git a/src/arch/mips/linux/process.cc b/src/arch/mips/linux/process.cc
index 9908c980b..06e6e2cf4 100644
--- a/src/arch/mips/linux/process.cc
+++ b/src/arch/mips/linux/process.cc
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
@@ -25,7 +26,8 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Korey Sewell
+ * Authors: Gabe Black
+ *          Korey Sewell
  */
 
 #include "arch/mips/linux/linux.hh"
diff --git a/src/arch/mips/linux/system.cc b/src/arch/mips/linux/system.cc
index b8cc4b295..bed863e9d 100644
--- a/src/arch/mips/linux/system.cc
+++ b/src/arch/mips/linux/system.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -28,7 +28,6 @@
  * Authors: Ali Saidi
  *          Lisa Hsu
  *          Nathan Binkert
- *          Steve Reinhardt
  */
 
 /**
diff --git a/src/arch/mips/linux/system.hh b/src/arch/mips/linux/system.hh
index 5de594918..24fb604ed 100644
--- a/src/arch/mips/linux/system.hh
+++ b/src/arch/mips/linux/system.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2004-2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/mips_core_specific.cc b/src/arch/mips/mips_core_specific.cc
index 308574525..a17ebcdf3 100755
--- a/src/arch/mips/mips_core_specific.cc
+++ b/src/arch/mips/mips_core_specific.cc
@@ -46,8 +46,6 @@
 
 #if FULL_SYSTEM
 
-using namespace MipsCore;
-
 ////////////////////////////////////////////////////////////////////////
 //
 //  Machine dependent functions
diff --git a/src/arch/mips/mips_core_specific.hh b/src/arch/mips/mips_core_specific.hh
index 4e20c11f2..0d19bf944 100644
--- a/src/arch/mips/mips_core_specific.hh
+++ b/src/arch/mips/mips_core_specific.hh
@@ -1,51 +1,49 @@
 /*
- * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
  *
- * This software is part of the M5 simulator.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
  *
- * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * TO THESE TERMS AND CONDITIONS.
- *
- * Permission is granted to use, copy, create derivative works and
- * distribute this software and such derivative works for any purpose,
- * so long as (1) the copyright notice above, this grant of permission,
- * and the disclaimer below appear in all copies and derivative works
- * made, (2) the copyright notice above is augmented as appropriate to
- * reflect the addition of any new copyrightable work in a derivative
- * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
- * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
- * advertising or publicity pertaining to the use or distribution of
- * this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
- * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
- * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
- * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
- * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
- * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
- * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
- * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
- * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
- * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
- * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Jaidev Patwardhan
- *
  */
 
-
 #ifndef __ARCH_MIPS_CORE_SPECIFIC_HH__
 #define __ARCH_MIPS_CORE_SPECIFIC_HH__
 
 #include "arch/mips/isa_traits.hh"
 
-namespace MipsISA {
-
-
-
+class ThreadContext;
 
+namespace MipsISA {
+    void initCPU(ThreadContext *tc, int cpuId);
+
+    /**
+     * Function to check for and process any interrupts.
+     * @param tc The thread context.
+     */
+    template <class CPU>
+    void processInterrupts(CPU *cpu);
 };
 
 #endif // __ARCH_MIPS_CORE_SPECIFIC_HH__
diff --git a/src/arch/mips/mmaped_ipr.hh b/src/arch/mips/mmaped_ipr.hh
index 3d51ee4b0..fa82a645c 100644
--- a/src/arch/mips/mmaped_ipr.hh
+++ b/src/arch/mips/mmaped_ipr.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2006 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,7 +25,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Jaidev Patwardhan
+ * Authors: Ali Saidi
  */
 
 #ifndef __ARCH_MIPS_MMAPED_IPR_HH__
diff --git a/src/arch/mips/mt.hh b/src/arch/mips/mt.hh
index 83fb99c71..6765c27a9 100755
--- a/src/arch/mips/mt.hh
+++ b/src/arch/mips/mt.hh
@@ -1,39 +1,31 @@
 /*
- * Copyright N) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
  *
- * This software is part of the M5 simulator.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
  *
- * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * TO THESE TERMS AND CONDITIONS.
- *
- * Permission is granted to use, copy, create derivative works and
- * distribute this software and such derivative works for any purpose,
- * so long as (1) the copyright notice above, this grant of permission,
- * and the disclaimer below appear in all copies and derivative works
- * made, (2) the copyright notice above is augmented as appropriate to
- * reflect the addition of any new copyrightable work in a derivative
- * work (e.g., Copyright N) <Publication Year> Copyright Owner), and (3)
- * the name of MIPS Technologies, Inc. ($(B!H(BMIPS$(B!I(B) is not used in any
- * advertising or publicity pertaining to the use or distribution of
- * this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED $(B!H(BAS IS.$(B!I(B  MIPS MAKES NO WARRANTIES AND
- * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
- * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
- * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
- * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
- * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
- * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
- * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
- * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
- * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
- * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Korey Sewell
- *          Jaidev Patwardhan
- *
  */
 
 #ifndef __ARCH_MIPS_MT_HH__
diff --git a/src/arch/mips/mt_constants.hh b/src/arch/mips/mt_constants.hh
index 0009f4724..3f26f5cba 100755
--- a/src/arch/mips/mt_constants.hh
+++ b/src/arch/mips/mt_constants.hh
@@ -1,45 +1,38 @@
 /*
- * Copyright .AN) 2007 MIPS Technologies, Inc.  All Rights Reserved
+ * Copyright (c) 2007 MIPS Technologies, Inc.
+ * All rights reserved.
  *
- * This software is part of the M5 simulator.
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
  *
- * THIS IS A LEGAL AGREEMENT.  BY DOWNLOADING, USING, COPYING, CREATING
- * DERIVATIVE WORKS, AND/OR DISTRIBUTING THIS SOFTWARE YOU ARE AGREEING
- * TO THESE TERMS AND CONDITIONS.
- *
- * Permission is granted to use, copy, create derivative works and
- * distribute this software and such derivative works for any purpose,
- * so long as (1) the copyright notice above, this grant of permission,
- * and the disclaimer below appear in all copies and derivative works
- * made, (2) the copyright notice above is augmented as appropriate to
- * reflect the addition of any new copyrightable work in a derivative
- * work (e.g., Copyright .AN) <Publication Year> Copyright Owner), and (3)
- * the name of MIPS Technologies, Inc. ($B!H(BMIPS$B!I(B) is not used in any
- * advertising or publicity pertaining to the use or distribution of
- * this software without specific, written prior authorization.
- *
- * THIS SOFTWARE IS PROVIDED $B!H(BAS IS.$B!I(B  MIPS MAKES NO WARRANTIES AND
- * DISCLAIMS ALL WARRANTIES, WHETHER EXPRESS, STATUTORY, IMPLIED OR
- * OTHERWISE, INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND
- * NON-INFRINGEMENT OF THIRD PARTY RIGHTS, REGARDING THIS SOFTWARE.
- * IN NO EVENT SHALL MIPS BE LIABLE FOR ANY DAMAGES, INCLUDING DIRECT,
- * INDIRECT, INCIDENTAL, CONSEQUENTIAL, SPECIAL, OR PUNITIVE DAMAGES OF
- * ANY KIND OR NATURE, ARISING OUT OF OR IN CONNECTION WITH THIS AGREEMENT,
- * THIS SOFTWARE AND/OR THE USE OF THIS SOFTWARE, WHETHER SUCH LIABILITY
- * IS ASSERTED ON THE BASIS OF CONTRACT, TORT (INCLUDING NEGLIGENCE OR
- * STRICT LIABILITY), OR OTHERWISE, EVEN IF MIPS HAS BEEN WARNED OF THE
- * POSSIBILITY OF ANY SUCH LOSS OR DAMAGE IN ADVANCE.
- *
- * Authors: Jaidev Patwardhan
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
+ * Authors: Korey Sewell
+ *          Jaidev Patwardhan
  */
 
 #ifndef __ARCH_MIPS_MT_CONSTANTS_HH__
 #define __ARCH_MIPS_MT_CONSTANTS_HH__
 
 #include "arch/mips/types.hh"
-//#include "config/full_system.hh"
 
 namespace MipsISA
 {
diff --git a/src/arch/mips/pagetable.cc b/src/arch/mips/pagetable.cc
index 912ad7196..5a2d9de7c 100644
--- a/src/arch/mips/pagetable.cc
+++ b/src/arch/mips/pagetable.cc
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
@@ -25,7 +26,9 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Jaidev Patwardhan
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
+ *          Jaidev Patwardhan
  */
 
 #include "arch/mips/pagetable.hh"
diff --git a/src/arch/mips/pagetable.hh b/src/arch/mips/pagetable.hh
index 0500edbce..8c43a7b0c 100755
--- a/src/arch/mips/pagetable.hh
+++ b/src/arch/mips/pagetable.hh
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
@@ -25,7 +26,9 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Jaidev Patwardhan
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
+ *          Jaidev Patwardhan
  */
 
 #ifndef __ARCH_MIPS_PAGETABLE_H__
diff --git a/src/arch/mips/process.hh b/src/arch/mips/process.hh
index a6e661e23..18bf289b8 100644
--- a/src/arch/mips/process.hh
+++ b/src/arch/mips/process.hh
@@ -27,7 +27,6 @@
  *
  * Authors: Gabe Black
  *          Ali Saidi
- *          Korey Sewell
  */
 
 #ifndef __MIPS_PROCESS_HH__
diff --git a/src/arch/mips/regfile.hh b/src/arch/mips/regfile.hh
index 4d1a1c148..29586a652 100644
--- a/src/arch/mips/regfile.hh
+++ b/src/arch/mips/regfile.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2007 MIPS Technologies, Inc.
+ * Copyright (c) 2003-2005 The Regents of The University of Michigan
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,7 +25,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Jaidev Patwardhan
+ * Authors: Gabe Black
  */
 
 #ifndef __ARCH_MIPS_REGFILE_HH__
diff --git a/src/arch/mips/regfile/float_regfile.hh b/src/arch/mips/regfile/float_regfile.hh
index 1c869cc4e..1537855df 100644
--- a/src/arch/mips/regfile/float_regfile.hh
+++ b/src/arch/mips/regfile/float_regfile.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -24,6 +25,8 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
  */
 
 #ifndef __ARCH_MIPS_REGFILE_FLOAT_REGFILE_HH__
diff --git a/src/arch/mips/regfile/int_regfile.cc b/src/arch/mips/regfile/int_regfile.cc
index 81511b67c..c46ecf0b3 100644
--- a/src/arch/mips/regfile/int_regfile.cc
+++ b/src/arch/mips/regfile/int_regfile.cc
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2003-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
  *
  * Authors: Gabe Black
  *          Korey Sewell
+ *          Jaidev Patwardhan
  */
 
 #include "arch/mips/regfile/int_regfile.hh"
diff --git a/src/arch/mips/regfile/int_regfile.hh b/src/arch/mips/regfile/int_regfile.hh
index bdce6bccf..8ddd276e6 100644
--- a/src/arch/mips/regfile/int_regfile.hh
+++ b/src/arch/mips/regfile/int_regfile.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/regfile/misc_regfile.cc b/src/arch/mips/regfile/misc_regfile.cc
index acb6f9c21..5e4c803fc 100755
--- a/src/arch/mips/regfile/misc_regfile.cc
+++ b/src/arch/mips/regfile/misc_regfile.cc
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/regfile/misc_regfile.hh b/src/arch/mips/regfile/misc_regfile.hh
index a92215076..a6f1a15c6 100644
--- a/src/arch/mips/regfile/misc_regfile.hh
+++ b/src/arch/mips/regfile/misc_regfile.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/regfile/regfile.hh b/src/arch/mips/regfile/regfile.hh
index 7d100a905..8304b7cda 100644
--- a/src/arch/mips/regfile/regfile.hh
+++ b/src/arch/mips/regfile/regfile.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
diff --git a/src/arch/mips/system.cc b/src/arch/mips/system.cc
index 434600595..605acfe32 100755
--- a/src/arch/mips/system.cc
+++ b/src/arch/mips/system.cc
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
diff --git a/src/arch/mips/system.hh b/src/arch/mips/system.hh
index d50f8f5aa..13cd3a75f 100755
--- a/src/arch/mips/system.hh
+++ b/src/arch/mips/system.hh
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
diff --git a/src/arch/mips/tlb.cc b/src/arch/mips/tlb.cc
index 2b6bdf9d4..4923e3e3a 100644
--- a/src/arch/mips/tlb.cc
+++ b/src/arch/mips/tlb.cc
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2001-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
@@ -25,7 +26,9 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Jaidev Patwardhan
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
+ *          Jaidev Patwardhan
  */
 
 #include <string>
diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index 0dfe3ecf1..d6f9ac101 100644
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2001-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
@@ -25,7 +26,10 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Jaidev Patwardhan
+ * Authors: Nathan Binkert
+ *          Steve Reinhardt
+ *          Jaidev Patwardhan
+ *          Korey Sewell
  */
 
 #ifndef __ARCH_MIPS_TLB_HH__
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 7282124a9..12ce3af9e 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -141,15 +141,6 @@ namespace MipsISA {
     //
     // CPU Utility
     //
-    void initCPU(ThreadContext *tc, int cpuId);
-
-    /**
-     * Function to check for and process any interrupts.
-     * @param tc The thread context.
-     */
-    template <class TC>
-    void processInterrupts(TC *tc);
-
     void startupCPU(ThreadContext *tc, int cpuId);
 };
 
diff --git a/src/arch/mips/vtophys.cc b/src/arch/mips/vtophys.cc
index 4b9bffa64..dc212862b 100755
--- a/src/arch/mips/vtophys.cc
+++ b/src/arch/mips/vtophys.cc
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2002-2005 The Regents of The University of Michigan
  * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
@@ -25,9 +26,8 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Nathan Binkert
- *          Steve Reinhardt
- *          Ali Saidi
+ * Authors: Ali Saidi
+ *          Nathan Binkert
  *          Jaidev Patwardhan
  */
 
diff --git a/src/arch/mips/vtophys.hh b/src/arch/mips/vtophys.hh
index e38182181..6fde36aac 100644
--- a/src/arch/mips/vtophys.hh
+++ b/src/arch/mips/vtophys.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2002-2005 The Regents of The University of Michigan
+ * Copyright (c) 2007 MIPS Technologies, Inc.
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -25,8 +26,8 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * Authors: Nathan Binkert
- *          Steve Reinhardt
+ * Authors: Ali Saidi
+ *          Nathan Binkert
  *          Jaidev Patwardhan
  */
 
diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index b6880ff94..52791e12a 100644
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -1363,11 +1363,6 @@ TLB::serialize(std::ostream &os)
     SERIALIZE_SCALAR(cntr);
     SERIALIZE_ARRAY(free_list,  cntr);
 
-    for (int x = 0; x < size; x++) {
-        nameOut(os, csprintf("%s.PTE%d", name(), x));
-        tlb[x].serialize(os);
-    }
-
     SERIALIZE_SCALAR(c0_tsb_ps0);
     SERIALIZE_SCALAR(c0_tsb_ps1);
     SERIALIZE_SCALAR(c0_config);
@@ -1376,6 +1371,11 @@ TLB::serialize(std::ostream &os)
     SERIALIZE_SCALAR(cx_config);
     SERIALIZE_SCALAR(sfsr);
     SERIALIZE_SCALAR(tag_access);
+
+    for (int x = 0; x < size; x++) {
+        nameOut(os, csprintf("%s.PTE%d", name(), x));
+        tlb[x].serialize(os);
+    }
 }
 
 void
@@ -1398,14 +1398,6 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
     for (int x = 0; x < cntr; x++)
         freeList.push_back(&tlb[free_list[x]]);
 
-    lookupTable.clear();
-    for (int x = 0; x < size; x++) {
-        tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
-        if (tlb[x].valid)
-            lookupTable.insert(tlb[x].range, &tlb[x]);
-
-    }
-
     UNSERIALIZE_SCALAR(c0_tsb_ps0);
     UNSERIALIZE_SCALAR(c0_tsb_ps1);
     UNSERIALIZE_SCALAR(c0_config);
@@ -1414,6 +1406,14 @@ TLB::unserialize(Checkpoint *cp, const std::string &section)
     UNSERIALIZE_SCALAR(cx_config);
     UNSERIALIZE_SCALAR(sfsr);
     UNSERIALIZE_SCALAR(tag_access);
+
+    lookupTable.clear();
+    for (int x = 0; x < size; x++) {
+        tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x));
+        if (tlb[x].valid)
+            lookupTable.insert(tlb[x].range, &tlb[x]);
+
+    }
 }
 
 void
diff --git a/src/mem/cache/cache_impl.hh b/src/mem/cache/cache_impl.hh
index 92ff4d12e..61846e233 100644
--- a/src/mem/cache/cache_impl.hh
+++ b/src/mem/cache/cache_impl.hh
@@ -881,9 +881,10 @@ Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
         assert(pkt->isRead() || blk->isValid());
     }
 
-    if (pkt->needsExclusive() || !pkt->sharedAsserted()) {
+    if (!pkt->sharedAsserted()) {
         blk->status = BlkValid | BlkWritable;
     } else {
+        assert(!pkt->needsExclusive());
         blk->status = BlkValid;
     }
 
diff --git a/src/mem/cache/miss/mshr.cc b/src/mem/cache/miss/mshr.cc
index 4e9b98481..e2ff444d5 100644
--- a/src/mem/cache/miss/mshr.cc
+++ b/src/mem/cache/miss/mshr.cc
@@ -330,6 +330,23 @@ MSHR::handleFill(Packet *pkt, CacheBlk *blk)
         // service... assert shared line on its behalf
         pkt->assertShared();
     }
+
+    if (!pkt->sharedAsserted() && !pendingInvalidate
+        && deferredTargets->needsExclusive) {
+        // We got an exclusive response, but we have deferred targets
+        // which are waiting to request an exclusive copy (not because
+        // of a pending invalidate).  This can happen if the original
+        // request was for a read-only (non-exclusive) block, but we
+        // got an exclusive copy anyway because of the E part of the
+        // MOESI/MESI protocol.  Since we got the exclusive copy
+        // there's no need to defer the targets, so move them up to
+        // the regular target list.
+        assert(!targets->needsExclusive);
+        targets->needsExclusive = true;
+        // this clears out deferredTargets too
+        targets->splice(targets->end(), *deferredTargets);
+        deferredTargets->resetFlags();
+    }
 }
 
 
diff --git a/src/mem/physical.cc b/src/mem/physical.cc
index 8c56d340f..a3a9df64e 100644
--- a/src/mem/physical.cc
+++ b/src/mem/physical.cc
@@ -70,6 +70,10 @@ PhysicalMemory::PhysicalMemory(const Params *p)
         memset(pmemAddr, 0, p->range.size());
 
     pagePtr = 0;
+
+    cachedSize = params()->range.size();
+    cachedStart = params()->range.start;
+
 }
 
 void
diff --git a/src/mem/physical.hh b/src/mem/physical.hh
index b06cc90f8..c3749bd5b 100644
--- a/src/mem/physical.hh
+++ b/src/mem/physical.hh
@@ -149,10 +149,12 @@ class PhysicalMemory : public MemObject
     std::vector<MemoryPort*> ports;
     typedef std::vector<MemoryPort*>::iterator PortIterator;
 
+    uint64_t cachedSize;
+    uint64_t cachedStart;
   public:
     Addr new_page();
-    uint64_t size() { return params()->range.size(); }
-    uint64_t start() { return params()->range.start; }
+    uint64_t size() { return cachedSize; }
+    uint64_t start() { return cachedStart; }
 
   public:
     typedef PhysicalMemoryParams Params;
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
index ba0757e28..ab935595d 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/m5stats.txt
@@ -1,70 +1,70 @@
 
 ---------- Begin Simulation Statistics ----------
-host_mem_usage                                 368532                       # Number of bytes of host memory used
-host_seconds                                   160.06                       # Real time elapsed on the host
-host_tick_rate                                1018563                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 366088                       # Number of bytes of host memory used
+host_seconds                                   156.35                       # Real time elapsed on the host
+host_tick_rate                                1042333                       # Simulator tick rate (ticks/s)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
 sim_seconds                                  0.000163                       # Number of seconds simulated
-sim_ticks                                   163028791                       # Number of ticks simulated
-system.cpu0.l1c.ReadReq_accesses                44866                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.ReadReq_avg_miss_latency 23548.187676                       # average ReadReq miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 22546.401324                       # average ReadReq mshr miss latency
+sim_ticks                                   162969030                       # Number of ticks simulated
+system.cpu0.l1c.ReadReq_accesses                44649                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_avg_miss_latency 23666.382848                       # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 22664.543419                       # average ReadReq mshr miss latency
 system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.ReadReq_hits                     7557                       # number of ReadReq hits
-system.cpu0.l1c.ReadReq_miss_latency        878559334                       # number of ReadReq miss cycles
-system.cpu0.l1c.ReadReq_miss_rate            0.831565                       # miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_misses                  37309                       # number of ReadReq misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency    841183687                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate       0.831565                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.ReadReq_mshr_misses             37309                       # number of ReadReq MSHR misses
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency    470726871                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_accesses               24129                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_avg_miss_latency 28316.559940                       # average WriteReq miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 27314.645519                       # average WriteReq mshr miss latency
+system.cpu0.l1c.ReadReq_hits                     7488                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_miss_latency        879466453                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_rate            0.832292                       # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_misses                  37161                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency    842237098                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate       0.832292                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_misses             37161                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency    472367401                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_accesses               24088                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_avg_miss_latency 28277.359652                       # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 27275.445460                       # average WriteReq mshr miss latency
 system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_hits                     864                       # number of WriteReq hits
-system.cpu0.l1c.WriteReq_miss_latency       658784767                       # number of WriteReq miss cycles
-system.cpu0.l1c.WriteReq_miss_rate           0.964192                       # miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_misses                 23265                       # number of WriteReq misses
-system.cpu0.l1c.WriteReq_mshr_miss_latency    635475228                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_rate      0.964192                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.WriteReq_mshr_misses            23265                       # number of WriteReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency    289831424                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.avg_blocked_cycles_no_mshrs  2291.330126                       # average number of cycles each access was blocked
+system.cpu0.l1c.WriteReq_hits                     885                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_miss_latency       656119576                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_rate           0.963260                       # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_misses                 23203                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_mshr_miss_latency    632872161                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_rate      0.963260                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_misses            23203                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency    285830278                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.avg_blocked_cycles_no_mshrs  2295.113017                       # average number of cycles each access was blocked
 system.cpu0.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu0.l1c.avg_refs                     0.411975                       # Average number of references to valid blocks.
-system.cpu0.l1c.blocked_no_mshrs                69625                       # number of cycles access was blocked
+system.cpu0.l1c.avg_refs                     0.412189                       # Average number of references to valid blocks.
+system.cpu0.l1c.blocked_no_mshrs                69538                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
-system.cpu0.l1c.blocked_cycles_no_mshrs     159533860                       # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles_no_mshrs     159597569                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.demand_accesses                 68995                       # number of demand (read+write) accesses
-system.cpu0.l1c.demand_avg_miss_latency  25379.603477                       # average overall miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency 24377.767937                       # average overall mshr miss latency
-system.cpu0.l1c.demand_hits                      8421                       # number of demand (read+write) hits
-system.cpu0.l1c.demand_miss_latency        1537344101                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.demand_miss_rate             0.877948                       # miss rate for demand accesses
-system.cpu0.l1c.demand_misses                   60574                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_accesses                 68737                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_avg_miss_latency  25438.771934                       # average overall miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency 24436.903767                       # average overall mshr miss latency
+system.cpu0.l1c.demand_hits                      8373                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_miss_latency        1535586029                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_rate             0.878188                       # miss rate for demand accesses
+system.cpu0.l1c.demand_misses                   60364                       # number of demand (read+write) misses
 system.cpu0.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu0.l1c.demand_mshr_miss_latency   1476658915                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_rate        0.877948                       # mshr miss rate for demand accesses
-system.cpu0.l1c.demand_mshr_misses              60574                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_miss_latency   1475109259                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_rate        0.878188                       # mshr miss rate for demand accesses
+system.cpu0.l1c.demand_mshr_misses              60364                       # number of demand (read+write) MSHR misses
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu0.l1c.overall_accesses                68995                       # number of overall (read+write) accesses
-system.cpu0.l1c.overall_avg_miss_latency 25379.603477                       # average overall miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency 24377.767937                       # average overall mshr miss latency
+system.cpu0.l1c.overall_accesses                68737                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_avg_miss_latency 25438.771934                       # average overall miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency 24436.903767                       # average overall mshr miss latency
 system.cpu0.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.l1c.overall_hits                     8421                       # number of overall hits
-system.cpu0.l1c.overall_miss_latency       1537344101                       # number of overall miss cycles
-system.cpu0.l1c.overall_miss_rate            0.877948                       # miss rate for overall accesses
-system.cpu0.l1c.overall_misses                  60574                       # number of overall misses
+system.cpu0.l1c.overall_hits                     8373                       # number of overall hits
+system.cpu0.l1c.overall_miss_latency       1535586029                       # number of overall miss cycles
+system.cpu0.l1c.overall_miss_rate            0.878188                       # miss rate for overall accesses
+system.cpu0.l1c.overall_misses                  60364                       # number of overall misses
 system.cpu0.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu0.l1c.overall_mshr_miss_latency   1476658915                       # number of overall MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_rate       0.877948                       # mshr miss rate for overall accesses
-system.cpu0.l1c.overall_mshr_misses             60574                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_uncacheable_latency    760558295                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_miss_latency   1475109259                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_rate       0.878188                       # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_misses             60364                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_uncacheable_latency    758197679                       # number of overall MSHR uncacheable cycles
 system.cpu0.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu0.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu0.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -75,75 +75,75 @@ system.cpu0.l1c.prefetcher.num_hwpf_issued            0                       #
 system.cpu0.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu0.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu0.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu0.l1c.replacements                    27647                       # number of replacements
-system.cpu0.l1c.sampled_refs                    27992                       # Sample count of references to valid blocks.
+system.cpu0.l1c.replacements                    27517                       # number of replacements
+system.cpu0.l1c.sampled_refs                    27861                       # Sample count of references to valid blocks.
 system.cpu0.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.l1c.tagsinuse                  346.649245                       # Cycle average of tags in use
-system.cpu0.l1c.total_refs                      11532                       # Total number of references to valid blocks.
+system.cpu0.l1c.tagsinuse                  345.687561                       # Cycle average of tags in use
+system.cpu0.l1c.total_refs                      11484                       # Total number of references to valid blocks.
 system.cpu0.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.writebacks                      10949                       # number of writebacks
+system.cpu0.l1c.writebacks                      10876                       # number of writebacks
 system.cpu0.num_copies                              0                       # number of copy accesses completed
-system.cpu0.num_reads                           99664                       # number of read accesses completed
-system.cpu0.num_writes                          53877                       # number of write accesses completed
-system.cpu1.l1c.ReadReq_accesses                44752                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.ReadReq_avg_miss_latency 23635.008165                       # average ReadReq miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 22633.168292                       # average ReadReq mshr miss latency
+system.cpu0.num_reads                           99133                       # number of read accesses completed
+system.cpu0.num_writes                          53626                       # number of write accesses completed
+system.cpu1.l1c.ReadReq_accesses                44934                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_avg_miss_latency 23743.367678                       # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 22741.526988                       # average ReadReq mshr miss latency
 system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.ReadReq_hits                     7519                       # number of ReadReq hits
-system.cpu1.l1c.ReadReq_miss_latency        880002259                       # number of ReadReq miss cycles
-system.cpu1.l1c.ReadReq_miss_rate            0.831985                       # miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_misses                  37233                       # number of ReadReq misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency    842700755                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate       0.831985                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.ReadReq_mshr_misses             37233                       # number of ReadReq MSHR misses
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency    466627047                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_accesses               24332                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_avg_miss_latency 28314.022230                       # average WriteReq miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 27312.235893                       # average WriteReq mshr miss latency
+system.cpu1.l1c.ReadReq_hits                     7510                       # number of ReadReq hits
+system.cpu1.l1c.ReadReq_miss_latency        888571792                       # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_rate            0.832866                       # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_misses                  37424                       # number of ReadReq misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency    851078906                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate       0.832866                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_mshr_misses             37424                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency    461314055                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_accesses               24224                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_avg_miss_latency 28268.157373                       # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 27266.371925                       # average WriteReq mshr miss latency
 system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_hits                     940                       # number of WriteReq hits
-system.cpu1.l1c.WriteReq_miss_latency       662321608                       # number of WriteReq miss cycles
-system.cpu1.l1c.WriteReq_miss_rate           0.961368                       # miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_misses                 23392                       # number of WriteReq misses
-system.cpu1.l1c.WriteReq_mshr_miss_latency    638887822                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_rate      0.961368                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.WriteReq_mshr_misses            23392                       # number of WriteReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency    282776699                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.avg_blocked_cycles_no_mshrs  2295.997672                       # average number of cycles each access was blocked
+system.cpu1.l1c.WriteReq_hits                     929                       # number of WriteReq hits
+system.cpu1.l1c.WriteReq_miss_latency       658506726                       # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_rate           0.961650                       # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_misses                 23295                       # number of WriteReq misses
+system.cpu1.l1c.WriteReq_mshr_miss_latency    635170134                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_rate      0.961650                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_mshr_misses            23295                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency    280215693                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.avg_blocked_cycles_no_mshrs  2295.300422                       # average number of cycles each access was blocked
 system.cpu1.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu1.l1c.avg_refs                     0.414619                       # Average number of references to valid blocks.
-system.cpu1.l1c.blocked_no_mshrs                69602                       # number of cycles access was blocked
+system.cpu1.l1c.avg_refs                     0.407660                       # Average number of references to valid blocks.
+system.cpu1.l1c.blocked_no_mshrs                69592                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
-system.cpu1.l1c.blocked_cycles_no_mshrs     159806030                       # number of cycles access was blocked
+system.cpu1.l1c.blocked_cycles_no_mshrs     159734547                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.demand_accesses                 69084                       # number of demand (read+write) accesses
-system.cpu1.l1c.demand_avg_miss_latency  25440.393682                       # average overall miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency 24438.574466                       # average overall mshr miss latency
-system.cpu1.l1c.demand_hits                      8459                       # number of demand (read+write) hits
-system.cpu1.l1c.demand_miss_latency        1542323867                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.demand_miss_rate             0.877555                       # miss rate for demand accesses
-system.cpu1.l1c.demand_misses                   60625                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_accesses                 69158                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_avg_miss_latency  25479.314844                       # average overall miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency 24477.495347                       # average overall mshr miss latency
+system.cpu1.l1c.demand_hits                      8439                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_miss_latency        1547078518                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_rate             0.877975                       # miss rate for demand accesses
+system.cpu1.l1c.demand_misses                   60719                       # number of demand (read+write) misses
 system.cpu1.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu1.l1c.demand_mshr_miss_latency   1481588577                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_rate        0.877555                       # mshr miss rate for demand accesses
-system.cpu1.l1c.demand_mshr_misses              60625                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_miss_latency   1486249040                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_rate        0.877975                       # mshr miss rate for demand accesses
+system.cpu1.l1c.demand_mshr_misses              60719                       # number of demand (read+write) MSHR misses
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu1.l1c.overall_accesses                69084                       # number of overall (read+write) accesses
-system.cpu1.l1c.overall_avg_miss_latency 25440.393682                       # average overall miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency 24438.574466                       # average overall mshr miss latency
+system.cpu1.l1c.overall_accesses                69158                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_avg_miss_latency 25479.314844                       # average overall miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency 24477.495347                       # average overall mshr miss latency
 system.cpu1.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.l1c.overall_hits                     8459                       # number of overall hits
-system.cpu1.l1c.overall_miss_latency       1542323867                       # number of overall miss cycles
-system.cpu1.l1c.overall_miss_rate            0.877555                       # miss rate for overall accesses
-system.cpu1.l1c.overall_misses                  60625                       # number of overall misses
+system.cpu1.l1c.overall_hits                     8439                       # number of overall hits
+system.cpu1.l1c.overall_miss_latency       1547078518                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_rate            0.877975                       # miss rate for overall accesses
+system.cpu1.l1c.overall_misses                  60719                       # number of overall misses
 system.cpu1.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu1.l1c.overall_mshr_miss_latency   1481588577                       # number of overall MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_rate       0.877555                       # mshr miss rate for overall accesses
-system.cpu1.l1c.overall_mshr_misses             60625                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_uncacheable_latency    749403746                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_miss_latency   1486249040                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_rate       0.877975                       # mshr miss rate for overall accesses
+system.cpu1.l1c.overall_mshr_misses             60719                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_uncacheable_latency    741529748                       # number of overall MSHR uncacheable cycles
 system.cpu1.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu1.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu1.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -154,75 +154,75 @@ system.cpu1.l1c.prefetcher.num_hwpf_issued            0                       #
 system.cpu1.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu1.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu1.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu1.l1c.replacements                    27644                       # number of replacements
-system.cpu1.l1c.sampled_refs                    28004                       # Sample count of references to valid blocks.
+system.cpu1.l1c.replacements                    27839                       # number of replacements
+system.cpu1.l1c.sampled_refs                    28200                       # Sample count of references to valid blocks.
 system.cpu1.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.l1c.tagsinuse                  346.128231                       # Cycle average of tags in use
-system.cpu1.l1c.total_refs                      11611                       # Total number of references to valid blocks.
+system.cpu1.l1c.tagsinuse                  345.864238                       # Cycle average of tags in use
+system.cpu1.l1c.total_refs                      11496                       # Total number of references to valid blocks.
 system.cpu1.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.writebacks                      10912                       # number of writebacks
+system.cpu1.l1c.writebacks                      10966                       # number of writebacks
 system.cpu1.num_copies                              0                       # number of copy accesses completed
-system.cpu1.num_reads                           99711                       # number of read accesses completed
-system.cpu1.num_writes                          53813                       # number of write accesses completed
-system.cpu2.l1c.ReadReq_accesses                44908                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.ReadReq_avg_miss_latency 23697.485035                       # average ReadReq miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 22695.564679                       # average ReadReq mshr miss latency
+system.cpu1.num_reads                           99887                       # number of read accesses completed
+system.cpu1.num_writes                          53581                       # number of write accesses completed
+system.cpu2.l1c.ReadReq_accesses                44676                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_avg_miss_latency 23702.165485                       # average ReadReq miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 22700.326495                       # average ReadReq mshr miss latency
 system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.ReadReq_hits                     7655                       # number of ReadReq hits
-system.cpu2.l1c.ReadReq_miss_latency        882802410                       # number of ReadReq miss cycles
-system.cpu2.l1c.ReadReq_miss_rate            0.829540                       # miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_misses                  37253                       # number of ReadReq misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency    845477871                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate       0.829540                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.ReadReq_mshr_misses             37253                       # number of ReadReq MSHR misses
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency    465312435                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_accesses               24367                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_avg_miss_latency 28178.781659                       # average WriteReq miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 27176.866738                       # average WriteReq mshr miss latency
+system.cpu2.l1c.ReadReq_hits                     7579                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_miss_latency        879279233                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_rate            0.830356                       # miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_misses                  37097                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency    842114012                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate       0.830356                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.ReadReq_mshr_misses             37097                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency    463945660                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_accesses               24311                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_avg_miss_latency 28427.205208                       # average WriteReq miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 27425.376280                       # average WriteReq mshr miss latency
 system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_hits                     977                       # number of WriteReq hits
-system.cpu2.l1c.WriteReq_miss_latency       659101703                       # number of WriteReq miss cycles
-system.cpu2.l1c.WriteReq_miss_rate           0.959905                       # miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_misses                 23390                       # number of WriteReq misses
-system.cpu2.l1c.WriteReq_mshr_miss_latency    635666913                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_rate      0.959905                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.WriteReq_mshr_misses            23390                       # number of WriteReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency    291069881                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.avg_blocked_cycles_no_mshrs  2292.851688                       # average number of cycles each access was blocked
+system.cpu2.l1c.WriteReq_hits                     964                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_miss_latency       663689960                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_rate           0.960347                       # miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_misses                 23347                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_mshr_miss_latency    640300260                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_rate      0.960347                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.WriteReq_mshr_misses            23347                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency    293541767                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.avg_blocked_cycles_no_mshrs  2298.353100                       # average number of cycles each access was blocked
 system.cpu2.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu2.l1c.avg_refs                     0.415602                       # Average number of references to valid blocks.
-system.cpu2.l1c.blocked_no_mshrs                69421                       # number of cycles access was blocked
+system.cpu2.l1c.avg_refs                     0.415183                       # Average number of references to valid blocks.
+system.cpu2.l1c.blocked_no_mshrs                69275                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
-system.cpu2.l1c.blocked_cycles_no_mshrs     159172057                       # number of cycles access was blocked
+system.cpu2.l1c.blocked_cycles_no_mshrs     159218411                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.demand_accesses                 69275                       # number of demand (read+write) accesses
-system.cpu2.l1c.demand_avg_miss_latency  25425.920766                       # average overall miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency 24424.002506                       # average overall mshr miss latency
-system.cpu2.l1c.demand_hits                      8632                       # number of demand (read+write) hits
-system.cpu2.l1c.demand_miss_latency        1541904113                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.demand_miss_rate             0.875395                       # miss rate for demand accesses
-system.cpu2.l1c.demand_misses                   60643                       # number of demand (read+write) misses
+system.cpu2.l1c.demand_accesses                 68987                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_avg_miss_latency  25527.251555                       # average overall miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency 24525.416452                       # average overall mshr miss latency
+system.cpu2.l1c.demand_hits                      8543                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_miss_latency        1542969193                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_rate             0.876165                       # miss rate for demand accesses
+system.cpu2.l1c.demand_misses                   60444                       # number of demand (read+write) misses
 system.cpu2.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu2.l1c.demand_mshr_miss_latency   1481144784                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_rate        0.875395                       # mshr miss rate for demand accesses
-system.cpu2.l1c.demand_mshr_misses              60643                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_miss_latency   1482414272                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_rate        0.876165                       # mshr miss rate for demand accesses
+system.cpu2.l1c.demand_mshr_misses              60444                       # number of demand (read+write) MSHR misses
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu2.l1c.overall_accesses                69275                       # number of overall (read+write) accesses
-system.cpu2.l1c.overall_avg_miss_latency 25425.920766                       # average overall miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency 24424.002506                       # average overall mshr miss latency
+system.cpu2.l1c.overall_accesses                68987                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_avg_miss_latency 25527.251555                       # average overall miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency 24525.416452                       # average overall mshr miss latency
 system.cpu2.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu2.l1c.overall_hits                     8632                       # number of overall hits
-system.cpu2.l1c.overall_miss_latency       1541904113                       # number of overall miss cycles
-system.cpu2.l1c.overall_miss_rate            0.875395                       # miss rate for overall accesses
-system.cpu2.l1c.overall_misses                  60643                       # number of overall misses
+system.cpu2.l1c.overall_hits                     8543                       # number of overall hits
+system.cpu2.l1c.overall_miss_latency       1542969193                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_rate            0.876165                       # miss rate for overall accesses
+system.cpu2.l1c.overall_misses                  60444                       # number of overall misses
 system.cpu2.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu2.l1c.overall_mshr_miss_latency   1481144784                       # number of overall MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_rate       0.875395                       # mshr miss rate for overall accesses
-system.cpu2.l1c.overall_mshr_misses             60643                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_uncacheable_latency    756382316                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_miss_latency   1482414272                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_rate       0.876165                       # mshr miss rate for overall accesses
+system.cpu2.l1c.overall_mshr_misses             60444                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_uncacheable_latency    757487427                       # number of overall MSHR uncacheable cycles
 system.cpu2.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu2.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu2.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -233,75 +233,75 @@ system.cpu2.l1c.prefetcher.num_hwpf_issued            0                       #
 system.cpu2.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu2.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu2.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu2.l1c.replacements                    27925                       # number of replacements
-system.cpu2.l1c.sampled_refs                    28265                       # Sample count of references to valid blocks.
+system.cpu2.l1c.replacements                    27813                       # number of replacements
+system.cpu2.l1c.sampled_refs                    28149                       # Sample count of references to valid blocks.
 system.cpu2.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu2.l1c.tagsinuse                  348.298398                       # Cycle average of tags in use
-system.cpu2.l1c.total_refs                      11747                       # Total number of references to valid blocks.
+system.cpu2.l1c.tagsinuse                  347.648591                       # Cycle average of tags in use
+system.cpu2.l1c.total_refs                      11687                       # Total number of references to valid blocks.
 system.cpu2.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.writebacks                      11043                       # number of writebacks
+system.cpu2.l1c.writebacks                      11045                       # number of writebacks
 system.cpu2.num_copies                              0                       # number of copy accesses completed
-system.cpu2.num_reads                           99614                       # number of read accesses completed
-system.cpu2.num_writes                          54181                       # number of write accesses completed
-system.cpu3.l1c.ReadReq_accesses                44867                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.ReadReq_avg_miss_latency 23550.912053                       # average ReadReq miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 22549.071641                       # average ReadReq mshr miss latency
+system.cpu2.num_reads                           99140                       # number of read accesses completed
+system.cpu2.num_writes                          54118                       # number of write accesses completed
+system.cpu3.l1c.ReadReq_accesses                44967                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_avg_miss_latency 23556.282690                       # average ReadReq miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 22554.335004                       # average ReadReq mshr miss latency
 system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.ReadReq_hits                     7458                       # number of ReadReq hits
-system.cpu3.l1c.ReadReq_miss_latency        881016069                       # number of ReadReq miss cycles
-system.cpu3.l1c.ReadReq_miss_rate            0.833775                       # miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_misses                  37409                       # number of ReadReq misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency    843538221                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate       0.833775                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.ReadReq_mshr_misses             37409                       # number of ReadReq MSHR misses
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency    469382996                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_accesses               24208                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_avg_miss_latency 28215.610982                       # average WriteReq miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 27213.782676                       # average WriteReq mshr miss latency
+system.cpu3.l1c.ReadReq_hits                     7463                       # number of ReadReq hits
+system.cpu3.l1c.ReadReq_miss_latency        883454826                       # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_rate            0.834034                       # miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_misses                  37504                       # number of ReadReq misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency    845877780                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate       0.834034                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.ReadReq_mshr_misses             37504                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency    463016288                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_accesses               24252                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_avg_miss_latency 28359.679643                       # average WriteReq miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 27357.936889                       # average WriteReq mshr miss latency
 system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_hits                     934                       # number of WriteReq hits
-system.cpu3.l1c.WriteReq_miss_latency       656690130                       # number of WriteReq miss cycles
-system.cpu3.l1c.WriteReq_miss_rate           0.961418                       # miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_misses                 23274                       # number of WriteReq misses
-system.cpu3.l1c.WriteReq_mshr_miss_latency    633373578                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_rate      0.961418                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.WriteReq_mshr_misses            23274                       # number of WriteReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency    292909328                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.avg_blocked_cycles_no_mshrs  2286.071306                       # average number of cycles each access was blocked
+system.cpu3.l1c.WriteReq_hits                     928                       # number of WriteReq hits
+system.cpu3.l1c.WriteReq_miss_latency       661461168                       # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_rate           0.961735                       # miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_misses                 23324                       # number of WriteReq misses
+system.cpu3.l1c.WriteReq_mshr_miss_latency    638096520                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_rate      0.961735                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.WriteReq_mshr_misses            23324                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency    286853981                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.avg_blocked_cycles_no_mshrs  2284.842199                       # average number of cycles each access was blocked
 system.cpu3.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu3.l1c.avg_refs                     0.400684                       # Average number of references to valid blocks.
-system.cpu3.l1c.blocked_no_mshrs                69658                       # number of cycles access was blocked
+system.cpu3.l1c.avg_refs                     0.401096                       # Average number of references to valid blocks.
+system.cpu3.l1c.blocked_no_mshrs                69803                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
-system.cpu3.l1c.blocked_cycles_no_mshrs     159243155                       # number of cycles access was blocked
+system.cpu3.l1c.blocked_cycles_no_mshrs     159488840                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.demand_accesses                 69075                       # number of demand (read+write) accesses
-system.cpu3.l1c.demand_avg_miss_latency  25339.983175                       # average overall miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency 24338.147405                       # average overall mshr miss latency
-system.cpu3.l1c.demand_hits                      8392                       # number of demand (read+write) hits
-system.cpu3.l1c.demand_miss_latency        1537706199                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.demand_miss_rate             0.878509                       # miss rate for demand accesses
-system.cpu3.l1c.demand_misses                   60683                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_accesses                 69219                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_avg_miss_latency  25398.106037                       # average overall miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency 24396.236930                       # average overall mshr miss latency
+system.cpu3.l1c.demand_hits                      8391                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_miss_latency        1544915994                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_rate             0.878776                       # miss rate for demand accesses
+system.cpu3.l1c.demand_misses                   60828                       # number of demand (read+write) misses
 system.cpu3.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu3.l1c.demand_mshr_miss_latency   1476911799                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_rate        0.878509                       # mshr miss rate for demand accesses
-system.cpu3.l1c.demand_mshr_misses              60683                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_miss_latency   1483974300                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_rate        0.878776                       # mshr miss rate for demand accesses
+system.cpu3.l1c.demand_mshr_misses              60828                       # number of demand (read+write) MSHR misses
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu3.l1c.overall_accesses                69075                       # number of overall (read+write) accesses
-system.cpu3.l1c.overall_avg_miss_latency 25339.983175                       # average overall miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency 24338.147405                       # average overall mshr miss latency
+system.cpu3.l1c.overall_accesses                69219                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_avg_miss_latency 25398.106037                       # average overall miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency 24396.236930                       # average overall mshr miss latency
 system.cpu3.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu3.l1c.overall_hits                     8392                       # number of overall hits
-system.cpu3.l1c.overall_miss_latency       1537706199                       # number of overall miss cycles
-system.cpu3.l1c.overall_miss_rate            0.878509                       # miss rate for overall accesses
-system.cpu3.l1c.overall_misses                  60683                       # number of overall misses
+system.cpu3.l1c.overall_hits                     8391                       # number of overall hits
+system.cpu3.l1c.overall_miss_latency       1544915994                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_rate            0.878776                       # miss rate for overall accesses
+system.cpu3.l1c.overall_misses                  60828                       # number of overall misses
 system.cpu3.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu3.l1c.overall_mshr_miss_latency   1476911799                       # number of overall MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_rate       0.878509                       # mshr miss rate for overall accesses
-system.cpu3.l1c.overall_mshr_misses             60683                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_uncacheable_latency    762292324                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_miss_latency   1483974300                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_rate       0.878776                       # mshr miss rate for overall accesses
+system.cpu3.l1c.overall_mshr_misses             60828                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_uncacheable_latency    749870269                       # number of overall MSHR uncacheable cycles
 system.cpu3.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu3.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu3.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -312,75 +312,75 @@ system.cpu3.l1c.prefetcher.num_hwpf_issued            0                       #
 system.cpu3.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu3.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu3.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu3.l1c.replacements                    28024                       # number of replacements
-system.cpu3.l1c.sampled_refs                    28379                       # Sample count of references to valid blocks.
+system.cpu3.l1c.replacements                    28133                       # number of replacements
+system.cpu3.l1c.sampled_refs                    28477                       # Sample count of references to valid blocks.
 system.cpu3.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu3.l1c.tagsinuse                  347.503603                       # Cycle average of tags in use
-system.cpu3.l1c.total_refs                      11371                       # Total number of references to valid blocks.
+system.cpu3.l1c.tagsinuse                  348.344200                       # Cycle average of tags in use
+system.cpu3.l1c.total_refs                      11422                       # Total number of references to valid blocks.
 system.cpu3.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.writebacks                      10929                       # number of writebacks
+system.cpu3.l1c.writebacks                      11005                       # number of writebacks
 system.cpu3.num_copies                              0                       # number of copy accesses completed
-system.cpu3.num_reads                           99752                       # number of read accesses completed
-system.cpu3.num_writes                          53813                       # number of write accesses completed
-system.cpu4.l1c.ReadReq_accesses                45052                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.ReadReq_avg_miss_latency 23676.379185                       # average ReadReq miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 22674.538283                       # average ReadReq mshr miss latency
+system.cpu3.num_reads                           99592                       # number of read accesses completed
+system.cpu3.num_writes                          53713                       # number of write accesses completed
+system.cpu4.l1c.ReadReq_accesses                44752                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_avg_miss_latency 23804.358655                       # average ReadReq miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 22802.626506                       # average ReadReq mshr miss latency
 system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.ReadReq_hits                     7503                       # number of ReadReq hits
-system.cpu4.l1c.ReadReq_miss_latency        889024362                       # number of ReadReq miss cycles
-system.cpu4.l1c.ReadReq_miss_rate            0.833459                       # miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_misses                  37549                       # number of ReadReq misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency    851406238                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate       0.833459                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.ReadReq_mshr_misses             37549                       # number of ReadReq MSHR misses
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency    464076918                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_accesses               23965                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_avg_miss_latency 28402.408395                       # average WriteReq miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 27400.538398                       # average WriteReq mshr miss latency
+system.cpu4.l1c.ReadReq_hits                     7485                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_miss_latency        887117034                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_rate            0.832745                       # miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_misses                  37267                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency    849785482                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate       0.832745                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.ReadReq_mshr_misses             37267                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency    460944695                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_accesses               24051                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_avg_miss_latency 28478.181673                       # average WriteReq miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 27476.224597                       # average WriteReq mshr miss latency
 system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_hits                     904                       # number of WriteReq hits
-system.cpu4.l1c.WriteReq_miss_latency       654987940                       # number of WriteReq miss cycles
-system.cpu4.l1c.WriteReq_miss_rate           0.962278                       # miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_misses                 23061                       # number of WriteReq misses
-system.cpu4.l1c.WriteReq_mshr_miss_latency    631883816                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_rate      0.962278                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.WriteReq_mshr_misses            23061                       # number of WriteReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency    290473799                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.avg_blocked_cycles_no_mshrs  2297.684951                       # average number of cycles each access was blocked
+system.cpu4.l1c.WriteReq_hits                     894                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_miss_latency       659469253                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_rate           0.962829                       # miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_misses                 23157                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_mshr_miss_latency    636266933                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_rate      0.962829                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.WriteReq_mshr_misses            23157                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency    290316641                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.avg_blocked_cycles_no_mshrs  2303.542545                       # average number of cycles each access was blocked
 system.cpu4.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu4.l1c.avg_refs                     0.405770                       # Average number of references to valid blocks.
-system.cpu4.l1c.blocked_no_mshrs                69513                       # number of cycles access was blocked
+system.cpu4.l1c.avg_refs                     0.410509                       # Average number of references to valid blocks.
+system.cpu4.l1c.blocked_no_mshrs                69338                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
-system.cpu4.l1c.blocked_cycles_no_mshrs     159718974                       # number of cycles access was blocked
+system.cpu4.l1c.blocked_cycles_no_mshrs     159723033                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.demand_accesses                 69017                       # number of demand (read+write) accesses
-system.cpu4.l1c.demand_avg_miss_latency  25474.547137                       # average overall miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency 24472.695166                       # average overall mshr miss latency
-system.cpu4.l1c.demand_hits                      8407                       # number of demand (read+write) hits
-system.cpu4.l1c.demand_miss_latency        1544012302                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.demand_miss_rate             0.878189                       # miss rate for demand accesses
-system.cpu4.l1c.demand_misses                   60610                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_accesses                 68803                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_avg_miss_latency  25595.562806                       # average overall miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency 24593.744456                       # average overall mshr miss latency
+system.cpu4.l1c.demand_hits                      8379                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_miss_latency        1546586287                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_rate             0.878218                       # miss rate for demand accesses
+system.cpu4.l1c.demand_misses                   60424                       # number of demand (read+write) misses
 system.cpu4.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu4.l1c.demand_mshr_miss_latency   1483290054                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_rate        0.878189                       # mshr miss rate for demand accesses
-system.cpu4.l1c.demand_mshr_misses              60610                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_miss_latency   1486052415                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_rate        0.878218                       # mshr miss rate for demand accesses
+system.cpu4.l1c.demand_mshr_misses              60424                       # number of demand (read+write) MSHR misses
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu4.l1c.overall_accesses                69017                       # number of overall (read+write) accesses
-system.cpu4.l1c.overall_avg_miss_latency 25474.547137                       # average overall miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency 24472.695166                       # average overall mshr miss latency
+system.cpu4.l1c.overall_accesses                68803                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_avg_miss_latency 25595.562806                       # average overall miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency 24593.744456                       # average overall mshr miss latency
 system.cpu4.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu4.l1c.overall_hits                     8407                       # number of overall hits
-system.cpu4.l1c.overall_miss_latency       1544012302                       # number of overall miss cycles
-system.cpu4.l1c.overall_miss_rate            0.878189                       # miss rate for overall accesses
-system.cpu4.l1c.overall_misses                  60610                       # number of overall misses
+system.cpu4.l1c.overall_hits                     8379                       # number of overall hits
+system.cpu4.l1c.overall_miss_latency       1546586287                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_rate            0.878218                       # miss rate for overall accesses
+system.cpu4.l1c.overall_misses                  60424                       # number of overall misses
 system.cpu4.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu4.l1c.overall_mshr_miss_latency   1483290054                       # number of overall MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_rate       0.878189                       # mshr miss rate for overall accesses
-system.cpu4.l1c.overall_mshr_misses             60610                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_uncacheable_latency    754550717                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_miss_latency   1486052415                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_rate       0.878218                       # mshr miss rate for overall accesses
+system.cpu4.l1c.overall_mshr_misses             60424                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_uncacheable_latency    751261336                       # number of overall MSHR uncacheable cycles
 system.cpu4.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu4.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu4.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -391,75 +391,75 @@ system.cpu4.l1c.prefetcher.num_hwpf_issued            0                       #
 system.cpu4.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu4.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu4.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu4.l1c.replacements                    27817                       # number of replacements
-system.cpu4.l1c.sampled_refs                    28144                       # Sample count of references to valid blocks.
+system.cpu4.l1c.replacements                    27694                       # number of replacements
+system.cpu4.l1c.sampled_refs                    28053                       # Sample count of references to valid blocks.
 system.cpu4.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu4.l1c.tagsinuse                  346.514694                       # Cycle average of tags in use
-system.cpu4.l1c.total_refs                      11420                       # Total number of references to valid blocks.
+system.cpu4.l1c.tagsinuse                  346.576888                       # Cycle average of tags in use
+system.cpu4.l1c.total_refs                      11516                       # Total number of references to valid blocks.
 system.cpu4.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.writebacks                      10757                       # number of writebacks
+system.cpu4.l1c.writebacks                      10817                       # number of writebacks
 system.cpu4.num_copies                              0                       # number of copy accesses completed
-system.cpu4.num_reads                           99082                       # number of read accesses completed
-system.cpu4.num_writes                          53389                       # number of write accesses completed
-system.cpu5.l1c.ReadReq_accesses                44738                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.ReadReq_avg_miss_latency 23469.170166                       # average ReadReq miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 22467.276917                       # average ReadReq mshr miss latency
+system.cpu4.num_reads                           98799                       # number of read accesses completed
+system.cpu4.num_writes                          53431                       # number of write accesses completed
+system.cpu5.l1c.ReadReq_accesses                44885                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_avg_miss_latency 23518.665421                       # average ReadReq miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 22516.852786                       # average ReadReq mshr miss latency
 system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.ReadReq_hits                     7633                       # number of ReadReq hits
-system.cpu5.l1c.ReadReq_miss_latency        870823559                       # number of ReadReq miss cycles
-system.cpu5.l1c.ReadReq_miss_rate            0.829384                       # miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_misses                  37105                       # number of ReadReq misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency    833648310                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate       0.829384                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.ReadReq_mshr_misses             37105                       # number of ReadReq MSHR misses
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency    475305988                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_accesses               24369                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_avg_miss_latency 28200.397532                       # average WriteReq miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 27198.611178                       # average WriteReq mshr miss latency
+system.cpu5.l1c.ReadReq_hits                     7701                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_miss_latency        874518055                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_rate            0.828428                       # miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_misses                  37184                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency    837266654                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate       0.828428                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.ReadReq_mshr_misses             37184                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency    472519207                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_accesses               24343                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_avg_miss_latency 28185.897903                       # average WriteReq miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 27184.111666                       # average WriteReq mshr miss latency
 system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_hits                     947                       # number of WriteReq hits
-system.cpu5.l1c.WriteReq_miss_latency       660509711                       # number of WriteReq miss cycles
-system.cpu5.l1c.WriteReq_miss_rate           0.961139                       # miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_misses                 23422                       # number of WriteReq misses
-system.cpu5.l1c.WriteReq_mshr_miss_latency    637045871                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_rate      0.961139                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.WriteReq_mshr_misses            23422                       # number of WriteReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency    288432414                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.avg_blocked_cycles_no_mshrs  2288.248839                       # average number of cycles each access was blocked
+system.cpu5.l1c.WriteReq_hits                     934                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_miss_latency       659803684                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_rate           0.961632                       # miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_misses                 23409                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_mshr_miss_latency    636352870                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_rate      0.961632                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.WriteReq_mshr_misses            23409                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency    285116672                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.avg_blocked_cycles_no_mshrs  2289.516557                       # average number of cycles each access was blocked
 system.cpu5.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu5.l1c.avg_refs                     0.414858                       # Average number of references to valid blocks.
-system.cpu5.l1c.blocked_no_mshrs                69575                       # number of cycles access was blocked
+system.cpu5.l1c.avg_refs                     0.417638                       # Average number of references to valid blocks.
+system.cpu5.l1c.blocked_no_mshrs                69638                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
-system.cpu5.l1c.blocked_cycles_no_mshrs     159204913                       # number of cycles access was blocked
+system.cpu5.l1c.blocked_cycles_no_mshrs     159437354                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.demand_accesses                 69107                       # number of demand (read+write) accesses
-system.cpu5.l1c.demand_avg_miss_latency  25300.002809                       # average overall miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency 24298.150924                       # average overall mshr miss latency
-system.cpu5.l1c.demand_hits                      8580                       # number of demand (read+write) hits
-system.cpu5.l1c.demand_miss_latency        1531333270                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.demand_miss_rate             0.875845                       # miss rate for demand accesses
-system.cpu5.l1c.demand_misses                   60527                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_accesses                 69228                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_avg_miss_latency  25321.765534                       # average overall miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency 24319.963098                       # average overall mshr miss latency
+system.cpu5.l1c.demand_hits                      8635                       # number of demand (read+write) hits
+system.cpu5.l1c.demand_miss_latency        1534321739                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_rate             0.875267                       # miss rate for demand accesses
+system.cpu5.l1c.demand_misses                   60593                       # number of demand (read+write) misses
 system.cpu5.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu5.l1c.demand_mshr_miss_latency   1470694181                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_rate        0.875845                       # mshr miss rate for demand accesses
-system.cpu5.l1c.demand_mshr_misses              60527                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_miss_latency   1473619524                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_rate        0.875267                       # mshr miss rate for demand accesses
+system.cpu5.l1c.demand_mshr_misses              60593                       # number of demand (read+write) MSHR misses
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu5.l1c.overall_accesses                69107                       # number of overall (read+write) accesses
-system.cpu5.l1c.overall_avg_miss_latency 25300.002809                       # average overall miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency 24298.150924                       # average overall mshr miss latency
+system.cpu5.l1c.overall_accesses                69228                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_avg_miss_latency 25321.765534                       # average overall miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency 24319.963098                       # average overall mshr miss latency
 system.cpu5.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu5.l1c.overall_hits                     8580                       # number of overall hits
-system.cpu5.l1c.overall_miss_latency       1531333270                       # number of overall miss cycles
-system.cpu5.l1c.overall_miss_rate            0.875845                       # miss rate for overall accesses
-system.cpu5.l1c.overall_misses                  60527                       # number of overall misses
+system.cpu5.l1c.overall_hits                     8635                       # number of overall hits
+system.cpu5.l1c.overall_miss_latency       1534321739                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_rate            0.875267                       # miss rate for overall accesses
+system.cpu5.l1c.overall_misses                  60593                       # number of overall misses
 system.cpu5.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu5.l1c.overall_mshr_miss_latency   1470694181                       # number of overall MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_rate       0.875845                       # mshr miss rate for overall accesses
-system.cpu5.l1c.overall_mshr_misses             60527                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_uncacheable_latency    763738402                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_miss_latency   1473619524                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_rate       0.875267                       # mshr miss rate for overall accesses
+system.cpu5.l1c.overall_mshr_misses             60593                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_uncacheable_latency    757635879                       # number of overall MSHR uncacheable cycles
 system.cpu5.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu5.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu5.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -470,75 +470,75 @@ system.cpu5.l1c.prefetcher.num_hwpf_issued            0                       #
 system.cpu5.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu5.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu5.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu5.l1c.replacements                    27804                       # number of replacements
-system.cpu5.l1c.sampled_refs                    28147                       # Sample count of references to valid blocks.
+system.cpu5.l1c.replacements                    27880                       # number of replacements
+system.cpu5.l1c.sampled_refs                    28223                       # Sample count of references to valid blocks.
 system.cpu5.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu5.l1c.tagsinuse                  347.082479                       # Cycle average of tags in use
-system.cpu5.l1c.total_refs                      11677                       # Total number of references to valid blocks.
+system.cpu5.l1c.tagsinuse                  348.509117                       # Cycle average of tags in use
+system.cpu5.l1c.total_refs                      11787                       # Total number of references to valid blocks.
 system.cpu5.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.writebacks                      11050                       # number of writebacks
+system.cpu5.l1c.writebacks                      11039                       # number of writebacks
 system.cpu5.num_copies                              0                       # number of copy accesses completed
-system.cpu5.num_reads                           99598                       # number of read accesses completed
-system.cpu5.num_writes                          53839                       # number of write accesses completed
-system.cpu6.l1c.ReadReq_accesses                44535                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.ReadReq_avg_miss_latency 23610.393004                       # average ReadReq miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 22608.500040                       # average ReadReq mshr miss latency
+system.cpu5.num_reads                          100000                       # number of read accesses completed
+system.cpu5.num_writes                          53951                       # number of write accesses completed
+system.cpu6.l1c.ReadReq_accesses                44452                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_avg_miss_latency 23599.078540                       # average ReadReq miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 22597.239994                       # average ReadReq mshr miss latency
 system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.ReadReq_hits                     7370                       # number of ReadReq hits
-system.cpu6.l1c.ReadReq_miss_latency        877480256                       # number of ReadReq miss cycles
-system.cpu6.l1c.ReadReq_miss_rate            0.834512                       # miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_misses                  37165                       # number of ReadReq misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency    840244904                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate       0.834512                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.ReadReq_mshr_misses             37165                       # number of ReadReq MSHR misses
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency    465545805                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_accesses               24347                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_avg_miss_latency 28528.225110                       # average WriteReq miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 27526.396266                       # average WriteReq mshr miss latency
+system.cpu6.l1c.ReadReq_hits                     7401                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_miss_latency        874369459                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_rate            0.833506                       # miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_misses                  37051                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency    837250339                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate       0.833506                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.ReadReq_mshr_misses             37051                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency    468398074                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_accesses               24180                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_avg_miss_latency 28689.725113                       # average WriteReq miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 27687.897435                       # average WriteReq mshr miss latency
 system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_hits                     994                       # number of WriteReq hits
-system.cpu6.l1c.WriteReq_miss_latency       666219641                       # number of WriteReq miss cycles
-system.cpu6.l1c.WriteReq_miss_rate           0.959174                       # miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_misses                 23353                       # number of WriteReq misses
-system.cpu6.l1c.WriteReq_mshr_miss_latency    642823932                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_rate      0.959174                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.WriteReq_mshr_misses            23353                       # number of WriteReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency    284792998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.avg_blocked_cycles_no_mshrs  2301.549644                       # average number of cycles each access was blocked
+system.cpu6.l1c.WriteReq_hits                     985                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_miss_latency       665458174                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_rate           0.959264                       # miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_misses                 23195                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_mshr_miss_latency    642220781                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_rate      0.959264                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.WriteReq_mshr_misses            23195                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency    283288804                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.avg_blocked_cycles_no_mshrs  2306.135407                       # average number of cycles each access was blocked
 system.cpu6.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu6.l1c.avg_refs                     0.409026                       # Average number of references to valid blocks.
-system.cpu6.l1c.blocked_no_mshrs                69474                       # number of cycles access was blocked
+system.cpu6.l1c.avg_refs                     0.410866                       # Average number of references to valid blocks.
+system.cpu6.l1c.blocked_no_mshrs                69302                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
-system.cpu6.l1c.blocked_cycles_no_mshrs     159897860                       # number of cycles access was blocked
+system.cpu6.l1c.blocked_cycles_no_mshrs     159819796                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.demand_accesses                 68882                       # number of demand (read+write) accesses
-system.cpu6.l1c.demand_avg_miss_latency  25508.111587                       # average overall miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency 24506.243366                       # average overall mshr miss latency
-system.cpu6.l1c.demand_hits                      8364                       # number of demand (read+write) hits
-system.cpu6.l1c.demand_miss_latency        1543699897                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.demand_miss_rate             0.878575                       # miss rate for demand accesses
-system.cpu6.l1c.demand_misses                   60518                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_accesses                 68632                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_avg_miss_latency  25559.001975                       # average overall miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency 24557.167613                       # average overall mshr miss latency
+system.cpu6.l1c.demand_hits                      8386                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_miss_latency        1539827633                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_rate             0.877812                       # miss rate for demand accesses
+system.cpu6.l1c.demand_misses                   60246                       # number of demand (read+write) misses
 system.cpu6.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu6.l1c.demand_mshr_miss_latency   1483068836                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_rate        0.878575                       # mshr miss rate for demand accesses
-system.cpu6.l1c.demand_mshr_misses              60518                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_miss_latency   1479471120                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_rate        0.877812                       # mshr miss rate for demand accesses
+system.cpu6.l1c.demand_mshr_misses              60246                       # number of demand (read+write) MSHR misses
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu6.l1c.overall_accesses                68882                       # number of overall (read+write) accesses
-system.cpu6.l1c.overall_avg_miss_latency 25508.111587                       # average overall miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency 24506.243366                       # average overall mshr miss latency
+system.cpu6.l1c.overall_accesses                68632                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_avg_miss_latency 25559.001975                       # average overall miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency 24557.167613                       # average overall mshr miss latency
 system.cpu6.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu6.l1c.overall_hits                     8364                       # number of overall hits
-system.cpu6.l1c.overall_miss_latency       1543699897                       # number of overall miss cycles
-system.cpu6.l1c.overall_miss_rate            0.878575                       # miss rate for overall accesses
-system.cpu6.l1c.overall_misses                  60518                       # number of overall misses
+system.cpu6.l1c.overall_hits                     8386                       # number of overall hits
+system.cpu6.l1c.overall_miss_latency       1539827633                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_rate            0.877812                       # miss rate for overall accesses
+system.cpu6.l1c.overall_misses                  60246                       # number of overall misses
 system.cpu6.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu6.l1c.overall_mshr_miss_latency   1483068836                       # number of overall MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_rate       0.878575                       # mshr miss rate for overall accesses
-system.cpu6.l1c.overall_mshr_misses             60518                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_uncacheable_latency    750338803                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_miss_latency   1479471120                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_rate       0.877812                       # mshr miss rate for overall accesses
+system.cpu6.l1c.overall_mshr_misses             60246                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_uncacheable_latency    751686878                       # number of overall MSHR uncacheable cycles
 system.cpu6.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu6.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu6.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -549,75 +549,75 @@ system.cpu6.l1c.prefetcher.num_hwpf_issued            0                       #
 system.cpu6.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu6.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu6.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu6.l1c.replacements                    27670                       # number of replacements
-system.cpu6.l1c.sampled_refs                    28030                       # Sample count of references to valid blocks.
+system.cpu6.l1c.replacements                    27468                       # number of replacements
+system.cpu6.l1c.sampled_refs                    27829                       # Sample count of references to valid blocks.
 system.cpu6.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu6.l1c.tagsinuse                  347.050394                       # Cycle average of tags in use
-system.cpu6.l1c.total_refs                      11465                       # Total number of references to valid blocks.
+system.cpu6.l1c.tagsinuse                  345.752626                       # Cycle average of tags in use
+system.cpu6.l1c.total_refs                      11434                       # Total number of references to valid blocks.
 system.cpu6.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.writebacks                      10922                       # number of writebacks
+system.cpu6.l1c.writebacks                      10779                       # number of writebacks
 system.cpu6.num_copies                              0                       # number of copy accesses completed
-system.cpu6.num_reads                           98586                       # number of read accesses completed
-system.cpu6.num_writes                          53530                       # number of write accesses completed
-system.cpu7.l1c.ReadReq_accesses                45060                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.ReadReq_avg_miss_latency 23572.973322                       # average ReadReq miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 22571.079447                       # average ReadReq mshr miss latency
+system.cpu6.num_reads                           98631                       # number of read accesses completed
+system.cpu6.num_writes                          53473                       # number of write accesses completed
+system.cpu7.l1c.ReadReq_accesses                45026                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_avg_miss_latency 23566.694007                       # average ReadReq miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 22564.854082                       # average ReadReq mshr miss latency
 system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.ReadReq_hits                     7689                       # number of ReadReq hits
-system.cpu7.l1c.ReadReq_miss_latency        880945586                       # number of ReadReq miss cycles
-system.cpu7.l1c.ReadReq_miss_rate            0.829361                       # miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_misses                  37371                       # number of ReadReq misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency    843503810                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate       0.829361                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.ReadReq_mshr_misses             37371                       # number of ReadReq MSHR misses
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency    464745135                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_accesses               24261                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_avg_miss_latency 28282.937385                       # average WriteReq miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 27281.151106                       # average WriteReq mshr miss latency
+system.cpu7.l1c.ReadReq_hits                     7731                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_miss_latency        878919853                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_rate            0.828299                       # miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_misses                  37295                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency    841556233                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate       0.828299                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_misses             37295                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency    464511482                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_accesses               24312                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_avg_miss_latency 28334.071468                       # average WriteReq miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 27332.156470                       # average WriteReq mshr miss latency
 system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_hits                     880                       # number of WriteReq hits
-system.cpu7.l1c.WriteReq_miss_latency       661283359                       # number of WriteReq miss cycles
-system.cpu7.l1c.WriteReq_miss_rate           0.963728                       # miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_misses                 23381                       # number of WriteReq misses
-system.cpu7.l1c.WriteReq_mshr_miss_latency    637860594                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_rate      0.963728                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.WriteReq_mshr_misses            23381                       # number of WriteReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency    291455406                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.avg_blocked_cycles_no_mshrs  2290.612942                       # average number of cycles each access was blocked
+system.cpu7.l1c.WriteReq_hits                     889                       # number of WriteReq hits
+system.cpu7.l1c.WriteReq_miss_latency       663668956                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_rate           0.963434                       # miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_misses                 23423                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_mshr_miss_latency    640201101                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_rate      0.963434                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_misses            23423                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency    287294687                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.avg_blocked_cycles_no_mshrs  2290.551288                       # average number of cycles each access was blocked
 system.cpu7.l1c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.cpu7.l1c.avg_refs                     0.415259                       # Average number of references to valid blocks.
-system.cpu7.l1c.blocked_no_mshrs                69540                       # number of cycles access was blocked
+system.cpu7.l1c.avg_refs                     0.413973                       # Average number of references to valid blocks.
+system.cpu7.l1c.blocked_no_mshrs                69548                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_no_targets                  0                       # number of cycles access was blocked
-system.cpu7.l1c.blocked_cycles_no_mshrs     159289224                       # number of cycles access was blocked
+system.cpu7.l1c.blocked_cycles_no_mshrs     159303261                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles_no_targets            0                       # number of cycles access was blocked
 system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.demand_accesses                 69321                       # number of demand (read+write) accesses
-system.cpu7.l1c.demand_avg_miss_latency  25385.648950                       # average overall miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency 24383.796484                       # average overall mshr miss latency
-system.cpu7.l1c.demand_hits                      8569                       # number of demand (read+write) hits
-system.cpu7.l1c.demand_miss_latency        1542228945                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.demand_miss_rate             0.876387                       # miss rate for demand accesses
-system.cpu7.l1c.demand_misses                   60752                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_accesses                 69338                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_avg_miss_latency  25405.790853                       # average overall miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency 24403.921967                       # average overall mshr miss latency
+system.cpu7.l1c.demand_hits                      8620                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_miss_latency        1542588809                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_rate             0.875681                       # miss rate for demand accesses
+system.cpu7.l1c.demand_misses                   60718                       # number of demand (read+write) misses
 system.cpu7.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu7.l1c.demand_mshr_miss_latency   1481364404                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_rate        0.876387                       # mshr miss rate for demand accesses
-system.cpu7.l1c.demand_mshr_misses              60752                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_miss_latency   1481757334                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_rate        0.875681                       # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_misses              60718                       # number of demand (read+write) MSHR misses
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
 system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
-system.cpu7.l1c.overall_accesses                69321                       # number of overall (read+write) accesses
-system.cpu7.l1c.overall_avg_miss_latency 25385.648950                       # average overall miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency 24383.796484                       # average overall mshr miss latency
+system.cpu7.l1c.overall_accesses                69338                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_avg_miss_latency 25405.790853                       # average overall miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency 24403.921967                       # average overall mshr miss latency
 system.cpu7.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu7.l1c.overall_hits                     8569                       # number of overall hits
-system.cpu7.l1c.overall_miss_latency       1542228945                       # number of overall miss cycles
-system.cpu7.l1c.overall_miss_rate            0.876387                       # miss rate for overall accesses
-system.cpu7.l1c.overall_misses                  60752                       # number of overall misses
+system.cpu7.l1c.overall_hits                     8620                       # number of overall hits
+system.cpu7.l1c.overall_miss_latency       1542588809                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_rate            0.875681                       # miss rate for overall accesses
+system.cpu7.l1c.overall_misses                  60718                       # number of overall misses
 system.cpu7.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu7.l1c.overall_mshr_miss_latency   1481364404                       # number of overall MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_rate       0.876387                       # mshr miss rate for overall accesses
-system.cpu7.l1c.overall_mshr_misses             60752                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_uncacheable_latency    756200541                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_miss_latency   1481757334                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_rate       0.875681                       # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_misses             60718                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_uncacheable_latency    751806169                       # number of overall MSHR uncacheable cycles
 system.cpu7.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.cpu7.l1c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.cpu7.l1c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -628,91 +628,91 @@ system.cpu7.l1c.prefetcher.num_hwpf_issued            0                       #
 system.cpu7.l1c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.cpu7.l1c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.cpu7.l1c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu7.l1c.replacements                    27776                       # number of replacements
-system.cpu7.l1c.sampled_refs                    28127                       # Sample count of references to valid blocks.
+system.cpu7.l1c.replacements                    27895                       # number of replacements
+system.cpu7.l1c.sampled_refs                    28241                       # Sample count of references to valid blocks.
 system.cpu7.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
-system.cpu7.l1c.tagsinuse                  346.455947                       # Cycle average of tags in use
-system.cpu7.l1c.total_refs                      11680                       # Total number of references to valid blocks.
+system.cpu7.l1c.tagsinuse                  347.065724                       # Cycle average of tags in use
+system.cpu7.l1c.total_refs                      11691                       # Total number of references to valid blocks.
 system.cpu7.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.writebacks                      10920                       # number of writebacks
+system.cpu7.l1c.writebacks                      10935                       # number of writebacks
 system.cpu7.num_copies                              0                       # number of copy accesses completed
-system.cpu7.num_reads                          100000                       # number of read accesses completed
-system.cpu7.num_writes                          53888                       # number of write accesses completed
-system.l2c.ReadExReq_accesses                   74532                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_avg_miss_latency    20118.794759                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 10011.874108                       # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_miss_latency          1499494011                       # number of ReadExReq miss cycles
+system.cpu7.num_reads                           99923                       # number of read accesses completed
+system.cpu7.num_writes                          53956                       # number of write accesses completed
+system.l2c.ReadExReq_accesses                   74537                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_avg_miss_latency    20115.263386                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency 10011.845848                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_miss_latency          1499331387                       # number of ReadExReq miss cycles
 system.l2c.ReadExReq_miss_rate                      1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_misses                     74532                       # number of ReadExReq misses
-system.l2c.ReadExReq_mshr_hits                    478                       # number of ReadExReq MSHR hits
-system.l2c.ReadExReq_mshr_miss_latency      746205001                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_misses                     74537                       # number of ReadExReq misses
+system.l2c.ReadExReq_mshr_hits                    461                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_miss_latency      746252954                       # number of ReadExReq MSHR miss cycles
 system.l2c.ReadExReq_mshr_miss_rate                 1                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_misses                74532                       # number of ReadExReq MSHR misses
-system.l2c.ReadReq_accesses                    137656                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_avg_miss_latency      20204.255734                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency 10011.528670                       # average ReadReq mshr miss latency
+system.l2c.ReadExReq_mshr_misses                74537                       # number of ReadExReq MSHR misses
+system.l2c.ReadReq_accesses                    137370                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_avg_miss_latency      20204.368124                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency 10010.792670                       # average ReadReq mshr miss latency
 system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.ReadReq_hits                         62664                       # number of ReadReq hits
-system.l2c.ReadReq_miss_latency            1515157546                       # number of ReadReq miss cycles
-system.l2c.ReadReq_miss_rate                 0.544778                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_misses                       74992                       # number of ReadReq misses
-system.l2c.ReadReq_mshr_hits                      876                       # number of ReadReq MSHR hits
-system.l2c.ReadReq_mshr_miss_latency        750784558                       # number of ReadReq MSHR miss cycles
-system.l2c.ReadReq_mshr_miss_rate            0.544778                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_misses                  74992                       # number of ReadReq MSHR misses
-system.l2c.ReadReq_mshr_uncacheable_latency    792812009                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.UpgradeReq_accesses                  18194                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_avg_miss_latency   10193.188359                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 10011.231065                       # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_miss_latency          185454869                       # number of UpgradeReq miss cycles
+system.l2c.ReadReq_hits                         62417                       # number of ReadReq hits
+system.l2c.ReadReq_miss_latency            1514378004                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_rate                 0.545629                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_misses                       74953                       # number of ReadReq misses
+system.l2c.ReadReq_mshr_hits                      884                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_miss_latency        750338943                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate            0.545629                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_misses                  74953                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_uncacheable_latency    791888060                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.UpgradeReq_accesses                  18325                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_avg_miss_latency   10129.887094                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency 10011.324093                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_miss_latency          185630181                       # number of UpgradeReq miss cycles
 system.l2c.UpgradeReq_miss_rate                     1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_misses                    18194                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_mshr_hits                    33                       # number of UpgradeReq MSHR hits
-system.l2c.UpgradeReq_mshr_miss_latency     182144338                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_misses                    18325                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_mshr_hits                    24                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_miss_latency     183457514                       # number of UpgradeReq MSHR miss cycles
 system.l2c.UpgradeReq_mshr_miss_rate                1                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_misses               18194                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses               18325                       # number of UpgradeReq MSHR misses
 system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.WriteReq_mshr_uncacheable_latency    429976462                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.Writeback_accesses                   86637                       # number of Writeback accesses(hits+misses)
+system.l2c.WriteReq_mshr_uncacheable_latency    429360910                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.Writeback_accesses                   86629                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_miss_rate                      1                       # miss rate for Writeback accesses
-system.l2c.Writeback_misses                     86637                       # number of Writeback misses
+system.l2c.Writeback_misses                     86629                       # number of Writeback misses
 system.l2c.Writeback_mshr_miss_rate                 1                       # mshr miss rate for Writeback accesses
-system.l2c.Writeback_mshr_misses                86637                       # number of Writeback MSHR misses
+system.l2c.Writeback_mshr_misses                86629                       # number of Writeback MSHR misses
 system.l2c.avg_blocked_cycles_no_mshrs    2919.500000                       # average number of cycles each access was blocked
 system.l2c.avg_blocked_cycles_no_targets <err: div-0>                       # average number of cycles each access was blocked
-system.l2c.avg_refs                          3.347484                       # Average number of references to valid blocks.
+system.l2c.avg_refs                          3.325063                       # Average number of references to valid blocks.
 system.l2c.blocked_no_mshrs                         6                       # number of cycles access was blocked
 system.l2c.blocked_no_targets                       0                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_mshrs              17517                       # number of cycles access was blocked
 system.l2c.blocked_cycles_no_targets                0                       # number of cycles access was blocked
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.demand_accesses                     212188                       # number of demand (read+write) accesses
-system.l2c.demand_avg_miss_latency       20161.656704                       # average overall miss latency
-system.l2c.demand_avg_mshr_miss_latency  10011.700857                       # average overall mshr miss latency
-system.l2c.demand_hits                          62664                       # number of demand (read+write) hits
-system.l2c.demand_miss_latency             3014651557                       # number of demand (read+write) miss cycles
-system.l2c.demand_miss_rate                  0.704677                       # miss rate for demand accesses
-system.l2c.demand_misses                       149524                       # number of demand (read+write) misses
-system.l2c.demand_mshr_hits                      1354                       # number of demand (read+write) MSHR hits
-system.l2c.demand_mshr_miss_latency        1496989559                       # number of demand (read+write) MSHR miss cycles
-system.l2c.demand_mshr_miss_rate             0.704677                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_misses                  149524                       # number of demand (read+write) MSHR misses
+system.l2c.demand_accesses                     211907                       # number of demand (read+write) accesses
+system.l2c.demand_avg_miss_latency       20159.939735                       # average overall miss latency
+system.l2c.demand_avg_mshr_miss_latency  10011.317794                       # average overall mshr miss latency
+system.l2c.demand_hits                          62417                       # number of demand (read+write) hits
+system.l2c.demand_miss_latency             3013709391                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_rate                  0.705451                       # miss rate for demand accesses
+system.l2c.demand_misses                       149490                       # number of demand (read+write) misses
+system.l2c.demand_mshr_hits                      1345                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_miss_latency        1496591897                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_rate             0.705451                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_misses                  149490                       # number of demand (read+write) MSHR misses
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.l2c.overall_accesses                    212188                       # number of overall (read+write) accesses
-system.l2c.overall_avg_miss_latency      20161.656704                       # average overall miss latency
-system.l2c.overall_avg_mshr_miss_latency 10011.700857                       # average overall mshr miss latency
+system.l2c.overall_accesses                    211907                       # number of overall (read+write) accesses
+system.l2c.overall_avg_miss_latency      20159.939735                       # average overall miss latency
+system.l2c.overall_avg_mshr_miss_latency 10011.317794                       # average overall mshr miss latency
 system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.overall_hits                         62664                       # number of overall hits
-system.l2c.overall_miss_latency            3014651557                       # number of overall miss cycles
-system.l2c.overall_miss_rate                 0.704677                       # miss rate for overall accesses
-system.l2c.overall_misses                      149524                       # number of overall misses
-system.l2c.overall_mshr_hits                     1354                       # number of overall MSHR hits
-system.l2c.overall_mshr_miss_latency       1496989559                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_miss_rate            0.704677                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_misses                 149524                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_latency   1222788471                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_hits                         62417                       # number of overall hits
+system.l2c.overall_miss_latency            3013709391                       # number of overall miss cycles
+system.l2c.overall_miss_rate                 0.705451                       # miss rate for overall accesses
+system.l2c.overall_misses                      149490                       # number of overall misses
+system.l2c.overall_mshr_hits                     1345                       # number of overall MSHR hits
+system.l2c.overall_mshr_miss_latency       1496591897                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_rate            0.705451                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_misses                 149490                       # number of overall MSHR misses
+system.l2c.overall_mshr_uncacheable_latency   1221248970                       # number of overall MSHR uncacheable cycles
 system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
 system.l2c.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
 system.l2c.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
@@ -723,11 +723,11 @@ system.l2c.prefetcher.num_hwpf_issued               0                       # nu
 system.l2c.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
 system.l2c.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
 system.l2c.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.l2c.replacements                         30644                       # number of replacements
-system.l2c.sampled_refs                         31095                       # Sample count of references to valid blocks.
+system.l2c.replacements                         30719                       # number of replacements
+system.l2c.sampled_refs                         31154                       # Sample count of references to valid blocks.
 system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.tagsinuse                       460.797785                       # Cycle average of tags in use
-system.l2c.total_refs                          104090                       # Total number of references to valid blocks.
+system.l2c.tagsinuse                       460.327226                       # Cycle average of tags in use
+system.l2c.total_refs                          103589                       # Total number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
 system.l2c.writebacks                               0                       # number of writebacks
 
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
index 9486d3e24..6aaad2045 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stderr
@@ -55,20 +55,20 @@ system.cpu1: completed 70000 read accesses @114429712
 system.cpu0: completed 70000 read accesses @114626666
 system.cpu4: completed 70000 read accesses @115046863
 system.cpu6: completed 70000 read accesses @115625699
-system.cpu7: completed 80000 read accesses @130041792
-system.cpu5: completed 80000 read accesses @130054396
-system.cpu1: completed 80000 read accesses @130640538
-system.cpu3: completed 80000 read accesses @130746631
-system.cpu0: completed 80000 read accesses @130757460
-system.cpu2: completed 80000 read accesses @130848004
-system.cpu4: completed 80000 read accesses @131798404
-system.cpu6: completed 80000 read accesses @132427801
-system.cpu7: completed 90000 read accesses @146399168
-system.cpu3: completed 90000 read accesses @146528404
-system.cpu0: completed 90000 read accesses @146893614
-system.cpu5: completed 90000 read accesses @147004410
-system.cpu1: completed 90000 read accesses @147082543
-system.cpu2: completed 90000 read accesses @147344874
-system.cpu4: completed 90000 read accesses @148040578
-system.cpu6: completed 90000 read accesses @149090244
-system.cpu7: completed 100000 read accesses @163028791
+system.cpu7: completed 80000 read accesses @130114471
+system.cpu5: completed 80000 read accesses @130239115
+system.cpu3: completed 80000 read accesses @130679996
+system.cpu1: completed 80000 read accesses @130860729
+system.cpu0: completed 80000 read accesses @131170286
+system.cpu2: completed 80000 read accesses @131219347
+system.cpu4: completed 80000 read accesses @131694972
+system.cpu6: completed 80000 read accesses @132127278
+system.cpu7: completed 90000 read accesses @146355152
+system.cpu5: completed 90000 read accesses @146631518
+system.cpu3: completed 90000 read accesses @146856424
+system.cpu1: completed 90000 read accesses @147217275
+system.cpu0: completed 90000 read accesses @147658368
+system.cpu2: completed 90000 read accesses @147775118
+system.cpu4: completed 90000 read accesses @148157312
+system.cpu6: completed 90000 read accesses @148500053
+system.cpu5: completed 100000 read accesses @162969030
diff --git a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
index bb2428fbe..82895303c 100644
--- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
+++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stdout
@@ -5,9 +5,9 @@ The Regents of The University of Michigan
 All Rights Reserved
 
 
-M5 compiled Aug 12 2007 00:26:55
-M5 started Sun Aug 12 12:13:31 2007
-M5 executing on zeep
+M5 compiled Nov 13 2007 20:22:15
+M5 started Tue Nov 13 20:22:26 2007
+M5 executing on vm1
 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest tests/run.py quick/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
-Exiting @ tick 163028791 because maximum number of loads reached
+Exiting @ tick 162969030 because maximum number of loads reached
diff --git a/util/make_release.py b/util/make_release.py
index 916b8a0ba..5ed23e594 100755
--- a/util/make_release.py
+++ b/util/make_release.py
@@ -131,7 +131,6 @@ rmtree(release_dir, 'src/arch/x86')
 #rmtree(release_dir, 'src/mem/cache/prefetch/stride_*.hh')
 rmtree(release_dir, 'configs/fullsys')
 rmtree(release_dir, 'configs/test')
-rmtree(release_dir, 'configs/splash2')
 rmtree(release_dir, 'tests/long/*/ref')
 rmtree(release_dir, 'tests/old')
 rmtree(release_dir, 'tests/quick/00.hello/ref/x86')