diff options
author | Nathan Binkert <nate@binkert.org> | 2010-04-15 16:24:12 -0700 |
---|---|---|
committer | Nathan Binkert <nate@binkert.org> | 2010-04-15 16:24:12 -0700 |
commit | e99828b06a1b694b7aca09682ae2b1be9089af88 (patch) | |
tree | e106d16b98b45695ffd993e2cd6684919723dc66 | |
parent | f7e6f19adabd0ce7e35cea8b5c3b070e2cd26c38 (diff) | |
download | gem5-e99828b06a1b694b7aca09682ae2b1be9089af88.tar.xz |
tick: rename Clock namespace to SimClock
-rw-r--r-- | src/arch/alpha/freebsd/system.cc | 2 | ||||
-rw-r--r-- | src/arch/alpha/linux/system.cc | 2 | ||||
-rw-r--r-- | src/arch/alpha/tru64/process.cc | 2 | ||||
-rw-r--r-- | src/arch/mips/linux/system.cc | 2 | ||||
-rw-r--r-- | src/cpu/base.hh | 2 | ||||
-rw-r--r-- | src/dev/alpha/tsunami_io.cc | 2 | ||||
-rw-r--r-- | src/dev/etherdump.cc | 4 | ||||
-rw-r--r-- | src/dev/i8254xGBe.cc | 4 | ||||
-rw-r--r-- | src/dev/i8254xGBe.hh | 2 | ||||
-rw-r--r-- | src/dev/intel_8254_timer.cc | 2 | ||||
-rw-r--r-- | src/dev/mc146818.cc | 2 | ||||
-rw-r--r-- | src/dev/mc146818.hh | 2 | ||||
-rwxr-xr-x | src/dev/mips/malta_io.cc | 2 | ||||
-rw-r--r-- | src/dev/uart8250.cc | 4 | ||||
-rw-r--r-- | src/mem/tport.cc | 2 | ||||
-rw-r--r-- | src/sim/core.cc | 6 | ||||
-rw-r--r-- | src/sim/core.hh | 4 | ||||
-rw-r--r-- | src/sim/pseudo_inst.cc | 25 | ||||
-rw-r--r-- | src/sim/stat_control.cc | 2 | ||||
-rw-r--r-- | src/sim/syscall_emul.hh | 4 |
20 files changed, 39 insertions, 38 deletions
diff --git a/src/arch/alpha/freebsd/system.cc b/src/arch/alpha/freebsd/system.cc index e541b260c..ac7a92ed3 100644 --- a/src/arch/alpha/freebsd/system.cc +++ b/src/arch/alpha/freebsd/system.cc @@ -77,7 +77,7 @@ FreebsdAlphaSystem::doCalibrateClocks(ThreadContext *tc) ppc_vaddr = (Addr)tc->readIntReg(17); timer_vaddr = (Addr)tc->readIntReg(18); - virtPort.write(ppc_vaddr, (uint32_t)Clock::Frequency); + virtPort.write(ppc_vaddr, (uint32_t)SimClock::Frequency); virtPort.write(timer_vaddr, (uint32_t)TIMER_FREQUENCY); } diff --git a/src/arch/alpha/linux/system.cc b/src/arch/alpha/linux/system.cc index 1d9332a58..c2af286dd 100644 --- a/src/arch/alpha/linux/system.cc +++ b/src/arch/alpha/linux/system.cc @@ -86,7 +86,7 @@ LinuxAlphaSystem::LinuxAlphaSystem(Params *p) * calculated it by using the PIT, RTC, etc. */ if (kernelSymtab->findAddress("est_cycle_freq", addr)) - virtPort.write(addr, (uint64_t)(Clock::Frequency / + virtPort.write(addr, (uint64_t)(SimClock::Frequency / p->boot_cpu_frequency)); diff --git a/src/arch/alpha/tru64/process.cc b/src/arch/alpha/tru64/process.cc index b039fbe19..824e0413c 100644 --- a/src/arch/alpha/tru64/process.cc +++ b/src/arch/alpha/tru64/process.cc @@ -183,7 +183,7 @@ tableFunc(SyscallDesc *desc, int callnum, LiveProcess *process, TypedBufferArg<Tru64::tbl_sysinfo> elp(bufPtr); const int clk_hz = one_million; - elp->si_user = htog(curTick / (Clock::Frequency / clk_hz)); + elp->si_user = htog(curTick / (SimClock::Frequency / clk_hz)); elp->si_nice = htog(0); elp->si_sys = htog(0); elp->si_idle = htog(0); diff --git a/src/arch/mips/linux/system.cc b/src/arch/mips/linux/system.cc index 295e22a61..ff07f526a 100644 --- a/src/arch/mips/linux/system.cc +++ b/src/arch/mips/linux/system.cc @@ -85,7 +85,7 @@ LinuxMipsSystem::LinuxMipsSystem(Params *p) * calculated it by using the PIT, RTC, etc. */ if (kernelSymtab->findAddress("est_cycle_freq", addr)) - virtPort.write(addr, (uint64_t)(Clock::Frequency / + virtPort.write(addr, (uint64_t)(SimClock::Frequency / p->boot_cpu_frequency)); /** diff --git a/src/cpu/base.hh b/src/cpu/base.hh index b229ddd38..b96a8adb2 100644 --- a/src/cpu/base.hh +++ b/src/cpu/base.hh @@ -98,7 +98,7 @@ class BaseCPU : public MemObject int cpuId() { return _cpuId; } // Tick currentTick; - inline Tick frequency() const { return Clock::Frequency / clock; } + inline Tick frequency() const { return SimClock::Frequency / clock; } inline Tick ticks(int numCycles) const { return clock * numCycles; } inline Tick curCycle() const { return curTick / clock; } inline Tick tickToCycles(Tick val) const { return val / clock; } diff --git a/src/dev/alpha/tsunami_io.cc b/src/dev/alpha/tsunami_io.cc index 8b06f5170..c90f06b5a 100644 --- a/src/dev/alpha/tsunami_io.cc +++ b/src/dev/alpha/tsunami_io.cc @@ -80,7 +80,7 @@ TsunamiIO::TsunamiIO(const Params *p) Tick TsunamiIO::frequency() const { - return Clock::Frequency / params()->frequency; + return SimClock::Frequency / params()->frequency; } Tick diff --git a/src/dev/etherdump.cc b/src/dev/etherdump.cc index c41ce4e1f..9cb15c4e8 100644 --- a/src/dev/etherdump.cc +++ b/src/dev/etherdump.cc @@ -94,8 +94,8 @@ void EtherDump::dumpPacket(EthPacketPtr &packet) { pcap_pkthdr pkthdr; - pkthdr.seconds = curTick / Clock::Int::s; - pkthdr.microseconds = (curTick / Clock::Int::us) % ULL(1000000); + pkthdr.seconds = curTick / SimClock::Int::s; + pkthdr.microseconds = (curTick / SimClock::Int::us) % ULL(1000000); pkthdr.caplen = std::min(packet->length, maxlen); pkthdr.len = packet->length; stream->write(reinterpret_cast<char *>(&pkthdr), sizeof(pkthdr)); diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index ca7e9e67a..2a044ebbe 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -693,7 +693,7 @@ IGbE::postInterrupt(IntTypes t, bool now) regs.icr = regs.icr() | t; - Tick itr_interval = Clock::Int::ns * 256 * regs.itr.interval(); + Tick itr_interval = SimClock::Int::ns * 256 * regs.itr.interval(); DPRINTF(EthernetIntr, "EINT: postInterrupt() curTick: %d itr: %d interval: %d\n", curTick, regs.itr.interval(), itr_interval); @@ -801,7 +801,7 @@ IGbE::chkInterrupt() DPRINTF(Ethernet, "Possibly scheduling interrupt because of imr write\n"); if (!interEvent.scheduled()) { - Tick t = curTick + Clock::Int::ns * 256 * regs.itr.interval(); + Tick t = curTick + SimClock::Int::ns * 256 * regs.itr.interval(); DPRINTF(Ethernet, "Scheduling for %d\n", t); schedule(interEvent, t); } diff --git a/src/dev/i8254xGBe.hh b/src/dev/i8254xGBe.hh index f7f7d9a2a..738b1cf43 100644 --- a/src/dev/i8254xGBe.hh +++ b/src/dev/i8254xGBe.hh @@ -171,7 +171,7 @@ class IGbE : public EtherDevice */ void cpuClearInt(); - Tick intClock() { return Clock::Int::ns * 1024; } + Tick intClock() { return SimClock::Int::ns * 1024; } /** This function is used to restart the clock so it can handle things like * draining and resume in one place. */ diff --git a/src/dev/intel_8254_timer.cc b/src/dev/intel_8254_timer.cc index 770df1c76..9e507b968 100644 --- a/src/dev/intel_8254_timer.cc +++ b/src/dev/intel_8254_timer.cc @@ -255,7 +255,7 @@ Intel8254Timer::Counter::unserialize(const string &base, Checkpoint *cp, Intel8254Timer::Counter::CounterEvent::CounterEvent(Counter* c_ptr) { - interval = (Tick)(Clock::Float::s / 1193180.0); + interval = (Tick)(SimClock::Float::s / 1193180.0); counter = c_ptr; } diff --git a/src/dev/mc146818.cc b/src/dev/mc146818.cc index 2e6ed2a4b..16ed58e46 100644 --- a/src/dev/mc146818.cc +++ b/src/dev/mc146818.cc @@ -271,7 +271,7 @@ void MC146818::RTCTickEvent::process() { DPRINTF(MC146818, "RTC clock tick\n"); - parent->schedule(this, curTick + Clock::Int::s); + parent->schedule(this, curTick + SimClock::Int::s); parent->tickClock(); } diff --git a/src/dev/mc146818.hh b/src/dev/mc146818.hh index e33658903..699785199 100644 --- a/src/dev/mc146818.hh +++ b/src/dev/mc146818.hh @@ -71,7 +71,7 @@ class MC146818 : public EventManager RTCTickEvent(MC146818 * _parent) : parent(_parent) { - parent->schedule(this, curTick + Clock::Int::s); + parent->schedule(this, curTick + SimClock::Int::s); } /** Event process to occur at interrupt*/ diff --git a/src/dev/mips/malta_io.cc b/src/dev/mips/malta_io.cc index 5a738a9b4..a7c68a3bc 100755 --- a/src/dev/mips/malta_io.cc +++ b/src/dev/mips/malta_io.cc @@ -80,7 +80,7 @@ MaltaIO::MaltaIO(const Params *p) Tick MaltaIO::frequency() const { - return Clock::Frequency / params()->frequency; + return SimClock::Frequency / params()->frequency; } Tick diff --git a/src/dev/uart8250.cc b/src/dev/uart8250.cc index f131ab69f..2bbcf2683 100644 --- a/src/dev/uart8250.cc +++ b/src/dev/uart8250.cc @@ -90,7 +90,7 @@ Uart8250::IntrEvent::process() void Uart8250::IntrEvent::scheduleIntr() { - static const Tick interval = 225 * Clock::Int::ns; + static const Tick interval = 225 * SimClock::Int::ns; DPRINTF(Uart, "Scheduling IER interrupt for %#x, at cycle %lld\n", intrBit, curTick + interval); if (!scheduled()) @@ -217,7 +217,7 @@ Uart8250::write(PacketPtr pkt) if (UART_IER_THRI & IER) { DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n"); - if (curTick - lastTxInt > 225 * Clock::Int::ns) { + if (curTick - lastTxInt > 225 * SimClock::Int::ns) { DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n", curTick, lastTxInt); txIntrEvent.process(); diff --git a/src/mem/tport.cc b/src/mem/tport.cc index f937eeb32..e981a7445 100644 --- a/src/mem/tport.cc +++ b/src/mem/tport.cc @@ -108,7 +108,7 @@ void SimpleTimingPort::schedSendTiming(PacketPtr pkt, Tick when) { assert(when > curTick); - assert(when < curTick + Clock::Int::ms); + assert(when < curTick + SimClock::Int::ms); // Nothing is on the list: add it and schedule an event if (transmitList.empty() || when < transmitList.front().tick) { diff --git a/src/sim/core.cc b/src/sim/core.cc index 8342b6740..32642c8a4 100644 --- a/src/sim/core.cc +++ b/src/sim/core.cc @@ -40,7 +40,7 @@ using namespace std; Tick curTick = 0; -namespace Clock { +namespace SimClock { /// The simulated frequency of curTick. (In ticks per second) Tick Frequency; @@ -65,12 +65,12 @@ Tick ns; Tick ps; /* namespace Float */ } -/* namespace Clock */ } +/* namespace SimClock */ } void setClockFrequency(Tick ticksPerSecond) { - using namespace Clock; + using namespace SimClock; Frequency = ticksPerSecond; Float::s = static_cast<double>(Frequency); Float::ms = Float::s / 1.0e3; diff --git a/src/sim/core.hh b/src/sim/core.hh index c1a363689..8be1dd259 100644 --- a/src/sim/core.hh +++ b/src/sim/core.hh @@ -40,7 +40,7 @@ extern Tick curTick; const Tick retryTime = 1000; -namespace Clock { +namespace SimClock { /// The simulated frequency of curTick. extern Tick Frequency; @@ -64,7 +64,7 @@ extern Tick us; extern Tick ns; extern Tick ps; /* namespace Int */ } -/* namespace Clock */ } +/* namespace SimClock */ } void setClockFrequency(Tick ticksPerSecond); diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index cf063818b..7a91bfbd4 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -93,7 +93,7 @@ quiesceNs(ThreadContext *tc, uint64_t ns) EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent(); - Tick resume = curTick + Clock::Int::ns * ns; + Tick resume = curTick + SimClock::Int::ns * ns; mainEventQueue.reschedule(quiesceEvent, resume, true); @@ -128,7 +128,8 @@ quiesceCycles(ThreadContext *tc, uint64_t cycles) uint64_t quiesceTime(ThreadContext *tc) { - return (tc->readLastActivate() - tc->readLastSuspend()) / Clock::Int::ns; + return (tc->readLastActivate() - tc->readLastSuspend()) / + SimClock::Int::ns; } #endif @@ -136,7 +137,7 @@ quiesceTime(ThreadContext *tc) uint64_t rpns(ThreadContext *tc) { - return curTick / Clock::Int::ns; + return curTick / SimClock::Int::ns; } void @@ -151,7 +152,7 @@ wakeCPU(ThreadContext *tc, uint64_t cpuid) void m5exit(ThreadContext *tc, Tick delay) { - Tick when = curTick + delay * Clock::Int::ns; + Tick when = curTick + delay * SimClock::Int::ns; Event *event = new SimLoopExitEvent("m5_exit instruction encountered", 0); mainEventQueue.schedule(event, when); } @@ -229,8 +230,8 @@ resetstats(ThreadContext *tc, Tick delay, Tick period) return; - Tick when = curTick + delay * Clock::Int::ns; - Tick repeat = period * Clock::Int::ns; + Tick when = curTick + delay * SimClock::Int::ns; + Tick repeat = period * SimClock::Int::ns; Stats::StatEvent(false, true, when, repeat); } @@ -242,8 +243,8 @@ dumpstats(ThreadContext *tc, Tick delay, Tick period) return; - Tick when = curTick + delay * Clock::Int::ns; - Tick repeat = period * Clock::Int::ns; + Tick when = curTick + delay * SimClock::Int::ns; + Tick repeat = period * SimClock::Int::ns; Stats::StatEvent(true, false, when, repeat); } @@ -255,8 +256,8 @@ dumpresetstats(ThreadContext *tc, Tick delay, Tick period) return; - Tick when = curTick + delay * Clock::Int::ns; - Tick repeat = period * Clock::Int::ns; + Tick when = curTick + delay * SimClock::Int::ns; + Tick repeat = period * SimClock::Int::ns; Stats::StatEvent(true, true, when, repeat); } @@ -267,8 +268,8 @@ m5checkpoint(ThreadContext *tc, Tick delay, Tick period) if (!tc->getCpuPtr()->params()->do_checkpoint_insts) return; - Tick when = curTick + delay * Clock::Int::ns; - Tick repeat = period * Clock::Int::ns; + Tick when = curTick + delay * SimClock::Int::ns; + Tick repeat = period * SimClock::Int::ns; Event *event = new SimLoopExitEvent("checkpoint", 0, repeat); mainEventQueue.schedule(event, when); diff --git a/src/sim/stat_control.cc b/src/sim/stat_control.cc index 2dcf4798d..e8c2d5814 100644 --- a/src/sim/stat_control.cc +++ b/src/sim/stat_control.cc @@ -106,7 +106,7 @@ Global::Global() ; simFreq - .scalar(Clock::Frequency) + .scalar(SimClock::Frequency) .name("sim_freq") .desc("Frequency of simulated ticks") ; diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh index 66e800183..6016ccfd9 100644 --- a/src/sim/syscall_emul.hh +++ b/src/sim/syscall_emul.hh @@ -360,7 +360,7 @@ template <class T1, class T2> void getElapsedTime(T1 &sec, T2 &usec) { - int elapsed_usecs = curTick / Clock::Int::us; + int elapsed_usecs = curTick / SimClock::Int::us; sec = elapsed_usecs / one_million; usec = elapsed_usecs % one_million; } @@ -1187,7 +1187,7 @@ timesFunc(SyscallDesc *desc, int callnum, LiveProcess *process, TypedBufferArg<typename OS::tms> bufp(process->getSyscallArg(tc, index)); // Fill in the time structure (in clocks) - int64_t clocks = curTick * OS::M5_SC_CLK_TCK / Clock::Int::s; + int64_t clocks = curTick * OS::M5_SC_CLK_TCK / SimClock::Int::s; bufp->tms_utime = clocks; bufp->tms_stime = 0; bufp->tms_cutime = 0; |