SE/FS: Make SE vs. FS mode a runtime parameter.

47 files changed, 55 insertions, 49 deletions

diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py
index 6154f9877..80379f6a3 100644
--- a/configs/common/FSConfig.py
+++ b/configs/common/FSConfig.py
@@ -552,8 +552,8 @@ def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
     return self
 
 
-def makeDualRoot(testSystem, driveSystem, dumpfile):
-    self = Root()
+def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
+    self = Root(full_system = full_system)
     self.testsys = testSystem
     self.drivesys = driveSystem
     self.etherlink = EtherLink()
diff --git a/configs/example/fs.py b/configs/example/fs.py
index 08484559a..9f41e24b9 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -198,9 +198,9 @@ if len(bm) == 2:
         drive_sys.kernel = binary(options.kernel)
 
     drive_sys.init_param = options.init_param
-    root = makeDualRoot(test_sys, drive_sys, options.etherdump)
+    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
 elif len(bm) == 1:
-    root = Root(system=test_sys)
+    root = Root(full_system=True, system=test_sys)
 else:
     print "Error I don't know how to create more than 2 systems."
     sys.exit(1)
diff --git a/configs/example/memtest.py b/configs/example/memtest.py
index 24a49a9b3..b2cedc8f5 100644
--- a/configs/example/memtest.py
+++ b/configs/example/memtest.py
@@ -172,7 +172,7 @@ make_level(treespec, prototypes, system.physmem, "port")
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 if options.atomic:
     root.system.mem_mode = 'atomic'
 else:
diff --git a/configs/example/ruby_direct_test.py b/configs/example/ruby_direct_test.py
index 55b1c85e6..d4843e866 100644
--- a/configs/example/ruby_direct_test.py
+++ b/configs/example/ruby_direct_test.py
@@ -111,7 +111,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index e6ac5f8c8..e18ed95af 100644
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -141,6 +141,6 @@ for (i, cpu) in enumerate(system.cpu):
         cpu.interrupts.pio = system.piobus.port
         cpu.interrupts.int_port = system.piobus.port
 
-root = Root(system = system)
+root = Root(full_system = True, system = system)
 
 Simulation.run(options, root, system, FutureClass)
diff --git a/configs/example/ruby_mem_test.py b/configs/example/ruby_mem_test.py
index 6b1a46776..a418c47eb 100644
--- a/configs/example/ruby_mem_test.py
+++ b/configs/example/ruby_mem_test.py
@@ -162,7 +162,7 @@ for (i, dma) in enumerate(dmas):
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/configs/example/ruby_network_test.py b/configs/example/ruby_network_test.py
index cd221ec7e..b5d788bf5 100644
--- a/configs/example/ruby_network_test.py
+++ b/configs/example/ruby_network_test.py
@@ -121,7 +121,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/configs/example/ruby_random_test.py b/configs/example/ruby_random_test.py
index 7655e32fd..4bf17d70b 100644
--- a/configs/example/ruby_random_test.py
+++ b/configs/example/ruby_random_test.py
@@ -131,7 +131,7 @@ for ruby_port in system.ruby._cpu_ruby_ports:
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/configs/example/se.py b/configs/example/se.py
index 572364482..f1dae9482 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -200,6 +200,6 @@ for i in xrange(np):
     if options.fastmem:
         system.cpu[0].physmem_port = system.physmem.port
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 
 Simulation.run(options, root, system, FutureClass)
diff --git a/configs/splash2/cluster.py b/configs/splash2/cluster.py
index e8c471eaa..4a9446794 100644
--- a/configs/splash2/cluster.py
+++ b/configs/splash2/cluster.py
@@ -239,7 +239,7 @@ for cluster in clusters:
 # Define the root
 # ----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 
 # --------------------
 # Pick the correct Splash2 Benchmarks
diff --git a/configs/splash2/run.py b/configs/splash2/run.py
index 200eb191d..8a9b815e6 100644
--- a/configs/splash2/run.py
+++ b/configs/splash2/run.py
@@ -225,7 +225,7 @@ for cpu in cpus:
 # Define the root
 # ----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 
 # --------------------
 # Pick the correct Splash2 Benchmarks
diff --git a/src/sim/Root.py b/src/sim/Root.py
index e15de1554..daa0a903f 100644
--- a/src/sim/Root.py
+++ b/src/sim/Root.py
@@ -28,6 +28,7 @@
 # Authors: Nathan Binkert
 
 from m5.SimObject import SimObject
+from m5.defines import buildEnv
 from m5.params import *
 from m5.util import fatal
 
@@ -58,6 +59,8 @@ class Root(SimObject):
 
     type = 'Root'
 
+    full_system = Param.Bool("if this is a full system simulation")
+
     # Time syncing prevents the simulation from running faster than real time.
     time_sync_enable = Param.Bool(False, "whether time syncing is enabled")
     time_sync_period = Param.Clock("100ms", "how often to sync with real time")
diff --git a/src/sim/full_system.hh b/src/sim/full_system.hh
index 911648f3a..e67fc11a9 100644
--- a/src/sim/full_system.hh
+++ b/src/sim/full_system.hh
@@ -31,8 +31,6 @@
 #ifndef __SIM_FULL_SYSTEM_HH__
 #define __SIM_FULL_SYSTEM_HH__
 
-#include "config/full_system.hh"
-
-static const bool FullSystem = FULL_SYSTEM;
+extern bool FullSystem;
 
 #endif // __SIM_FULL_SYSTEM_HH__
diff --git a/src/sim/root.cc b/src/sim/root.cc
index dd7c12077..c47ada30e 100644
--- a/src/sim/root.cc
+++ b/src/sim/root.cc
@@ -33,6 +33,7 @@
 
 #include "base/misc.hh"
 #include "debug/TimeSync.hh"
+#include "sim/full_system.hh"
 #include "sim/root.hh"
 
 Root *Root::_root = NULL;
@@ -123,6 +124,8 @@ Root::loadState(Checkpoint *cp)
     timeSyncEnable(params()->time_sync_enable);
 }
 
+bool FullSystem;
+
 Root *
 RootParams::create()
 {
@@ -132,5 +135,7 @@ RootParams::create()
 
     created = true;
 
+    FullSystem = full_system;
+
     return new Root(this);
 }
diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py
index 1bab83609..2a87cb663 100644
--- a/tests/configs/inorder-timing.py
+++ b/tests/configs/inorder-timing.py
@@ -54,4 +54,4 @@ system.system_port = system.membus.port
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff --git a/tests/configs/memtest-ruby.py b/tests/configs/memtest-ruby.py
index 2517e7670..6d0f8aa86 100644
--- a/tests/configs/memtest-ruby.py
+++ b/tests/configs/memtest-ruby.py
@@ -117,7 +117,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py
index 66e49a63e..c1358eecd 100644
--- a/tests/configs/memtest.py
+++ b/tests/configs/memtest.py
@@ -86,7 +86,7 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 #root.trace.flags="Cache CachePort MemoryAccess"
 #root.trace.cycle=1
diff --git a/tests/configs/o3-timing-mp-ruby.py b/tests/configs/o3-timing-mp-ruby.py
index b14f0e5b1..2f8829db0 100644
--- a/tests/configs/o3-timing-mp-ruby.py
+++ b/tests/configs/o3-timing-mp-ruby.py
@@ -51,5 +51,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py
index 67aaebd21..9436cf88a 100644
--- a/tests/configs/o3-timing-mp.py
+++ b/tests/configs/o3-timing-mp.py
@@ -86,7 +86,7 @@ system.system_port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
 #root.trace.flags="Bus Cache"
 #root.trace.flags = "BusAddrRanges"
diff --git a/tests/configs/o3-timing-ruby.py b/tests/configs/o3-timing-ruby.py
index 07851ae9f..b967a5080 100644
--- a/tests/configs/o3-timing-ruby.py
+++ b/tests/configs/o3-timing-ruby.py
@@ -43,4 +43,4 @@ system = System(cpu = cpu,
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py
index 395fd24a3..9701b1012 100644
--- a/tests/configs/o3-timing.py
+++ b/tests/configs/o3-timing.py
@@ -54,4 +54,4 @@ system.system_port = system.membus.port
 system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff --git a/tests/configs/pc-o3-timing.py b/tests/configs/pc-o3-timing.py
index 0fe23d1ee..f3b8e700f 100644
--- a/tests/configs/pc-o3-timing.py
+++ b/tests/configs/pc-o3-timing.py
@@ -108,6 +108,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/pc-simple-atomic.py b/tests/configs/pc-simple-atomic.py
index eeff17069..62c7c7bd4 100644
--- a/tests/configs/pc-simple-atomic.py
+++ b/tests/configs/pc-simple-atomic.py
@@ -110,6 +110,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/pc-simple-timing.py b/tests/configs/pc-simple-timing.py
index a1b2f4676..cbfda22a2 100644
--- a/tests/configs/pc-simple-timing.py
+++ b/tests/configs/pc-simple-timing.py
@@ -110,6 +110,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
index 69c583abd..adab96fcb 100644
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
index bab5a193d..f466bc480 100644
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -92,6 +92,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-simple-atomic-dual.py b/tests/configs/realview-simple-atomic-dual.py
index edfd940ad..5baa3c91a 100644
--- a/tests/configs/realview-simple-atomic-dual.py
+++ b/tests/configs/realview-simple-atomic-dual.py
@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-simple-atomic.py b/tests/configs/realview-simple-atomic.py
index 83f85641a..f1de86411 100644
--- a/tests/configs/realview-simple-atomic.py
+++ b/tests/configs/realview-simple-atomic.py
@@ -90,6 +90,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-simple-timing-dual.py b/tests/configs/realview-simple-timing-dual.py
index 7fe0d409b..81646f825 100644
--- a/tests/configs/realview-simple-timing-dual.py
+++ b/tests/configs/realview-simple-timing-dual.py
@@ -94,6 +94,6 @@ for c in cpus:
     c.clock = '2GHz'
 
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/realview-simple-timing.py b/tests/configs/realview-simple-timing.py
index 90f2539e6..8d1840571 100644
--- a/tests/configs/realview-simple-timing.py
+++ b/tests/configs/realview-simple-timing.py
@@ -92,6 +92,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/rubytest-ruby.py b/tests/configs/rubytest-ruby.py
index a7e598b0a..0fffe1aa2 100644
--- a/tests/configs/rubytest-ruby.py
+++ b/tests/configs/rubytest-ruby.py
@@ -112,7 +112,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root(full_system = False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/tests/configs/simple-atomic-mp-ruby.py b/tests/configs/simple-atomic-mp-ruby.py
index 705f13ef3..fe0311801 100644
--- a/tests/configs/simple-atomic-mp-ruby.py
+++ b/tests/configs/simple-atomic-mp-ruby.py
@@ -52,5 +52,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'atomic'
diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py
index e722ef334..db0c0b9c0 100644
--- a/tests/configs/simple-atomic-mp.py
+++ b/tests/configs/simple-atomic-mp.py
@@ -85,5 +85,5 @@ system.system_port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'atomic'
diff --git a/tests/configs/simple-atomic.py b/tests/configs/simple-atomic.py
index 191230164..eb7415b8d 100644
--- a/tests/configs/simple-atomic.py
+++ b/tests/configs/simple-atomic.py
@@ -37,4 +37,4 @@ system.physmem.port = system.membus.port
 system.cpu.connectAllPorts(system.membus)
 system.cpu.clock = '2GHz'
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
diff --git a/tests/configs/simple-timing-mp-ruby.py b/tests/configs/simple-timing-mp-ruby.py
index 58ca862e1..63d5291b9 100644
--- a/tests/configs/simple-timing-mp-ruby.py
+++ b/tests/configs/simple-timing-mp-ruby.py
@@ -95,7 +95,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system=False, system = system )
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py
index f1ebb1939..c82ef0a26 100644
--- a/tests/configs/simple-timing-mp.py
+++ b/tests/configs/simple-timing-mp.py
@@ -85,5 +85,5 @@ system.physmem.port = system.membus.port
 # run simulation
 # -----------------------
 
-root = Root( system = system )
+root = Root( full_system = False, system = system )
 root.system.mem_mode = 'timing'
diff --git a/tests/configs/simple-timing-ruby.py b/tests/configs/simple-timing-ruby.py
index 319dd3b55..2324c196b 100644
--- a/tests/configs/simple-timing-ruby.py
+++ b/tests/configs/simple-timing-ruby.py
@@ -91,7 +91,7 @@ system.system_port = system.ruby._sys_port_proxy.port
 # run simulation
 # -----------------------
 
-root = Root(system = system)
+root = Root(full_system = False, system = system)
 root.system.mem_mode = 'timing'
 
 # Not much point in this being higher than the L1 latency
diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py
index cc0d1d207..19b40fe48 100644
--- a/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@ -51,4 +51,4 @@ system.physmem.port = system.membus.port
 cpu.connectAllPorts(system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system = system)
+root = Root(full_system=False, system = system)
diff --git a/tests/configs/t1000-simple-atomic.py b/tests/configs/t1000-simple-atomic.py
index ae2c59110..217135bf0 100644
--- a/tests/configs/t1000-simple-atomic.py
+++ b/tests/configs/t1000-simple-atomic.py
@@ -36,6 +36,6 @@ system = FSConfig.makeSparcSystem('atomic')
 system.cpu = cpu
 cpu.connectAllPorts(system.membus)
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 
 m5.ticks.setGlobalFrequency('2GHz')
diff --git a/tests/configs/tsunami-inorder.py b/tests/configs/tsunami-inorder.py
index a08261533..dc30633b3 100644
--- a/tests/configs/tsunami-inorder.py
+++ b/tests/configs/tsunami-inorder.py
@@ -96,6 +96,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/tsunami-o3-dual.py b/tests/configs/tsunami-o3-dual.py
index c63637f73..1680be166 100644
--- a/tests/configs/tsunami-o3-dual.py
+++ b/tests/configs/tsunami-o3-dual.py
@@ -95,6 +95,6 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/tsunami-o3.py b/tests/configs/tsunami-o3.py
index a6bb4b122..accf350b3 100644
--- a/tests/configs/tsunami-o3.py
+++ b/tests/configs/tsunami-o3.py
@@ -93,6 +93,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py
index 758dbef09..9a29f5c65 100644
--- a/tests/configs/tsunami-simple-atomic-dual.py
+++ b/tests/configs/tsunami-simple-atomic-dual.py
@@ -93,5 +93,5 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py
index a2335d763..897b1c946 100644
--- a/tests/configs/tsunami-simple-atomic.py
+++ b/tests/configs/tsunami-simple-atomic.py
@@ -91,6 +91,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py
index ad466a5c0..6b78b71f4 100644
--- a/tests/configs/tsunami-simple-timing-dual.py
+++ b/tests/configs/tsunami-simple-timing-dual.py
@@ -93,7 +93,7 @@ for c in cpus:
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
 
diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py
index 7dc0ded5c..e3a764e16 100644
--- a/tests/configs/tsunami-simple-timing.py
+++ b/tests/configs/tsunami-simple-timing.py
@@ -93,6 +93,6 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
 
-root = Root(system=system)
+root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')
 
diff --git a/tests/configs/twosys-tsunami-simple-atomic.py b/tests/configs/twosys-tsunami-simple-atomic.py
index 658508fa0..d32e5dd87 100644
--- a/tests/configs/twosys-tsunami-simple-atomic.py
+++ b/tests/configs/twosys-tsunami-simple-atomic.py
@@ -53,6 +53,6 @@ drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
 drive_sys.iobridge.slave = drive_sys.iobus.port
 drive_sys.iobridge.master = drive_sys.membus.port
 
-root = makeDualRoot(test_sys, drive_sys, "ethertrace")
+root = makeDualRoot(True, test_sys, drive_sys, "ethertrace")
 
 maxtick = 199999999