python: Don't assume SimObjects live in the global namespace

The importer in Python 3 doesn't like the way we import SimObjects
from the global namespace. Convert the existing SimObject declarations
to import from m5.objects. As a side-effect, this makes these files
consistent with configuration files.

Change-Id: I11153502b430822130722839e1fa767b82a027aa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15981
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

131 files changed, 300 insertions, 267 deletions

diff --git a/src/arch/alpha/AlphaSystem.py b/src/arch/alpha/AlphaSystem.py
index 1bf3b1981..0d76447c8 100644
--- a/src/arch/alpha/AlphaSystem.py
+++ b/src/arch/alpha/AlphaSystem.py
@@ -28,7 +28,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from System import System
+
+from m5.objects.System import System
 
 class AlphaSystem(System):
     type = 'AlphaSystem'
diff --git a/src/arch/alpha/AlphaTLB.py b/src/arch/alpha/AlphaTLB.py
index 8031c719f..f2e285360 100644
--- a/src/arch/alpha/AlphaTLB.py
+++ b/src/arch/alpha/AlphaTLB.py
@@ -29,7 +29,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class AlphaTLB(BaseTLB):
     type = 'AlphaTLB'
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
index b4e8536a0..70be40313 100644
--- a/src/arch/arm/ArmISA.py
+++ b/src/arch/arm/ArmISA.py
@@ -40,8 +40,8 @@ from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
-from ArmPMU import ArmPMU
-from ISACommon import VecRegRenameMode
+from m5.objects.ArmPMU import ArmPMU
+from m5.objects.ISACommon import VecRegRenameMode
 
 # Enum for DecoderFlavour
 class DecoderFlavour(Enum): vals = ['Generic']
diff --git a/src/arch/arm/ArmNativeTrace.py b/src/arch/arm/ArmNativeTrace.py
index 3101c33de..53ee04a8b 100644
--- a/src/arch/arm/ArmNativeTrace.py
+++ b/src/arch/arm/ArmNativeTrace.py
@@ -28,7 +28,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from CPUTracers import NativeTrace
+from m5.objects.CPUTracers import NativeTrace
 
 class ArmNativeTrace(NativeTrace):
     type = 'ArmNativeTrace'
diff --git a/src/arch/arm/ArmPMU.py b/src/arch/arm/ArmPMU.py
index cb37ff88c..be9dbb86e 100644
--- a/src/arch/arm/ArmPMU.py
+++ b/src/arch/arm/ArmPMU.py
@@ -42,7 +42,7 @@ from m5.SimObject import *
 from m5.params import *
 from m5.params import isNullPointer
 from m5.proxy import *
-from Gic import ArmInterruptPin
+from m5.objects.Gic import ArmInterruptPin
 
 class ProbeEvent(object):
     def __init__(self, pmu, _eventId, obj, *listOfNames):
diff --git a/src/arch/arm/ArmSemihosting.py b/src/arch/arm/ArmSemihosting.py
index 784649914..a804aa8ab 100644
--- a/src/arch/arm/ArmSemihosting.py
+++ b/src/arch/arm/ArmSemihosting.py
@@ -38,8 +38,8 @@
 from m5.params import *
 from m5.SimObject import *
 
-from Serial import SerialDevice
-from Terminal import Terminal
+from m5.objects.Serial import SerialDevice
+from m5.objects.Terminal import Terminal
 
 class ArmSemihosting(SimObject):
     type = 'ArmSemihosting'
diff --git a/src/arch/arm/ArmSystem.py b/src/arch/arm/ArmSystem.py
index 98ff95918..7ade1e695 100644
--- a/src/arch/arm/ArmSystem.py
+++ b/src/arch/arm/ArmSystem.py
@@ -41,8 +41,8 @@ from m5.options import *
 from m5.SimObject import *
 from m5.util.fdthelper import *
 
-from System import System
-from ArmSemihosting import ArmSemihosting
+from m5.objects.System import System
+from m5.objects.ArmSemihosting import ArmSemihosting
 
 class ArmMachineType(Enum):
     map = {
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index 4cac944f1..c5a8122dd 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -40,8 +40,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from BaseTLB import BaseTLB
+from m5.objects.MemObject import MemObject
+from m5.objects.BaseTLB import BaseTLB
 
 # Basic stage 1 translation objects
 class ArmTableWalker(MemObject):
diff --git a/src/arch/arm/tracers/TarmacTrace.py b/src/arch/arm/tracers/TarmacTrace.py
index 8955fadd6..7c0e60f59 100644
--- a/src/arch/arm/tracers/TarmacTrace.py
+++ b/src/arch/arm/tracers/TarmacTrace.py
@@ -38,7 +38,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from InstTracer import InstTracer
+from m5.objects.InstTracer import InstTracer
 
 class TarmacParser(InstTracer):
     type = 'TarmacParser'
diff --git a/src/arch/mips/MipsSystem.py b/src/arch/mips/MipsSystem.py
index 58e30f28d..7a5d8fd76 100644
--- a/src/arch/mips/MipsSystem.py
+++ b/src/arch/mips/MipsSystem.py
@@ -32,7 +32,7 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 
-from System import System
+from m5.objects.System import System
 
 class MipsSystem(System):
     type = 'MipsSystem'
diff --git a/src/arch/mips/MipsTLB.py b/src/arch/mips/MipsTLB.py
index c43cee717..62996ccab 100644
--- a/src/arch/mips/MipsTLB.py
+++ b/src/arch/mips/MipsTLB.py
@@ -32,7 +32,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class MipsTLB(BaseTLB):
     type = 'MipsTLB'
diff --git a/src/arch/power/PowerTLB.py b/src/arch/power/PowerTLB.py
index b12c5a8e3..5c582b485 100644
--- a/src/arch/power/PowerTLB.py
+++ b/src/arch/power/PowerTLB.py
@@ -31,7 +31,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class PowerTLB(BaseTLB):
     type = 'PowerTLB'
diff --git a/src/arch/riscv/RiscvSystem.py b/src/arch/riscv/RiscvSystem.py
index 071b211a2..ea1defd90 100644
--- a/src/arch/riscv/RiscvSystem.py
+++ b/src/arch/riscv/RiscvSystem.py
@@ -31,8 +31,8 @@
 #          Robert Scheffel
 
 from m5.params import *
-from System import System
 
+from m5.objects.System import System
 
 class RiscvSystem(System):
     type = 'RiscvSystem'
diff --git a/src/arch/riscv/RiscvTLB.py b/src/arch/riscv/RiscvTLB.py
index bcba00ee0..b24fffb43 100644
--- a/src/arch/riscv/RiscvTLB.py
+++ b/src/arch/riscv/RiscvTLB.py
@@ -32,7 +32,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class RiscvTLB(BaseTLB):
     type = 'RiscvTLB'
diff --git a/src/arch/sparc/SparcNativeTrace.py b/src/arch/sparc/SparcNativeTrace.py
index 46b606652..1dbac34c3 100644
--- a/src/arch/sparc/SparcNativeTrace.py
+++ b/src/arch/sparc/SparcNativeTrace.py
@@ -28,7 +28,8 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from CPUTracers import NativeTrace
+
+from m5.objects.CPUTracers import NativeTrace
 
 class SparcNativeTrace(NativeTrace):
     type = 'SparcNativeTrace'
diff --git a/src/arch/sparc/SparcSystem.py b/src/arch/sparc/SparcSystem.py
index 9d8be5d06..60c56c69b 100644
--- a/src/arch/sparc/SparcSystem.py
+++ b/src/arch/sparc/SparcSystem.py
@@ -28,8 +28,8 @@
 
 from m5.params import *
 
-from SimpleMemory import SimpleMemory
-from System import System
+from m5.objects.SimpleMemory import SimpleMemory
+from m5.objects.System import System
 
 class SparcSystem(System):
     type = 'SparcSystem'
diff --git a/src/arch/sparc/SparcTLB.py b/src/arch/sparc/SparcTLB.py
index 219f6842a..a7bfaea2a 100644
--- a/src/arch/sparc/SparcTLB.py
+++ b/src/arch/sparc/SparcTLB.py
@@ -29,7 +29,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 
-from BaseTLB import BaseTLB
+from m5.objects.BaseTLB import BaseTLB
 
 class SparcTLB(BaseTLB):
     type = 'SparcTLB'
diff --git a/src/arch/x86/X86LocalApic.py b/src/arch/x86/X86LocalApic.py
index 5c14679c2..5d4910e98 100644
--- a/src/arch/x86/X86LocalApic.py
+++ b/src/arch/x86/X86LocalApic.py
@@ -41,7 +41,8 @@
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
+
+from m5.objects.Device import BasicPioDevice
 
 class X86LocalApic(BasicPioDevice):
     type = 'X86LocalApic'
diff --git a/src/arch/x86/X86NativeTrace.py b/src/arch/x86/X86NativeTrace.py
index e6eae8918..798fc879f 100644
--- a/src/arch/x86/X86NativeTrace.py
+++ b/src/arch/x86/X86NativeTrace.py
@@ -28,7 +28,8 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from CPUTracers import NativeTrace
+
+from m5.objects.CPUTracers import NativeTrace
 
 class X86NativeTrace(NativeTrace):
     type = 'X86NativeTrace'
diff --git a/src/arch/x86/X86System.py b/src/arch/x86/X86System.py
index 02185b648..e2ee1b6ec 100644
--- a/src/arch/x86/X86System.py
+++ b/src/arch/x86/X86System.py
@@ -36,11 +36,12 @@
 # Authors: Gabe Black
 
 from m5.params import *
-from E820 import X86E820Table, X86E820Entry
-from SMBios import X86SMBiosSMBiosTable
-from IntelMP import X86IntelMPFloatingPointer, X86IntelMPConfigTable
-from ACPI import X86ACPIRSDP
-from System import System
+
+from m5.objects.E820 import X86E820Table, X86E820Entry
+from m5.objects.SMBios import X86SMBiosSMBiosTable
+from m5.objects.IntelMP import X86IntelMPFloatingPointer, X86IntelMPConfigTable
+from m5.objects.ACPI import X86ACPIRSDP
+from m5.objects.System import System
 
 class X86System(System):
     type = 'X86System'
diff --git a/src/arch/x86/X86TLB.py b/src/arch/x86/X86TLB.py
index 7f195f233..1b2f63d1d 100644
--- a/src/arch/x86/X86TLB.py
+++ b/src/arch/x86/X86TLB.py
@@ -38,8 +38,8 @@
 from m5.params import *
 from m5.proxy import *
 
-from BaseTLB import BaseTLB
-from MemObject import MemObject
+from m5.objects.BaseTLB import BaseTLB
+from m5.objects.MemObject import MemObject
 
 class X86PagetableWalker(MemObject):
     type = 'X86PagetableWalker'
diff --git a/src/base/vnc/Vnc.py b/src/base/vnc/Vnc.py
index e440d101e..2cdec4b41 100644
--- a/src/base/vnc/Vnc.py
+++ b/src/base/vnc/Vnc.py
@@ -37,7 +37,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from Graphics import *
+from m5.objects.Graphics import *
 
 
 class VncInput(SimObject):
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index e02d36724..007c869af 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -52,51 +52,51 @@ from m5.params import *
 from m5.proxy import *
 from m5.util.fdthelper import *
 
-from XBar import L2XBar
-from InstTracer import InstTracer
-from CPUTracers import ExeTracer
-from MemObject import MemObject
-from SubSystem import SubSystem
-from ClockDomain import *
-from Platform import Platform
+from m5.objects.XBar import L2XBar
+from m5.objects.InstTracer import InstTracer
+from m5.objects.CPUTracers import ExeTracer
+from m5.objects.MemObject import MemObject
+from m5.objects.SubSystem import SubSystem
+from m5.objects.ClockDomain import *
+from m5.objects.Platform import Platform
 
 default_tracer = ExeTracer()
 
 if buildEnv['TARGET_ISA'] == 'alpha':
-    from AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
-    from AlphaInterrupts import AlphaInterrupts
-    from AlphaISA import AlphaISA
+    from m5.objects.AlphaTLB import AlphaDTB as ArchDTB, AlphaITB as ArchITB
+    from m5.objects.AlphaInterrupts import AlphaInterrupts
+    from m5.objects.AlphaISA import AlphaISA
     default_isa_class = AlphaISA
 elif buildEnv['TARGET_ISA'] == 'sparc':
-    from SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
-    from SparcInterrupts import SparcInterrupts
-    from SparcISA import SparcISA
+    from m5.objects.SparcTLB import SparcTLB as ArchDTB, SparcTLB as ArchITB
+    from m5.objects.SparcInterrupts import SparcInterrupts
+    from m5.objects.SparcISA import SparcISA
     default_isa_class = SparcISA
 elif buildEnv['TARGET_ISA'] == 'x86':
-    from X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
-    from X86LocalApic import X86LocalApic
-    from X86ISA import X86ISA
+    from m5.objects.X86TLB import X86TLB as ArchDTB, X86TLB as ArchITB
+    from m5.objects.X86LocalApic import X86LocalApic
+    from m5.objects.X86ISA import X86ISA
     default_isa_class = X86ISA
 elif buildEnv['TARGET_ISA'] == 'mips':
-    from MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
-    from MipsInterrupts import MipsInterrupts
-    from MipsISA import MipsISA
+    from m5.objects.MipsTLB import MipsTLB as ArchDTB, MipsTLB as ArchITB
+    from m5.objects.MipsInterrupts import MipsInterrupts
+    from m5.objects.MipsISA import MipsISA
     default_isa_class = MipsISA
 elif buildEnv['TARGET_ISA'] == 'arm':
-    from ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
-    from ArmTLB import ArmStage2IMMU, ArmStage2DMMU
-    from ArmInterrupts import ArmInterrupts
-    from ArmISA import ArmISA
+    from m5.objects.ArmTLB import ArmTLB as ArchDTB, ArmTLB as ArchITB
+    from m5.objects.ArmTLB import ArmStage2IMMU, ArmStage2DMMU
+    from m5.objects.ArmInterrupts import ArmInterrupts
+    from m5.objects.ArmISA import ArmISA
     default_isa_class = ArmISA
 elif buildEnv['TARGET_ISA'] == 'power':
-    from PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
-    from PowerInterrupts import PowerInterrupts
-    from PowerISA import PowerISA
+    from m5.objects.PowerTLB import PowerTLB as ArchDTB, PowerTLB as ArchITB
+    from m5.objects.PowerInterrupts import PowerInterrupts
+    from m5.objects.PowerISA import PowerISA
     default_isa_class = PowerISA
 elif buildEnv['TARGET_ISA'] == 'riscv':
-    from RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
-    from RiscvInterrupts import RiscvInterrupts
-    from RiscvISA import RiscvISA
+    from m5.objects.RiscvTLB import RiscvTLB as ArchDTB, RiscvTLB as ArchITB
+    from m5.objects.RiscvInterrupts import RiscvInterrupts
+    from m5.objects.RiscvISA import RiscvISA
     default_isa_class = RiscvISA
 
 class BaseCPU(MemObject):
diff --git a/src/cpu/CPUTracers.py b/src/cpu/CPUTracers.py
index df7a8939f..16d003683 100644
--- a/src/cpu/CPUTracers.py
+++ b/src/cpu/CPUTracers.py
@@ -28,7 +28,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from InstTracer import InstTracer
+from m5.objects.InstTracer import InstTracer
 
 class ExeTracer(InstTracer):
     type = 'ExeTracer'
diff --git a/src/cpu/CheckerCPU.py b/src/cpu/CheckerCPU.py
index f08b59f20..51c1e5c3c 100644
--- a/src/cpu/CheckerCPU.py
+++ b/src/cpu/CheckerCPU.py
@@ -27,7 +27,8 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from BaseCPU import BaseCPU
+
+from m5.objects.BaseCPU import BaseCPU
 
 class CheckerCPU(BaseCPU):
     type = 'CheckerCPU'
diff --git a/src/cpu/DummyChecker.py b/src/cpu/DummyChecker.py
index 3bf021a14..300909209 100644
--- a/src/cpu/DummyChecker.py
+++ b/src/cpu/DummyChecker.py
@@ -36,7 +36,7 @@
 # Authors: Geoffrey Blake
 
 from m5.params import *
-from CheckerCPU import CheckerCPU
+from m5.objects.CheckerCPU import CheckerCPU
 
 class DummyChecker(CheckerCPU):
     type = 'DummyChecker'
diff --git a/src/cpu/InstPBTrace.py b/src/cpu/InstPBTrace.py
index 2576fc944..8feedd60c 100644
--- a/src/cpu/InstPBTrace.py
+++ b/src/cpu/InstPBTrace.py
@@ -28,7 +28,8 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from InstTracer import InstTracer
+
+from m5.objects.InstTracer import InstTracer
 
 class InstPBTrace(InstTracer):
     type = 'InstPBTrace'
diff --git a/src/cpu/kvm/BaseKvmCPU.py b/src/cpu/kvm/BaseKvmCPU.py
index cb9bf481a..c9e64bd69 100644
--- a/src/cpu/kvm/BaseKvmCPU.py
+++ b/src/cpu/kvm/BaseKvmCPU.py
@@ -39,8 +39,8 @@ from m5.SimObject import *
 from m5.params import *
 from m5.proxy import *
 
-from BaseCPU import BaseCPU
-from KvmVM import KvmVM
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.KvmVM import KvmVM
 
 class BaseKvmCPU(BaseCPU):
     type = 'BaseKvmCPU'
diff --git a/src/cpu/kvm/X86KvmCPU.py b/src/cpu/kvm/X86KvmCPU.py
index 411db7dbe..a632bff3f 100644
--- a/src/cpu/kvm/X86KvmCPU.py
+++ b/src/cpu/kvm/X86KvmCPU.py
@@ -28,7 +28,8 @@
 
 from m5.params import *
 from m5.SimObject import *
-from BaseKvmCPU import BaseKvmCPU
+
+from m5.objects.BaseKvmCPU import BaseKvmCPU
 
 class X86KvmCPU(BaseKvmCPU):
     type = 'X86KvmCPU'
diff --git a/src/cpu/minor/MinorCPU.py b/src/cpu/minor/MinorCPU.py
index 9e285a4d1..bb4df82f0 100644
--- a/src/cpu/minor/MinorCPU.py
+++ b/src/cpu/minor/MinorCPU.py
@@ -46,12 +46,12 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from BaseCPU import BaseCPU
-from DummyChecker import DummyChecker
-from BranchPredictor import *
-from TimingExpr import TimingExpr
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.DummyChecker import DummyChecker
+from m5.objects.BranchPredictor import *
+from m5.objects.TimingExpr import TimingExpr
 
-from FuncUnit import OpClass
+from m5.objects.FuncUnit import OpClass
 
 class MinorOpClass(SimObject):
     """Boxing of OpClass to get around build problems and provide a hook for
diff --git a/src/cpu/o3/FUPool.py b/src/cpu/o3/FUPool.py
index 0f4ea67c7..1461b405c 100644
--- a/src/cpu/o3/FUPool.py
+++ b/src/cpu/o3/FUPool.py
@@ -28,8 +28,8 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from FuncUnit import *
-from FuncUnitConfig import *
+from m5.objects.FuncUnit import *
+from m5.objects.FuncUnitConfig import *
 
 class FUPool(SimObject):
     type = 'FUPool'
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index f0c70f55a..ef114df09 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -41,7 +41,8 @@
 from m5.SimObject import SimObject
 from m5.defines import buildEnv
 from m5.params import *
-from FuncUnit import *
+
+from m5.objects.FuncUnit import *
 
 class IntALU(FUDesc):
     opList = [ OpDesc(opClass='IntAlu') ]
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
index e73c09334..8e17d9a3f 100644
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -43,10 +43,11 @@ from __future__ import print_function
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
-from BaseCPU import BaseCPU
-from FUPool import *
-from O3Checker import O3Checker
-from BranchPredictor import *
+
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.FUPool import *
+from m5.objects.O3Checker import O3Checker
+from m5.objects.BranchPredictor import *
 
 class FetchPolicy(ScopedEnum):
     vals = [ 'SingleThread', 'RoundRobin', 'Branch', 'IQCount', 'LSQCount' ]
@@ -178,7 +179,7 @@ class DerivO3CPU(BaseCPU):
 
     def addCheckerCpu(self):
         if buildEnv['TARGET_ISA'] in ['arm']:
-            from ArmTLB import ArmTLB
+            from m5.objects.ArmTLB import ArmTLB
 
             self.checker = O3Checker(workload=self.workload,
                                      exitOnError=False,
diff --git a/src/cpu/o3/O3Checker.py b/src/cpu/o3/O3Checker.py
index f21a038c4..20d59c1f4 100644
--- a/src/cpu/o3/O3Checker.py
+++ b/src/cpu/o3/O3Checker.py
@@ -27,7 +27,7 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from CheckerCPU import CheckerCPU
+from m5.objects.CheckerCPU import CheckerCPU
 
 class O3Checker(CheckerCPU):
     type = 'O3Checker'
diff --git a/src/cpu/o3/probe/ElasticTrace.py b/src/cpu/o3/probe/ElasticTrace.py
index 20057ab97..d60681d3f 100644
--- a/src/cpu/o3/probe/ElasticTrace.py
+++ b/src/cpu/o3/probe/ElasticTrace.py
@@ -37,7 +37,7 @@
 #          Andreas Hansson
 #          Thomas Grass
 
-from Probe import *
+from m5.objects.Probe import *
 
 class ElasticTrace(ProbeListenerObject):
     type = 'ElasticTrace'
diff --git a/src/cpu/o3/probe/SimpleTrace.py b/src/cpu/o3/probe/SimpleTrace.py
index eeec58ef0..9572aa218 100644
--- a/src/cpu/o3/probe/SimpleTrace.py
+++ b/src/cpu/o3/probe/SimpleTrace.py
@@ -35,7 +35,7 @@
 #
 # Authors: Matt Horsnell
 
-from Probe import *
+from m5.objects.Probe import *
 
 class SimpleTrace(ProbeListenerObject):
     type = 'SimpleTrace'
diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/AtomicSimpleCPU.py
index 15a3feb69..d9dee461b 100644
--- a/src/cpu/simple/AtomicSimpleCPU.py
+++ b/src/cpu/simple/AtomicSimpleCPU.py
@@ -39,8 +39,8 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from BaseSimpleCPU import BaseSimpleCPU
-from SimPoint import SimPoint
+from m5.objects.BaseSimpleCPU import BaseSimpleCPU
+from m5.objects.SimPoint import SimPoint
 
 class AtomicSimpleCPU(BaseSimpleCPU):
     """Simple CPU model executing a configurable number of
diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py
index b40458482..6714295d2 100644
--- a/src/cpu/simple/BaseSimpleCPU.py
+++ b/src/cpu/simple/BaseSimpleCPU.py
@@ -30,9 +30,10 @@ from __future__ import print_function
 
 from m5.defines import buildEnv
 from m5.params import *
-from BaseCPU import BaseCPU
-from DummyChecker import DummyChecker
-from BranchPredictor import *
+
+from m5.objects.BaseCPU import BaseCPU
+from m5.objects.DummyChecker import DummyChecker
+from m5.objects.BranchPredictor import *
 
 class BaseSimpleCPU(BaseCPU):
     type = 'BaseSimpleCPU'
@@ -41,7 +42,7 @@ class BaseSimpleCPU(BaseCPU):
 
     def addCheckerCpu(self):
         if buildEnv['TARGET_ISA'] in ['arm']:
-            from ArmTLB import ArmTLB
+            from m5.objects.ArmTLB import ArmTLB
 
             self.checker = DummyChecker(workload = self.workload)
             self.checker.itb = ArmTLB(size = self.itb.size)
diff --git a/src/cpu/simple/NonCachingSimpleCPU.py b/src/cpu/simple/NonCachingSimpleCPU.py
index 2905a79ac..3fe0e02c3 100644
--- a/src/cpu/simple/NonCachingSimpleCPU.py
+++ b/src/cpu/simple/NonCachingSimpleCPU.py
@@ -36,7 +36,7 @@
 # Authors: Andreas Sandberg
 
 from m5.params import *
-from AtomicSimpleCPU import AtomicSimpleCPU
+from m5.objects.AtomicSimpleCPU import AtomicSimpleCPU
 
 class NonCachingSimpleCPU(AtomicSimpleCPU):
     """Simple CPU model based on the atomic CPU. Unlike the atomic CPU,
diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/TimingSimpleCPU.py
index 25149eaa8..134c8bb35 100644
--- a/src/cpu/simple/TimingSimpleCPU.py
+++ b/src/cpu/simple/TimingSimpleCPU.py
@@ -27,7 +27,8 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from BaseSimpleCPU import BaseSimpleCPU
+
+from m5.objects.BaseSimpleCPU import BaseSimpleCPU
 
 class TimingSimpleCPU(BaseSimpleCPU):
     type = 'TimingSimpleCPU'
diff --git a/src/cpu/simple/probes/SimPoint.py b/src/cpu/simple/probes/SimPoint.py
index ac6ec0730..14766a791 100644
--- a/src/cpu/simple/probes/SimPoint.py
+++ b/src/cpu/simple/probes/SimPoint.py
@@ -36,7 +36,7 @@
 # Authors: Curtis Dunham
 
 from m5.params import *
-from Probe import ProbeListenerObject
+from m5.objects.Probe import ProbeListenerObject
 
 class SimPoint(ProbeListenerObject):
     """Probe for collecting SimPoint Basic Block Vectors (BBVs)."""
diff --git a/src/cpu/testers/directedtest/RubyDirectedTester.py b/src/cpu/testers/directedtest/RubyDirectedTester.py
index df1205659..9f90c9b41 100644
--- a/src/cpu/testers/directedtest/RubyDirectedTester.py
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.py
@@ -27,10 +27,11 @@
 # Authors: Brad Beckmann
 
 from m5.SimObject import SimObject
-from MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 
+from m5.objects.MemObject import MemObject
+
 class DirectedGenerator(SimObject):
     type = 'DirectedGenerator'
     abstract = True
diff --git a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
index 261e643c1..4c7772348 100644
--- a/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
+++ b/src/cpu/testers/garnet_synthetic_traffic/GarnetSyntheticTraffic.py
@@ -26,7 +26,7 @@
 #
 # Authors: Tushar Krishna
 
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 
diff --git a/src/cpu/testers/memtest/MemTest.py b/src/cpu/testers/memtest/MemTest.py
index d09537639..5585b1f70 100644
--- a/src/cpu/testers/memtest/MemTest.py
+++ b/src/cpu/testers/memtest/MemTest.py
@@ -38,11 +38,11 @@
 #
 # Authors: Nathan Binkert
 #          Andreas Hansson
-
-from MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 
+from m5.objects.MemObject import MemObject
+
 class MemTest(MemObject):
     type = 'MemTest'
     cxx_header = "cpu/testers/memtest/memtest.hh"
diff --git a/src/cpu/testers/rubytest/RubyTester.py b/src/cpu/testers/rubytest/RubyTester.py
index f12485566..2ac1697fd 100644
--- a/src/cpu/testers/rubytest/RubyTester.py
+++ b/src/cpu/testers/rubytest/RubyTester.py
@@ -25,11 +25,11 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 #
-
-from MemObject import MemObject
 from m5.params import *
 from m5.proxy import *
 
+from m5.objects.MemObject import MemObject
+
 class RubyTester(MemObject):
     type = 'RubyTester'
     cxx_header = "cpu/testers/rubytest/RubyTester.hh"
diff --git a/src/cpu/testers/traffic_gen/BaseTrafficGen.py b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
index dbe0c848b..94e3319d5 100644
--- a/src/cpu/testers/traffic_gen/BaseTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/BaseTrafficGen.py
@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 # Types of Stream Generators.
 # Those are orthogonal to the other generators in the TrafficGen
diff --git a/src/cpu/testers/traffic_gen/PyTrafficGen.py b/src/cpu/testers/traffic_gen/PyTrafficGen.py
index c29ad0a3b..c8829ecc8 100644
--- a/src/cpu/testers/traffic_gen/PyTrafficGen.py
+++ b/src/cpu/testers/traffic_gen/PyTrafficGen.py
@@ -37,7 +37,8 @@
 
 from m5.defines import buildEnv
 from m5.SimObject import *
-from BaseTrafficGen import *
+
+from m5.objects.BaseTrafficGen import *
 
 class PyTrafficGen(BaseTrafficGen):
     type = 'PyTrafficGen'
diff --git a/src/cpu/testers/traffic_gen/TrafficGen.py b/src/cpu/testers/traffic_gen/TrafficGen.py
index f1e094821..af6c4902c 100644
--- a/src/cpu/testers/traffic_gen/TrafficGen.py
+++ b/src/cpu/testers/traffic_gen/TrafficGen.py
@@ -38,7 +38,7 @@
 #          Sascha Bischoff
 
 from m5.params import *
-from BaseTrafficGen import *
+from m5.objects.BaseTrafficGen import *
 
 # The behaviour of this traffic generator is specified in a
 # configuration file, and this file describes a state transition graph
diff --git a/src/cpu/trace/TraceCPU.py b/src/cpu/trace/TraceCPU.py
index e108b1a50..0838dd8c4 100644
--- a/src/cpu/trace/TraceCPU.py
+++ b/src/cpu/trace/TraceCPU.py
@@ -38,7 +38,7 @@
 #          Thomas Grass
 
 from m5.params import *
-from BaseCPU import BaseCPU
+from m5.objects.BaseCPU import BaseCPU
 
 class TraceCPU(BaseCPU):
     """Trace CPU model which replays traces generated in a prior simulation
diff --git a/src/dev/BadDevice.py b/src/dev/BadDevice.py
index d6d68f86d..faaa265d0 100644
--- a/src/dev/BadDevice.py
+++ b/src/dev/BadDevice.py
@@ -27,7 +27,7 @@
 # Authors: Nathan Binkert
 
 from m5.params import *
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
 
 class BadDevice(BasicPioDevice):
     type = 'BadDevice'
diff --git a/src/dev/Device.py b/src/dev/Device.py
index e4656078d..c137ce66d 100644
--- a/src/dev/Device.py
+++ b/src/dev/Device.py
@@ -42,7 +42,8 @@
 from m5.params import *
 from m5.proxy import *
 from m5.util.fdthelper import *
-from MemObject import MemObject
+
+from m5.objects.MemObject import MemObject
 
 class PioDevice(MemObject):
     type = 'PioDevice'
diff --git a/src/dev/Platform.py b/src/dev/Platform.py
index b182acfd6..c6b6fdebe 100644
--- a/src/dev/Platform.py
+++ b/src/dev/Platform.py
@@ -29,6 +29,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
+
 class Platform(SimObject):
     type = 'Platform'
     abstract = True
diff --git a/src/dev/alpha/AlphaBackdoor.py b/src/dev/alpha/AlphaBackdoor.py
index 29372bce8..6355269fc 100644
--- a/src/dev/alpha/AlphaBackdoor.py
+++ b/src/dev/alpha/AlphaBackdoor.py
@@ -29,7 +29,8 @@
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
+
+from m5.objects.Device import BasicPioDevice
 
 class AlphaBackdoor(BasicPioDevice):
     type = 'AlphaBackdoor'
diff --git a/src/dev/alpha/Tsunami.py b/src/dev/alpha/Tsunami.py
index f807e946f..e5b8885ad 100644
--- a/src/dev/alpha/Tsunami.py
+++ b/src/dev/alpha/Tsunami.py
@@ -28,12 +28,12 @@
 
 from m5.params import *
 from m5.proxy import *
-from BadDevice import BadDevice
-from AlphaBackdoor import AlphaBackdoor
-from Device import BasicPioDevice, IsaFake, BadAddr
-from PciHost import GenericPciHost
-from Platform import Platform
-from Uart import Uart8250
+from m5.objects.BadDevice import BadDevice
+from m5.objects.AlphaBackdoor import AlphaBackdoor
+from m5.objects.Device import BasicPioDevice, IsaFake, BadAddr
+from m5.objects.PciHost import GenericPciHost
+from m5.objects.Platform import Platform
+from m5.objects.Uart import Uart8250
 
 class TsunamiCChip(BasicPioDevice):
     type = 'TsunamiCChip'
diff --git a/src/dev/arm/EnergyCtrl.py b/src/dev/arm/EnergyCtrl.py
index 571f94178..d007ea7b4 100644
--- a/src/dev/arm/EnergyCtrl.py
+++ b/src/dev/arm/EnergyCtrl.py
@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.SimObject import SimObject
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
 from m5.proxy import *
 from m5.util.fdthelper import *
 
diff --git a/src/dev/arm/FlashDevice.py b/src/dev/arm/FlashDevice.py
index ed3b9d04d..a4f2e34ed 100644
--- a/src/dev/arm/FlashDevice.py
+++ b/src/dev/arm/FlashDevice.py
@@ -38,7 +38,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from AbstractNVM import *
+
+from m5.objects.AbstractNVM import *
 
 #Distribution of the data.
 #sequential: sequential (address n+1 is likely to be on the same plane as n)
diff --git a/src/dev/arm/Gic.py b/src/dev/arm/Gic.py
index 0e0aa89fe..29535e4e9 100644
--- a/src/dev/arm/Gic.py
+++ b/src/dev/arm/Gic.py
@@ -40,8 +40,8 @@ from m5.proxy import *
 from m5.util.fdthelper import *
 from m5.SimObject import SimObject
 
-from Device import PioDevice
-from Platform import Platform
+from m5.objects.Device import PioDevice
+from m5.objects.Platform import Platform
 
 class BaseGic(PioDevice):
     type = 'BaseGic'
diff --git a/src/dev/arm/NoMali.py b/src/dev/arm/NoMali.py
index 4272f90d0..31509e62d 100644
--- a/src/dev/arm/NoMali.py
+++ b/src/dev/arm/NoMali.py
@@ -36,8 +36,9 @@
 # Authors: Andreas Sandberg
 
 from m5.params import *
-from Device import BasicPioDevice
-from Gic import *
+
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Gic import *
 
 class NoMaliGpuType(Enum): vals = [
     'T60x',
diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index d7ce9eba0..af19f3bbd 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -45,31 +45,32 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 from m5.util.fdthelper import *
-from ClockDomain import ClockDomain
-from VoltageDomain import VoltageDomain
-from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
-from PciHost import *
-from Ethernet import NSGigE, IGbE_igb, IGbE_e1000
-from Ide import *
-from Platform import Platform
-from Terminal import Terminal
-from Uart import Uart
-from SimpleMemory import SimpleMemory
-from Gic import *
-from EnergyCtrl import EnergyCtrl
-from ClockedObject import ClockedObject
-from ClockDomain import SrcClockDomain
-from SubSystem import SubSystem
-from Graphics import ImageFormat
-from ClockedObject import ClockedObject
-from PS2 import *
-from VirtIOMMIO import MmioVirtIO
+from m5.objects.ClockDomain import ClockDomain
+from m5.objects.VoltageDomain import VoltageDomain
+from m5.objects.Device import \
+    BasicPioDevice, PioDevice, IsaFake, BadAddr, DmaDevice
+from m5.objects.PciHost import *
+from m5.objects.Ethernet import NSGigE, IGbE_igb, IGbE_e1000
+from m5.objects.Ide import *
+from m5.objects.Platform import Platform
+from m5.objects.Terminal import Terminal
+from m5.objects.Uart import Uart
+from m5.objects.SimpleMemory import SimpleMemory
+from m5.objects.Gic import *
+from m5.objects.EnergyCtrl import EnergyCtrl
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.ClockDomain import SrcClockDomain
+from m5.objects.SubSystem import SubSystem
+from m5.objects.Graphics import ImageFormat
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.PS2 import *
+from m5.objects.VirtIOMMIO import MmioVirtIO
 
 # Platforms with KVM support should generally use in-kernel GIC
 # emulation. Use a GIC model that automatically switches between
 # gem5's GIC model and KVM's GIC model if KVM is available.
 try:
-    from KvmGic import MuxingKvmGic
+    from m5.objects.KvmGic import MuxingKvmGic
     kvm_gicv2_class = MuxingKvmGic
 except ImportError:
     # KVM support wasn't compiled into gem5. Fallback to a
diff --git a/src/dev/arm/UFSHostDevice.py b/src/dev/arm/UFSHostDevice.py
index f9369ebc9..3c7dda722 100644
--- a/src/dev/arm/UFSHostDevice.py
+++ b/src/dev/arm/UFSHostDevice.py
@@ -38,8 +38,8 @@
 import sys
 from m5.params import *
 from m5.proxy import *
-from Device import DmaDevice
-from AbstractNVM import *
+from m5.objects.Device import DmaDevice
+from m5.objects.AbstractNVM import *
 
 class UFSHostDevice(DmaDevice):
     type = 'UFSHostDevice'
diff --git a/src/dev/arm/VirtIOMMIO.py b/src/dev/arm/VirtIOMMIO.py
index 2c95ef3ce..e91fb8156 100644
--- a/src/dev/arm/VirtIOMMIO.py
+++ b/src/dev/arm/VirtIOMMIO.py
@@ -41,9 +41,9 @@ from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
 
-from Device import BasicPioDevice
-from Gic import ArmInterruptPin
-from VirtIO import VirtIODeviceBase, VirtIODummyDevice
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Gic import ArmInterruptPin
+from m5.objects.VirtIO import VirtIODeviceBase, VirtIODummyDevice
 
 class MmioVirtIO(BasicPioDevice):
     type = 'MmioVirtIO'
diff --git a/src/dev/i2c/I2C.py b/src/dev/i2c/I2C.py
index f249d0648..0d1b2a97a 100644
--- a/src/dev/i2c/I2C.py
+++ b/src/dev/i2c/I2C.py
@@ -37,7 +37,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
 
 class I2CDevice(SimObject):
     type = 'I2CDevice'
diff --git a/src/dev/mips/Malta.py b/src/dev/mips/Malta.py
index 920b5fe94..cb15dd9aa 100755
--- a/src/dev/mips/Malta.py
+++ b/src/dev/mips/Malta.py
@@ -29,10 +29,10 @@
 from m5.params import *
 from m5.proxy import *
 
-from BadDevice import BadDevice
-from Device import BasicPioDevice
-from Platform import Platform
-from Uart import Uart8250
+from m5.objects.BadDevice import BadDevice
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Platform import Platform
+from m5.objects.Uart import Uart8250
 
 class MaltaCChip(BasicPioDevice):
     type = 'MaltaCChip'
diff --git a/src/dev/net/Ethernet.py b/src/dev/net/Ethernet.py
index 71665c564..7c3c766bc 100644
--- a/src/dev/net/Ethernet.py
+++ b/src/dev/net/Ethernet.py
@@ -42,7 +42,7 @@ from m5.defines import buildEnv
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from PciDevice import PciDevice
+from m5.objects.PciDevice import PciDevice
 
 class EtherObject(SimObject):
     type = 'EtherObject'
diff --git a/src/dev/pci/CopyEngine.py b/src/dev/pci/CopyEngine.py
index f1b9df1b9..1570365a6 100644
--- a/src/dev/pci/CopyEngine.py
+++ b/src/dev/pci/CopyEngine.py
@@ -29,7 +29,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from PciDevice import PciDevice
+
+from m5.objects.PciDevice import PciDevice
 
 class CopyEngine(PciDevice):
     type = 'CopyEngine'
diff --git a/src/dev/pci/PciDevice.py b/src/dev/pci/PciDevice.py
index 21e6edf62..3f41de181 100644
--- a/src/dev/pci/PciDevice.py
+++ b/src/dev/pci/PciDevice.py
@@ -41,8 +41,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from Device import DmaDevice
-from PciHost import PciHost
+from m5.objects.Device import DmaDevice
+from m5.objects.PciHost import PciHost
 
 class PciDevice(DmaDevice):
     type = 'PciDevice'
diff --git a/src/dev/pci/PciHost.py b/src/dev/pci/PciHost.py
index 28405c198..607b5f392 100644
--- a/src/dev/pci/PciHost.py
+++ b/src/dev/pci/PciHost.py
@@ -39,8 +39,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from Device import PioDevice
-from Platform import Platform
+from m5.objects.Device import PioDevice
+from m5.objects.Platform import Platform
 
 class PciHost(PioDevice):
     type = 'PciHost'
diff --git a/src/dev/serial/Terminal.py b/src/dev/serial/Terminal.py
index 864491617..be7fbdc91 100644
--- a/src/dev/serial/Terminal.py
+++ b/src/dev/serial/Terminal.py
@@ -29,7 +29,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from Serial import SerialDevice
+
+from m5.objects.Serial import SerialDevice
 
 class Terminal(SerialDevice):
     type = 'Terminal'
diff --git a/src/dev/serial/Uart.py b/src/dev/serial/Uart.py
index 029d46c4f..a850f1534 100644
--- a/src/dev/serial/Uart.py
+++ b/src/dev/serial/Uart.py
@@ -40,8 +40,9 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
-from Serial import SerialDevice
+
+from m5.objects.Device import BasicPioDevice
+from m5.objects.Serial import SerialDevice
 
 class Uart(BasicPioDevice):
     type = 'Uart'
diff --git a/src/dev/sparc/T1000.py b/src/dev/sparc/T1000.py
index 99f083450..d2040914c 100644
--- a/src/dev/sparc/T1000.py
+++ b/src/dev/sparc/T1000.py
@@ -28,10 +28,11 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
-from Platform import Platform
-from Terminal import Terminal
-from Uart import Uart8250
+
+from m5.objects.Device import BasicPioDevice, PioDevice, IsaFake, BadAddr
+from m5.objects.Platform import Platform
+from m5.objects.Terminal import Terminal
+from m5.objects.Uart import Uart8250
 
 
 class MmDisk(BasicPioDevice):
diff --git a/src/dev/storage/Ide.py b/src/dev/storage/Ide.py
index fc3f356f0..65571b167 100644
--- a/src/dev/storage/Ide.py
+++ b/src/dev/storage/Ide.py
@@ -28,7 +28,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from PciDevice import PciDevice
+from m5.objects.PciDevice import PciDevice
 
 class IdeID(Enum): vals = ['master', 'slave']
 
diff --git a/src/dev/virtio/VirtIO.py b/src/dev/virtio/VirtIO.py
index bf050fd47..fcb9235ec 100644
--- a/src/dev/virtio/VirtIO.py
+++ b/src/dev/virtio/VirtIO.py
@@ -40,8 +40,8 @@
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
-from Device import PioDevice
-from PciDevice import PciDevice
+from m5.objects.Device import PioDevice
+from m5.objects.PciDevice import PciDevice
 
 
 class VirtIODeviceBase(SimObject):
diff --git a/src/dev/virtio/VirtIO9P.py b/src/dev/virtio/VirtIO9P.py
index 623403d1d..02e50f301 100644
--- a/src/dev/virtio/VirtIO9P.py
+++ b/src/dev/virtio/VirtIO9P.py
@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from VirtIO import VirtIODeviceBase
+from m5.objects.VirtIO import VirtIODeviceBase
 
 class VirtIO9PBase(VirtIODeviceBase):
     type = 'VirtIO9PBase'
diff --git a/src/dev/virtio/VirtIOBlock.py b/src/dev/virtio/VirtIOBlock.py
index 1add847c7..5f68c00c2 100644
--- a/src/dev/virtio/VirtIOBlock.py
+++ b/src/dev/virtio/VirtIOBlock.py
@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from VirtIO import VirtIODeviceBase
+from m5.objects.VirtIO import VirtIODeviceBase
 
 class VirtIOBlock(VirtIODeviceBase):
     type = 'VirtIOBlock'
diff --git a/src/dev/virtio/VirtIOConsole.py b/src/dev/virtio/VirtIOConsole.py
index bce5e1de2..142bbc69e 100644
--- a/src/dev/virtio/VirtIOConsole.py
+++ b/src/dev/virtio/VirtIOConsole.py
@@ -39,8 +39,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from VirtIO import VirtIODeviceBase
-from Serial import SerialDevice
+from m5.objects.VirtIO import VirtIODeviceBase
+from m5.objects.Serial import SerialDevice
 
 class VirtIOConsole(VirtIODeviceBase):
     type = 'VirtIOConsole'
diff --git a/src/dev/x86/Cmos.py b/src/dev/x86/Cmos.py
index c0b2be58a..9bc395cb2 100644
--- a/src/dev/x86/Cmos.py
+++ b/src/dev/x86/Cmos.py
@@ -28,8 +28,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSourcePin
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSourcePin
 
 class Cmos(BasicPioDevice):
     type = 'Cmos'
diff --git a/src/dev/x86/I8042.py b/src/dev/x86/I8042.py
index 43e70d6e4..5615d3e9f 100644
--- a/src/dev/x86/I8042.py
+++ b/src/dev/x86/I8042.py
@@ -28,9 +28,9 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSourcePin
-from PS2 import *
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSourcePin
+from m5.objects.PS2 import *
 
 class I8042(BasicPioDevice):
     type = 'I8042'
diff --git a/src/dev/x86/I82094AA.py b/src/dev/x86/I82094AA.py
index 7e71cdfc1..d848904f0 100644
--- a/src/dev/x86/I82094AA.py
+++ b/src/dev/x86/I82094AA.py
@@ -28,8 +28,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSinkPin
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSinkPin
 
 class I82094AA(BasicPioDevice):
     type = 'I82094AA'
diff --git a/src/dev/x86/I8237.py b/src/dev/x86/I8237.py
index a4c5e3ad5..22e29ba5f 100644
--- a/src/dev/x86/I8237.py
+++ b/src/dev/x86/I8237.py
@@ -28,7 +28,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
 
 class I8237(BasicPioDevice):
     type = 'I8237'
diff --git a/src/dev/x86/I8254.py b/src/dev/x86/I8254.py
index 574dd81c2..f0a6b2222 100644
--- a/src/dev/x86/I8254.py
+++ b/src/dev/x86/I8254.py
@@ -28,8 +28,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSourcePin
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSourcePin
 
 class I8254(BasicPioDevice):
     type = 'I8254'
diff --git a/src/dev/x86/I8259.py b/src/dev/x86/I8259.py
index 4403c3f53..7066cb846 100644
--- a/src/dev/x86/I8259.py
+++ b/src/dev/x86/I8259.py
@@ -28,8 +28,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
-from X86IntPin import X86IntSourcePin, X86IntSinkPin
+from m5.objects.Device import BasicPioDevice
+from m5.objects.X86IntPin import X86IntSourcePin, X86IntSinkPin
 
 class X86I8259CascadeMode(Enum):
     map = {'I8259Master' : 0,
diff --git a/src/dev/x86/Pc.py b/src/dev/x86/Pc.py
index 4d20214ad..0e75a2e51 100644
--- a/src/dev/x86/Pc.py
+++ b/src/dev/x86/Pc.py
@@ -29,12 +29,12 @@
 from m5.params import *
 from m5.proxy import *
 
-from Device import IsaFake
-from Platform import Platform
-from SouthBridge import SouthBridge
-from Terminal import Terminal
-from Uart import Uart8250
-from PciHost import GenericPciHost
+from m5.objects.Device import IsaFake
+from m5.objects.Platform import Platform
+from m5.objects.SouthBridge import SouthBridge
+from m5.objects.Terminal import Terminal
+from m5.objects.Uart import Uart8250
+from m5.objects.PciHost import GenericPciHost
 
 def x86IOAddress(port):
     IO_address_space_base = 0x8000000000000000
diff --git a/src/dev/x86/PcSpeaker.py b/src/dev/x86/PcSpeaker.py
index f1c23157b..079a3d8da 100644
--- a/src/dev/x86/PcSpeaker.py
+++ b/src/dev/x86/PcSpeaker.py
@@ -28,7 +28,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from Device import BasicPioDevice
+from m5.objects.Device import BasicPioDevice
 
 class PcSpeaker(BasicPioDevice):
     type = 'PcSpeaker'
diff --git a/src/dev/x86/SouthBridge.py b/src/dev/x86/SouthBridge.py
index 704656594..7029eb358 100644
--- a/src/dev/x86/SouthBridge.py
+++ b/src/dev/x86/SouthBridge.py
@@ -28,15 +28,15 @@
 
 from m5.params import *
 from m5.proxy import *
-from Cmos import Cmos
-from I8042 import I8042
-from I82094AA import I82094AA
-from I8237 import I8237
-from I8254 import I8254
-from I8259 import I8259
-from Ide import IdeController
-from PcSpeaker import PcSpeaker
-from X86IntPin import X86IntLine
+from m5.objects.Cmos import Cmos
+from m5.objects.I8042 import I8042
+from m5.objects.I82094AA import I82094AA
+from m5.objects.I8237 import I8237
+from m5.objects.I8254 import I8254
+from m5.objects.I8259 import I8259
+from m5.objects.Ide import IdeController
+from m5.objects.PcSpeaker import PcSpeaker
+from m5.objects.X86IntPin import X86IntLine
 from m5.SimObject import SimObject
 
 def x86IOAddress(port):
diff --git a/src/gpu-compute/GPU.py b/src/gpu-compute/GPU.py
index 0cb9e76a4..9eb662abc 100644
--- a/src/gpu-compute/GPU.py
+++ b/src/gpu-compute/GPU.py
@@ -33,16 +33,17 @@
 #  Author: Steve Reinhardt
 #
 
-from ClockedObject import ClockedObject
-from Device import DmaDevice
 from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from MemObject import MemObject
-from Process import EmulatedDriver
-from Bridge import Bridge
-from LdsState import LdsState
+
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.Device import DmaDevice
+from m5.objects.MemObject import MemObject
+from m5.objects.Process import EmulatedDriver
+from m5.objects.Bridge import Bridge
+from m5.objects.LdsState import LdsState
 
 class PrefetchType(Enum): vals = [
     'PF_CU',
diff --git a/src/gpu-compute/LdsState.py b/src/gpu-compute/LdsState.py
index 5732edbe3..f1f8cd18a 100644
--- a/src/gpu-compute/LdsState.py
+++ b/src/gpu-compute/LdsState.py
@@ -35,7 +35,7 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class LdsState(MemObject):
     type = 'LdsState'
diff --git a/src/learning_gem5/part2/SimpleCache.py b/src/learning_gem5/part2/SimpleCache.py
index c0cdef9b8..d0ad261d8 100644
--- a/src/learning_gem5/part2/SimpleCache.py
+++ b/src/learning_gem5/part2/SimpleCache.py
@@ -29,7 +29,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class SimpleCache(MemObject):
     type = 'SimpleCache'
diff --git a/src/learning_gem5/part2/SimpleMemobj.py b/src/learning_gem5/part2/SimpleMemobj.py
index 414e2c7f6..e1fb95e22 100644
--- a/src/learning_gem5/part2/SimpleMemobj.py
+++ b/src/learning_gem5/part2/SimpleMemobj.py
@@ -28,7 +28,7 @@
 # Authors: Jason Lowe-Power
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class SimpleMemobj(MemObject):
     type = 'SimpleMemobj'
diff --git a/src/mem/AbstractMemory.py b/src/mem/AbstractMemory.py
index d5b34bbd0..5bffc30af 100644
--- a/src/mem/AbstractMemory.py
+++ b/src/mem/AbstractMemory.py
@@ -40,7 +40,7 @@
 #          Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class AbstractMemory(MemObject):
     type = 'AbstractMemory'
diff --git a/src/mem/AddrMapper.py b/src/mem/AddrMapper.py
index f6e943ed1..a1ddaeb7a 100644
--- a/src/mem/AddrMapper.py
+++ b/src/mem/AddrMapper.py
@@ -36,7 +36,7 @@
 # Authors: Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 # An address mapper changes the packet addresses in going from the
 # slave port side of the mapper to the master port side. When the
diff --git a/src/mem/Bridge.py b/src/mem/Bridge.py
index e488871a4..34af552e3 100644
--- a/src/mem/Bridge.py
+++ b/src/mem/Bridge.py
@@ -40,7 +40,7 @@
 #          Andreas Hansson
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class Bridge(MemObject):
     type = 'Bridge'
diff --git a/src/mem/CommMonitor.py b/src/mem/CommMonitor.py
index aa8da62ed..fc53ef1f0 100644
--- a/src/mem/CommMonitor.py
+++ b/src/mem/CommMonitor.py
@@ -38,8 +38,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from System import System
+from m5.objects.MemObject import MemObject
+from m5.objects.System import System
 
 # The communication monitor will most typically be used in combination
 # with periodic dumping and resetting of stats using schedStatEvent
diff --git a/src/mem/DRAMCtrl.py b/src/mem/DRAMCtrl.py
index fa04c9f39..93ea7d56f 100644
--- a/src/mem/DRAMCtrl.py
+++ b/src/mem/DRAMCtrl.py
@@ -46,8 +46,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from AbstractMemory import *
-from QoSMemCtrl import *
+from m5.objects.AbstractMemory import *
+from m5.objects.QoSMemCtrl import *
 
 # Enum for memory scheduling algorithms, currently First-Come
 # First-Served and a First-Row Hit then First-Come First-Served
diff --git a/src/mem/ExternalMaster.py b/src/mem/ExternalMaster.py
index 44b49971a..883e27727 100644
--- a/src/mem/ExternalMaster.py
+++ b/src/mem/ExternalMaster.py
@@ -39,7 +39,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class ExternalMaster(MemObject):
     type = 'ExternalMaster'
diff --git a/src/mem/ExternalSlave.py b/src/mem/ExternalSlave.py
index 15f529de6..7be5fd8a9 100644
--- a/src/mem/ExternalSlave.py
+++ b/src/mem/ExternalSlave.py
@@ -36,7 +36,7 @@
 # Authors: Andrew Bardsley
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class ExternalSlave(MemObject):
     type = 'ExternalSlave'
diff --git a/src/mem/HMCController.py b/src/mem/HMCController.py
index e52438e98..bb6171f17 100644
--- a/src/mem/HMCController.py
+++ b/src/mem/HMCController.py
@@ -39,7 +39,7 @@
 # Authors: Erfan Azarkhish
 
 from m5.params import *
-from XBar import *
+from m5.objects.XBar import *
 
 # References:
 # [1] http://www.open-silicon.com/open-silicon-ips/hmc/
diff --git a/src/mem/MemChecker.py b/src/mem/MemChecker.py
index 5126f4364..7460cd13b 100644
--- a/src/mem/MemChecker.py
+++ b/src/mem/MemChecker.py
@@ -35,7 +35,7 @@
 #
 # Authors: Marco Elver
 
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 from m5.SimObject import SimObject
 from m5.params import *
 from m5.proxy import *
diff --git a/src/mem/MemDelay.py b/src/mem/MemDelay.py
index b48866815..415cef4ce 100644
--- a/src/mem/MemDelay.py
+++ b/src/mem/MemDelay.py
@@ -36,7 +36,7 @@
 # Authors: Andreas Sandberg
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class MemDelay(MemObject):
     type = 'MemDelay'
diff --git a/src/mem/MemObject.py b/src/mem/MemObject.py
index 0827218aa..42d561d73 100644
--- a/src/mem/MemObject.py
+++ b/src/mem/MemObject.py
@@ -26,7 +26,7 @@
 #
 # Authors: Ron Dreslinski
 
-from ClockedObject import ClockedObject
+from m5.objects.ClockedObject import ClockedObject
 
 class MemObject(ClockedObject):
     type = 'MemObject'
diff --git a/src/mem/SerialLink.py b/src/mem/SerialLink.py
index fd9b0ff6b..02dcd4c7e 100644
--- a/src/mem/SerialLink.py
+++ b/src/mem/SerialLink.py
@@ -42,7 +42,7 @@
 #          Erfan Azarkhish
 
 from m5.params import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 # SerialLink is a simple variation of the Bridge class, with the ability to
 # account for the latency of packet serialization.
diff --git a/src/mem/SimpleMemory.py b/src/mem/SimpleMemory.py
index 0a90eaa7c..34cc186f4 100644
--- a/src/mem/SimpleMemory.py
+++ b/src/mem/SimpleMemory.py
@@ -40,7 +40,7 @@
 #          Andreas Hansson
 
 from m5.params import *
-from AbstractMemory import *
+from m5.objects.AbstractMemory import *
 
 class SimpleMemory(AbstractMemory):
     type = 'SimpleMemory'
diff --git a/src/mem/XBar.py b/src/mem/XBar.py
index 655d9808a..c9f35f3e5 100644
--- a/src/mem/XBar.py
+++ b/src/mem/XBar.py
@@ -39,12 +39,13 @@
 # Authors: Nathan Binkert
 #          Andreas Hansson
 
-from MemObject import MemObject
-from System import System
+from m5.objects.System import System
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
 
+from m5.objects.MemObject import MemObject
+
 class BaseXBar(MemObject):
     type = 'BaseXBar'
     abstract = True
diff --git a/src/mem/cache/Cache.py b/src/mem/cache/Cache.py
index 8ffab911b..0a590c2ca 100644
--- a/src/mem/cache/Cache.py
+++ b/src/mem/cache/Cache.py
@@ -42,10 +42,11 @@
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from MemObject import MemObject
-from Prefetcher import BasePrefetcher
-from ReplacementPolicies import *
-from Tags import *
+
+from m5.objects.MemObject import MemObject
+from m5.objects.Prefetcher import BasePrefetcher
+from m5.objects.ReplacementPolicies import *
+from m5.objects.Tags import *
 
 
 # Enum for cache clusivity, currently mostly inclusive or mostly
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index 082590853..827a66b0f 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -39,12 +39,13 @@
 # Authors: Ron Dreslinski
 #          Mitch Hayenga
 
-from ClockedObject import ClockedObject
-from IndexingPolicies import *
 from m5.SimObject import *
 from m5.params import *
 from m5.proxy import *
-from ReplacementPolicies import *
+
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.IndexingPolicies import *
+from m5.objects.ReplacementPolicies import *
 
 class HWPProbeEvent(object):
     def __init__(self, prefetcher, obj, *listOfNames):
diff --git a/src/mem/cache/tags/Tags.py b/src/mem/cache/tags/Tags.py
index f2658f4f8..9ac240d13 100644
--- a/src/mem/cache/tags/Tags.py
+++ b/src/mem/cache/tags/Tags.py
@@ -37,8 +37,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from ClockedObject import ClockedObject
-from IndexingPolicies import *
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.IndexingPolicies import *
 
 class BaseTags(ClockedObject):
     type = 'BaseTags'
diff --git a/src/mem/probes/MemFootprintProbe.py b/src/mem/probes/MemFootprintProbe.py
index 7a6551207..64b79fe16 100644
--- a/src/mem/probes/MemFootprintProbe.py
+++ b/src/mem/probes/MemFootprintProbe.py
@@ -38,7 +38,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from BaseMemProbe import BaseMemProbe
+
+from m5.objects.BaseMemProbe import BaseMemProbe
 
 class MemFootprintProbe(BaseMemProbe):
     type = "MemFootprintProbe"
diff --git a/src/mem/probes/MemTraceProbe.py b/src/mem/probes/MemTraceProbe.py
index 8daf94dbd..9dfd0eb51 100644
--- a/src/mem/probes/MemTraceProbe.py
+++ b/src/mem/probes/MemTraceProbe.py
@@ -37,7 +37,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from BaseMemProbe import BaseMemProbe
+from m5.objects.BaseMemProbe import BaseMemProbe
 
 class MemTraceProbe(BaseMemProbe):
     type = 'MemTraceProbe'
diff --git a/src/mem/probes/StackDistProbe.py b/src/mem/probes/StackDistProbe.py
index 431e86463..89a752d74 100644
--- a/src/mem/probes/StackDistProbe.py
+++ b/src/mem/probes/StackDistProbe.py
@@ -38,7 +38,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from BaseMemProbe import BaseMemProbe
+from m5.objects.BaseMemProbe import BaseMemProbe
 
 class StackDistProbe(BaseMemProbe):
     type = 'StackDistProbe'
diff --git a/src/mem/qos/QoSMemCtrl.py b/src/mem/qos/QoSMemCtrl.py
index 185856553..dbf881ca0 100644
--- a/src/mem/qos/QoSMemCtrl.py
+++ b/src/mem/qos/QoSMemCtrl.py
@@ -36,8 +36,8 @@
 # Authors: Matteo Andreozzi
 
 from m5.params import *
-from AbstractMemory import AbstractMemory
-from QoSTurnaround import *
+from m5.objects.AbstractMemory import AbstractMemory
+from m5.objects.QoSTurnaround import *
 
 # QoS Queue Selection policy used to select packets among same-QoS queues
 class QoSQPolicy(Enum): vals = ["fifo", "lifo", "lrg"]
diff --git a/src/mem/qos/QoSMemSinkCtrl.py b/src/mem/qos/QoSMemSinkCtrl.py
index 00f19ef7d..572cad5c4 100644
--- a/src/mem/qos/QoSMemSinkCtrl.py
+++ b/src/mem/qos/QoSMemSinkCtrl.py
@@ -36,7 +36,7 @@
 # Author: Matteo Andreozzi
 
 from m5.params import *
-from QoSMemCtrl import *
+from m5.objects.QoSMemCtrl import *
 
 class QoSMemSinkCtrl(QoSMemCtrl):
     type = 'QoSMemSinkCtrl'
diff --git a/src/mem/ruby/network/BasicRouter.py b/src/mem/ruby/network/BasicRouter.py
index 68a7b1d8b..e121048d4 100644
--- a/src/mem/ruby/network/BasicRouter.py
+++ b/src/mem/ruby/network/BasicRouter.py
@@ -28,7 +28,8 @@
 #          Brad Beckmann
 
 from m5.params import *
-from ClockedObject import ClockedObject
+
+from m5.objects.ClockedObject import ClockedObject
 
 class BasicRouter(ClockedObject):
     type = 'BasicRouter'
diff --git a/src/mem/ruby/network/Network.py b/src/mem/ruby/network/Network.py
index da0a788b5..861fd791d 100644
--- a/src/mem/ruby/network/Network.py
+++ b/src/mem/ruby/network/Network.py
@@ -28,8 +28,8 @@
 #          Brad Beckmann
 
 from m5.params import *
-from ClockedObject import ClockedObject
-from BasicLink import BasicLink
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.BasicLink import BasicLink
 
 class RubyNetwork(ClockedObject):
     type = 'RubyNetwork'
diff --git a/src/mem/ruby/network/garnet2.0/GarnetLink.py b/src/mem/ruby/network/garnet2.0/GarnetLink.py
index fc5632d49..0e7c4d1c6 100644
--- a/src/mem/ruby/network/garnet2.0/GarnetLink.py
+++ b/src/mem/ruby/network/garnet2.0/GarnetLink.py
@@ -30,8 +30,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from ClockedObject import ClockedObject
-from BasicLink import BasicIntLink, BasicExtLink
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.BasicLink import BasicIntLink, BasicExtLink
 
 class NetworkLink(ClockedObject):
     type = 'NetworkLink'
diff --git a/src/mem/ruby/network/garnet2.0/GarnetNetwork.py b/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
index 00213d60f..04c0ef46b 100644
--- a/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
+++ b/src/mem/ruby/network/garnet2.0/GarnetNetwork.py
@@ -30,9 +30,9 @@
 
 from m5.params import *
 from m5.proxy import *
-from Network import RubyNetwork
-from BasicRouter import BasicRouter
-from ClockedObject import ClockedObject
+from m5.objects.Network import RubyNetwork
+from m5.objects.BasicRouter import BasicRouter
+from m5.objects.ClockedObject import ClockedObject
 
 class GarnetNetwork(RubyNetwork):
     type = 'GarnetNetwork'
diff --git a/src/mem/ruby/network/simple/SimpleLink.py b/src/mem/ruby/network/simple/SimpleLink.py
index 716a21eec..2832b1c5c 100644
--- a/src/mem/ruby/network/simple/SimpleLink.py
+++ b/src/mem/ruby/network/simple/SimpleLink.py
@@ -30,7 +30,7 @@
 from m5.params import *
 from m5.proxy import *
 from m5.SimObject import SimObject
-from BasicLink import BasicIntLink, BasicExtLink
+from m5.objects.BasicLink import BasicIntLink, BasicExtLink
 
 class SimpleExtLink(BasicExtLink):
     type = 'SimpleExtLink'
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.py b/src/mem/ruby/network/simple/SimpleNetwork.py
index 3d6f7e854..e7a79492b 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.py
+++ b/src/mem/ruby/network/simple/SimpleNetwork.py
@@ -29,9 +29,10 @@
 
 from m5.params import *
 from m5.proxy import *
-from Network import RubyNetwork
-from BasicRouter import BasicRouter
-from MessageBuffer import MessageBuffer
+
+from m5.objects.Network import RubyNetwork
+from m5.objects.BasicRouter import BasicRouter
+from m5.objects.MessageBuffer import MessageBuffer
 
 class SimpleNetwork(RubyNetwork):
     type = 'SimpleNetwork'
diff --git a/src/mem/ruby/slicc_interface/Controller.py b/src/mem/ruby/slicc_interface/Controller.py
index 39a0ea912..0eb704916 100644
--- a/src/mem/ruby/slicc_interface/Controller.py
+++ b/src/mem/ruby/slicc_interface/Controller.py
@@ -41,7 +41,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class RubyController(MemObject):
     type = 'RubyController'
diff --git a/src/mem/ruby/structures/LRUReplacementPolicy.py b/src/mem/ruby/structures/LRUReplacementPolicy.py
index 2b4a263b7..9c36b5f51 100644
--- a/src/mem/ruby/structures/LRUReplacementPolicy.py
+++ b/src/mem/ruby/structures/LRUReplacementPolicy.py
@@ -31,7 +31,7 @@
 
 from m5.params import *
 from m5.SimObject import SimObject
-from ReplacementPolicy import ReplacementPolicy
+from m5.objects.ReplacementPolicy import ReplacementPolicy
 
 class LRUReplacementPolicy(ReplacementPolicy):
     type = 'LRUReplacementPolicy'
diff --git a/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py b/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
index d922007f5..2b892d47a 100644
--- a/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
+++ b/src/mem/ruby/structures/PseudoLRUReplacementPolicy.py
@@ -27,7 +27,7 @@
 #
 # Author: Derek Hower
 
-from ReplacementPolicy import ReplacementPolicy
+from m5.objects.ReplacementPolicy import ReplacementPolicy
 
 class PseudoLRUReplacementPolicy(ReplacementPolicy):
     type = 'PseudoLRUReplacementPolicy'
diff --git a/src/mem/ruby/structures/RubyCache.py b/src/mem/ruby/structures/RubyCache.py
index 9fc4726b0..cf8410c6d 100644
--- a/src/mem/ruby/structures/RubyCache.py
+++ b/src/mem/ruby/structures/RubyCache.py
@@ -29,7 +29,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from PseudoLRUReplacementPolicy import PseudoLRUReplacementPolicy
+from m5.objects.PseudoLRUReplacementPolicy import PseudoLRUReplacementPolicy
 from m5.SimObject import SimObject
 
 class RubyCache(SimObject):
diff --git a/src/mem/ruby/structures/RubyPrefetcher.py b/src/mem/ruby/structures/RubyPrefetcher.py
index 18bb3dc69..00a933d8c 100644
--- a/src/mem/ruby/structures/RubyPrefetcher.py
+++ b/src/mem/ruby/structures/RubyPrefetcher.py
@@ -27,10 +27,11 @@
 # Authors: Nilay Vaish
 
 from m5.SimObject import SimObject
-from System import System
 from m5.params import *
 from m5.proxy import *
 
+from m5.objects.System import System
+
 class Prefetcher(SimObject):
     type = 'Prefetcher'
     cxx_class = 'Prefetcher'
diff --git a/src/mem/ruby/system/GPUCoalescer.py b/src/mem/ruby/system/GPUCoalescer.py
index 87ee3b221..ec6429342 100644
--- a/src/mem/ruby/system/GPUCoalescer.py
+++ b/src/mem/ruby/system/GPUCoalescer.py
@@ -34,7 +34,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from Sequencer import *
+
+from m5.objects.Sequencer import *
 
 class RubyGPUCoalescer(RubyPort):
    type = 'RubyGPUCoalescer'
diff --git a/src/mem/ruby/system/RubySystem.py b/src/mem/ruby/system/RubySystem.py
index 5dcfe2f81..02d2890e2 100644
--- a/src/mem/ruby/system/RubySystem.py
+++ b/src/mem/ruby/system/RubySystem.py
@@ -28,8 +28,8 @@
 #          Brad Beckmann
 
 from m5.params import *
-from ClockedObject import ClockedObject
-from SimpleMemory import *
+from m5.objects.ClockedObject import ClockedObject
+from m5.objects.SimpleMemory import *
 
 class RubySystem(ClockedObject):
     type = 'RubySystem'
diff --git a/src/mem/ruby/system/Sequencer.py b/src/mem/ruby/system/Sequencer.py
index 22d545d30..35460438c 100644
--- a/src/mem/ruby/system/Sequencer.py
+++ b/src/mem/ruby/system/Sequencer.py
@@ -29,7 +29,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
+from m5.objects.MemObject import MemObject
 
 class RubyPort(MemObject):
    type = 'RubyPort'
diff --git a/src/mem/ruby/system/VIPERCoalescer.py b/src/mem/ruby/system/VIPERCoalescer.py
index 280a33382..85370f6df 100644
--- a/src/mem/ruby/system/VIPERCoalescer.py
+++ b/src/mem/ruby/system/VIPERCoalescer.py
@@ -34,7 +34,7 @@
 
 from m5.params import *
 from m5.proxy import *
-from GPUCoalescer import *
+from m5.objects.GPUCoalescer import *
 
 class VIPERCoalescer(RubyGPUCoalescer):
     type = 'VIPERCoalescer'
diff --git a/src/mem/ruby/system/WeightedLRUReplacementPolicy.py b/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
index 80f3d6981..77ee60554 100644
--- a/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
+++ b/src/mem/ruby/system/WeightedLRUReplacementPolicy.py
@@ -33,8 +33,8 @@
 
 from m5.params import *
 from m5.proxy import *
-from MemObject import MemObject
-from ReplacementPolicy import ReplacementPolicy
+from m5.objects.MemObject import MemObject
+from m5.objects.ReplacementPolicy import ReplacementPolicy
 
 class WeightedLRUReplacementPolicy(ReplacementPolicy):
     type = "WeightedLRUReplacementPolicy"
diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index e63f6fc60..cbcc7924a 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -226,7 +226,7 @@ class StateMachine(Symbol):
         code('''
 from m5.params import *
 from m5.SimObject import SimObject
-from Controller import RubyController
+from m5.objects.Controller import RubyController
 
 class $py_ident(RubyController):
     type = '$py_ident'
diff --git a/src/sim/System.py b/src/sim/System.py
index f45decb6b..51b1a743f 100644
--- a/src/sim/System.py
+++ b/src/sim/System.py
@@ -45,8 +45,8 @@ from m5.defines import buildEnv
 from m5.params import *
 from m5.proxy import *
 
-from DVFSHandler import *
-from SimpleMemory import *
+from m5.objects.DVFSHandler import *
+from m5.objects.SimpleMemory import *
 
 class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing',
                                 'atomic_noncaching']
diff --git a/src/sim/TickedObject.py b/src/sim/TickedObject.py
index a566aac92..8746e3775 100644
--- a/src/sim/TickedObject.py
+++ b/src/sim/TickedObject.py
@@ -35,7 +35,7 @@
 #
 # Authors: Andrew Bardsley
 
-from ClockedObject import ClockedObject
+from m5.objects.ClockedObject import ClockedObject
 
 class TickedObject(ClockedObject):
     type = 'TickedObject'
diff --git a/src/sim/power/MathExprPowerModel.py b/src/sim/power/MathExprPowerModel.py
index 85132d22c..e462fa120 100644
--- a/src/sim/power/MathExprPowerModel.py
+++ b/src/sim/power/MathExprPowerModel.py
@@ -37,7 +37,7 @@
 
 from m5.SimObject import SimObject
 from m5.params import *
-from PowerModelState import PowerModelState
+from m5.objects.PowerModelState import PowerModelState
 
 # Represents a power model for a simobj
 class MathExprPowerModel(PowerModelState):
diff --git a/src/sim/power/ThermalModel.py b/src/sim/power/ThermalModel.py
index e6a01b2be..ef9548a76 100644
--- a/src/sim/power/ThermalModel.py
+++ b/src/sim/power/ThermalModel.py
@@ -36,7 +36,7 @@
 # Authors: David Guillen Fandos
 
 from m5.SimObject import *
-from ClockedObject import ClockedObject
+from m5.objects.ClockedObject import ClockedObject
 
 from m5.params import *
 from m5.objects import ThermalDomain