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authorAli Saidi <Ali.Saidi@ARM.com>2010-11-08 13:58:22 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2010-11-08 13:58:22 -0600
commitf4f5d03ed211571f07f13ea9d5df0d70f3101aa3 (patch)
treeab6151c1dd36fc0d7b7b62dcbd472c5c2348f2ab
parent0ea794bcf453093f83c21a56333d78ba1b8dae33 (diff)
downloadgem5-f4f5d03ed211571f07f13ea9d5df0d70f3101aa3.tar.xz
ARM: Make all ARM uops delayed commit.
-rw-r--r--src/arch/arm/insts/macromem.hh6
-rw-r--r--src/arch/arm/isa/templates/mem.isa19
-rw-r--r--src/cpu/static_inst.hh2
3 files changed, 21 insertions, 6 deletions
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index 018cb1de5..1a2db8b9a 100644
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -73,12 +73,6 @@ class MicroOp : public PredOp
public:
void
- setDelayedCommit()
- {
- flags[IsDelayedCommit] = true;
- }
-
- void
advancePC(PCState &pcState) const
{
if (flags[IsLastMicroop]) {
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 29ef8d007..ab4f1b01b 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -917,6 +917,7 @@ def template RfeConstructor {{
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _base, _mode, _wb);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -934,6 +935,7 @@ def template SrsConstructor {{
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _regMode, _mode, _wb);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -963,6 +965,7 @@ def template LoadStoreDImmConstructor {{
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add, _imm);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -984,6 +987,7 @@ def template StoreExDImmConstructor {{
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _result, _dest, _dest2,
_base, _add, _imm);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -1001,6 +1005,7 @@ def template LoadStoreImmConstructor {{
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -1021,6 +1026,7 @@ def template StoreExImmConstructor {{
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _result, _dest,
_base, _add, _imm);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -1043,6 +1049,7 @@ def template StoreDRegConstructor {{
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -1064,6 +1071,7 @@ def template StoreRegConstructor {{
uops = new StaticInstPtr[numMicroops];
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
#endif
@@ -1087,14 +1095,17 @@ def template LoadDRegConstructor {{
if ((_dest == _index) || (_dest2 == _index)) {
IntRegIndex wbIndexReg = INTREG_UREG0;
uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[1]->setDelayedCommit();
uops[2] = new %(wb_decl)s;
uops[2]->setLastMicroop();
} else {
IntRegIndex wbIndexReg = index;
uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
}
@@ -1119,20 +1130,25 @@ def template LoadRegConstructor {{
IntRegIndex wbIndexReg = index;
uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
+ uops[1]->setDelayedCommit();
uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
uops[2]->setLastMicroop();
} else if(_dest == _index) {
IntRegIndex wbIndexReg = INTREG_UREG0;
uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[1]->setDelayedCommit();
uops[2] = new %(wb_decl)s;
uops[2]->setLastMicroop();
} else {
IntRegIndex wbIndexReg = index;
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
_shiftAmt, _shiftType, _index);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
@@ -1154,11 +1170,14 @@ def template LoadImmConstructor {{
if (_dest == INTREG_PC) {
uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
_imm);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
+ uops[1]->setDelayedCommit();
uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
uops[2]->setLastMicroop();
} else {
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add, _imm);
+ uops[0]->setDelayedCommit();
uops[1] = new %(wb_decl)s;
uops[1]->setLastMicroop();
}
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index b219fafd6..5951ab122 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -263,6 +263,8 @@ class StaticInstBase : public RefCounted
//@}
void setLastMicroop() { flags[IsLastMicroop] = true; }
+ void setDelayedCommit() { flags[IsDelayedCommit] = true; }
+
/// Operation class. Used to select appropriate function unit in issue.
OpClass opClass() const { return _opClass; }
};