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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-11-14 19:22:29 -0800 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-11-14 19:22:29 -0800 |
| commit | 1df0025e28d8f9699f86fc118db3b93a0f1ec50c (patch) | |
| tree | f0cfe7096ce31b1e2f8aaef61a4d6930c8e8ff5a | |
| parent | 50b9149c7572b4cff351f2c28726226030cefdbd (diff) | |
| download | gem5-1df0025e28d8f9699f86fc118db3b93a0f1ec50c.tar.xz | |
ARM: More accurately describe the effects of using the control operands.
| -rw-r--r-- | src/arch/arm/isa/operands.isa | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index fe085cdac..aadefc79c 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -81,12 +81,12 @@ def operands {{ #Memory Operand 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), - 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40), - 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', 'IsInteger', 41), - 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 42), - 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 43), - 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 44), - 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 45), + 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40), + 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', (None, None, 'IsControl'), 41), + 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', (None, None, 'IsControl'), 42), + 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', (None, None, 'IsControl'), 43), + 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', (None, None, 'IsControl'), 44), + 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', (None, None, 'IsControl'), 45), 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 50), 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 51) |