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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-30 05:38:24 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-01-30 05:38:24 -0500 |
| commit | cfc268ad9e5b83cac551cae118811e5c86382d9e (patch) | |
| tree | a7e24ac6a73e8813a87b7817a3e6b02f44e9c96d | |
| parent | ef9fc010736df313fbc7acaea3a9b0e2fee33955 (diff) | |
| download | gem5-cfc268ad9e5b83cac551cae118811e5c86382d9e.tar.xz | |
MEM: Make the RubyPort physMemPort a PioPort instead of M5Port
This patch makes the physMemPort of the RubyPort a PioPort rather than
an M5Port. This reflects the fact that the M5Port and PioPort have
different roles. The M5Port is really a coherent slave that is
connected to the CPUs and other coherent masters of the system,
e.g. DMA ports. The PioPort, on the other hand, is a master port that
is connected to the memory and other slaves, for example the pio
devices.
This simplifies future changes into master/slave ports and is
consistent with the port roles throughout the system.
| -rw-r--r-- | src/mem/ruby/system/RubyPort.cc | 3 | ||||
| -rw-r--r-- | src/mem/ruby/system/RubyPort.hh | 2 |
2 files changed, 2 insertions, 3 deletions
diff --git a/src/mem/ruby/system/RubyPort.cc b/src/mem/ruby/system/RubyPort.cc index b60ca2a07..af414f17a 100644 --- a/src/mem/ruby/system/RubyPort.cc +++ b/src/mem/ruby/system/RubyPort.cc @@ -88,8 +88,7 @@ RubyPort::getPort(const std::string &if_name, int idx) // RubyPort should only have one port to physical memory assert (physMemPort == NULL); - physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this, - ruby_system, access_phys_mem); + physMemPort = new PioPort(csprintf("%s-physMemPort", name()), this); return physMemPort; } diff --git a/src/mem/ruby/system/RubyPort.hh b/src/mem/ruby/system/RubyPort.hh index 2ffdef3d9..6df713a13 100644 --- a/src/mem/ruby/system/RubyPort.hh +++ b/src/mem/ruby/system/RubyPort.hh @@ -155,7 +155,7 @@ class RubyPort : public MemObject uint16_t m_port_id; uint64_t m_request_cnt; - M5Port* physMemPort; + PioPort* physMemPort; /*! Vector of CPU Port attached to this Ruby port. */ typedef std::vector<M5Port*>::iterator CpuPortIter; |