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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:48 -0600 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-02-23 15:10:48 -0600 |
| commit | d63020717c8a722eb2f5236eacd042cdee78769d (patch) | |
| tree | f53db4e1a39979e80660a7c739f7046d6b8e72c2 | |
| parent | 981e1dd7eea3661cc2a0f99e783459bdc9fe5bd9 (diff) | |
| download | gem5-d63020717c8a722eb2f5236eacd042cdee78769d.tar.xz | |
ARM: Adds dummy support for a L2 latency miscreg.
| -rw-r--r-- | src/arch/arm/isa/formats/misc.isa | 3 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.cc | 2 | ||||
| -rw-r--r-- | src/arch/arm/miscregs.hh | 1 |
3 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa index 6a734a582..3bcb5c97d 100644 --- a/src/arch/arm/isa/formats/misc.isa +++ b/src/arch/arm/isa/formats/misc.isa @@ -143,6 +143,9 @@ let {{ case MISCREG_BPIALL: return new WarnUnimplemented( isRead ? "mrc bpiall" : "mcr bpiall", machInst); + case MISCREG_L2LATENCY: + return new WarnUnimplemented( + isRead ? "mrc l2latency" : "mcr l2latency", machInst); // Write only. case MISCREG_TLBIALLIS: diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 13dec0add..fc04ce87d 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc @@ -381,6 +381,8 @@ decodeCP15Reg(unsigned crn, unsigned opc1, unsigned crm, unsigned opc2) return MISCREG_PMINTENCLR; } } + } else if (opc1 == 1) { + return MISCREG_L2LATENCY; } //Reserved for Branch Predictor, Cache and TCM operations break; diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh index cf9da428a..90b4fd999 100644 --- a/src/arch/arm/miscregs.hh +++ b/src/arch/arm/miscregs.hh @@ -191,6 +191,7 @@ namespace ArmISA MISCREG_MVBAR, MISCREG_ISR, MISCREG_FCEIDR, + MISCREG_L2LATENCY, MISCREG_CP15_END, |