diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-01-20 08:12:02 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-01-20 08:12:02 -0500 |
| commit | de162ad96886cc78bd9c0fdb3417f8d8047f643b (patch) | |
| tree | da6e05cf52b09dbb2953cb9a2d01468253eb4c9c | |
| parent | 6096e2f9c11afbb57b78f985f8b8fe7e059821b0 (diff) | |
| download | gem5-de162ad96886cc78bd9c0fdb3417f8d8047f643b.tar.xz | |
tests: Remove deprecated InOrderCPU tests
This patch removes the three MIPS and SPARC regressions that use the
deprecated InOrderCPU.
This is the first step in completely removing the code from the tree,
avoiding confusion, and focusing all development efforts on the
MinorCPU. Brave new world.
14 files changed, 0 insertions, 3387 deletions
diff --git a/tests/SConscript b/tests/SConscript index 5c33e2956..a4b259681 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -354,7 +354,6 @@ if env['TARGET_ISA'] == 'x86': configs += ['simple-atomic', 'simple-atomic-mp', 'simple-timing', 'simple-timing-mp', - 'inorder-timing', 'minor-timing', 'minor-timing-mp', 'o3-timing', 'o3-timing-mp', 'rubytest', 'memtest', 'memtest-filter', diff --git a/tests/configs/inorder-timing.py b/tests/configs/inorder-timing.py deleted file mode 100644 index a5fbd7763..000000000 --- a/tests/configs/inorder-timing.py +++ /dev/null @@ -1,45 +0,0 @@ -# Copyright (c) 2013 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. -# -# Copyright (c) 2006-2007 The Regents of The University of Michigan -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are -# met: redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer; -# redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution; -# neither the name of the copyright holders nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -# -# Authors: Andreas Hansson - -from m5.objects import * -from base_config import * - -root = BaseSESystemUniprocessor(mem_mode='timing', mem_class=DDR3_1600_x64, - cpu_class=InOrderCPU).create_root() diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini deleted file mode 100644 index 93ee36e3b..000000000 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini +++ /dev/null @@ -1,384 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=InOrderCPU -children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -activity=0 -branchPred=system.cpu.branchPred -cachePorts=2 -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -div16Latency=1 -div16RepeatRate=1 -div24Latency=1 -div24RepeatRate=1 -div32Latency=1 -div32RepeatRate=1 -div8Latency=1 -div8RepeatRate=1 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBuffSize=4 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -memBlockSize=64 -multLatency=1 -multRepeatRate=1 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -stageTracing=false -stageWidth=4 -switched_out=false -system=system -threadModel=SMT -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -predType=tournament - -[system.cpu.dcache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=MipsTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=MipsInterrupts -eventq_index=0 - -[system.cpu.isa] -type=MipsISA -eventq_index=0 -num_threads=1 -num_vpes=1 -system=system - -[system.cpu.itb] -type=MipsTLB -eventq_index=0 -size=64 - -[system.cpu.l2cache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=20 -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -clk_domain=system.cpu_clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/mips/linux/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaChCo -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -page_policy=open_adaptive -range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=0 -tXPDLL=0 -tXS=0 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr deleted file mode 100755 index 1a4f96712..000000000 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simerr +++ /dev/null @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout deleted file mode 100755 index 5a8e6736f..000000000 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout +++ /dev/null @@ -1,12 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 16:53:01 -gem5 started Jan 22 2014 17:27:52 -gem5 executing on u200540-lin -command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -info: Increasing stack size by one page. -Hello World! -Exiting @ tick 24975000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt deleted file mode 100644 index a18a67ef2..000000000 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ /dev/null @@ -1,727 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24407000 # Number of ticks simulated -final_tick 24407000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 92117 # Simulator instruction rate (inst/s) -host_op_rate 92097 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 399597243 # Simulator tick rate (ticks/s) -host_mem_usage 289532 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 5624 # Number of instructions simulated -sim_ops 5624 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory -system.physmem.bytes_read::total 28800 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory -system.physmem.num_reads::total 450 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 820748146 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 359241201 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1179989347 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 820748146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 820748146 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 820748146 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 359241201 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1179989347 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 450 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 450 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 28800 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 28800 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 27 # Per bank write bursts -system.physmem.perBankRdBursts::1 0 # Per bank write bursts -system.physmem.perBankRdBursts::2 0 # Per bank write bursts -system.physmem.perBankRdBursts::3 0 # Per bank write bursts -system.physmem.perBankRdBursts::4 8 # Per bank write bursts -system.physmem.perBankRdBursts::5 3 # Per bank write bursts -system.physmem.perBankRdBursts::6 12 # Per bank write bursts -system.physmem.perBankRdBursts::7 50 # Per bank write bursts -system.physmem.perBankRdBursts::8 56 # Per bank write bursts -system.physmem.perBankRdBursts::9 75 # Per bank write bursts -system.physmem.perBankRdBursts::10 36 # Per bank write bursts -system.physmem.perBankRdBursts::11 19 # Per bank write bursts -system.physmem.perBankRdBursts::12 52 # Per bank write bursts -system.physmem.perBankRdBursts::13 28 # Per bank write bursts -system.physmem.perBankRdBursts::14 77 # Per bank write bursts -system.physmem.perBankRdBursts::15 7 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 24326000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 450 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 299 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 121 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 276.504854 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 191.986288 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 256.190297 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 25 24.27% 24.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 37 35.92% 60.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14 13.59% 73.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 8 7.77% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8 7.77% 89.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 1.94% 91.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 2.91% 94.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 0.97% 95.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 4.85% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation -system.physmem.totQLat 4895500 # Total ticks spent queuing -system.physmem.totMemAccLat 13333000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2250000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10878.89 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29628.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1179.99 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1179.99 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 9.22 # Data bus utilization in percentage -system.physmem.busUtilRead 9.22 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.52 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 344 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 76.44 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 54057.78 # Average gap between requests -system.physmem.pageHitRate 76.44 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 181440 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 99000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 772200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 14753880 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1232250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 18564450 # Total energy per rank (pJ) -system.physmem_0.averagePower 785.838404 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1971000 # Time in different power states -system.physmem_0.memoryStateTime::REF 780000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 20886000 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 582120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 317625 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 2652000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 16041510 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 99750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 21218685 # Total energy per rank (pJ) -system.physmem_1.averagePower 898.383064 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 96500 # Time in different power states -system.physmem_1.memoryStateTime::REF 780000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 22756000 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1124 # Number of BP lookups -system.cpu.branchPred.condPredicted 833 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 586 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 850 # Number of BTB lookups -system.cpu.branchPred.BTBHits 329 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 38.705882 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 84 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.dtb.read_hits 0 # DTB read hits -system.cpu.dtb.read_misses 0 # DTB read misses -system.cpu.dtb.read_accesses 0 # DTB read accesses -system.cpu.dtb.write_hits 0 # DTB write hits -system.cpu.dtb.write_misses 0 # DTB write misses -system.cpu.dtb.write_accesses 0 # DTB write accesses -system.cpu.dtb.hits 0 # DTB hits -system.cpu.dtb.misses 0 # DTB misses -system.cpu.dtb.accesses 0 # DTB accesses -system.cpu.itb.read_hits 0 # DTB read hits -system.cpu.itb.read_misses 0 # DTB read misses -system.cpu.itb.read_accesses 0 # DTB read accesses -system.cpu.itb.write_hits 0 # DTB write hits -system.cpu.itb.write_misses 0 # DTB write misses -system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.hits 0 # DTB hits -system.cpu.itb.misses 0 # DTB misses -system.cpu.itb.accesses 0 # DTB accesses -system.cpu.workload.num_syscalls 7 # Number of system calls -system.cpu.numCycles 48815 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 421 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 703 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 4929 # Number of Reads from Int. Register File -system.cpu.regfile_manager.intRegFileWrites 3280 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8209 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File -system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1292 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 2173 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 263 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 315 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 578 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 305 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 65.458664 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3019 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 2 # Number of Multipy Operations Executed -system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9295 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 454 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 43567 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5248 # Number of cycles cpu stages are processed. -system.cpu.activity 10.750794 # Percentage of cycles cpu is active -system.cpu.comLoads 1132 # Number of Load instructions committed -system.cpu.comStores 901 # Number of Store instructions committed -system.cpu.comBranches 883 # Number of Branches instructions committed -system.cpu.comNops 637 # Number of Nop instructions committed -system.cpu.comNonSpec 9 # Number of Non-Speculative instructions committed -system.cpu.comInts 2062 # Number of Integer instructions committed -system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 5624 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 5624 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 5624 # Number of Instructions committed (Total) -system.cpu.cpi 8.679765 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 8.679765 # CPI: Total CPI of All Threads -system.cpu.ipc 0.115210 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.115210 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 45271 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3544 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 7.260064 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 46079 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2736 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 5.604835 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46125 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2690 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 5.510601 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 47621 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1194 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.445969 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46021 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2794 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 5.723651 # Percentage of cycles stage was utilized (processing insts). -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 89.114959 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1596 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.649635 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 89.114959 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021757 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021757 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 107 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1035 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1035 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 561 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 561 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1596 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1596 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1596 # number of overall hits -system.cpu.dcache.overall_hits::total 1596 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 340 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 340 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 437 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 437 # number of overall misses -system.cpu.dcache.overall_misses::total 437 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7368000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7368000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 20579000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 20579000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 27947000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 27947000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 27947000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 27947000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085689 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085689 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.377358 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.377358 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.214953 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.214953 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.214953 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.214953 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75958.762887 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75958.762887 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 60526.470588 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 60526.470588 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 63951.945080 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 63951.945080 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 63951.945080 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 63951.945080 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 265 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 13 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 20.384615 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 10 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 290 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 290 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 300 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 300 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 300 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6703250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3771500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3771500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10474750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10474750 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10474750 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10474750 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 77048.850575 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 77048.850575 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75430 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75430 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76458.029197 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76458.029197 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76458.029197 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76458.029197 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 13 # number of replacements -system.cpu.icache.tags.tagsinuse 147.861470 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 418 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 315 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 1.326984 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 147.861470 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.072198 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.072198 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 302 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.147461 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 1839 # Number of tag accesses -system.cpu.icache.tags.data_accesses 1839 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 418 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 418 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 418 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 418 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 418 # number of overall hits -system.cpu.icache.overall_hits::total 418 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 344 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 344 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses -system.cpu.icache.overall_misses::total 344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25136000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25136000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25136000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25136000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25136000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25136000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 762 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 762 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 762 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 762 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 762 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 762 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.451444 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.451444 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.451444 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.451444 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.451444 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.451444 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 73069.767442 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 73069.767442 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 73069.767442 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 73069.767442 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 73069.767442 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 73069.767442 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 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-system.cpu.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 315 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 315 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 315 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22960000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 22960000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22960000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 22960000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22960000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 22960000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.413386 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.413386 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.413386 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.413386 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72888.888889 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72888.888889 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72888.888889 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72888.888889 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72888.888889 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72888.888889 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 204.748410 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 400 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005000 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 149.325774 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 55.422636 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004557 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001691 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006248 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 400 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 161 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012207 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 4066 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 4066 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 450 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses -system.cpu.l2cache.overall_misses::total 450 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22619000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6609750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29228750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3718500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3718500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22619000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10328250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32947250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22619000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10328250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32947250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 315 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 315 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 315 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993651 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993651 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995575 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993651 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995575 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72265.175719 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75974.137931 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 73071.875000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74370 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74370 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72265.175719 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75388.686131 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 73216.111111 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72265.175719 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75388.686131 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 73216.111111 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 450 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18689500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5530750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 24220250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3088000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3088000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18689500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8618750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 27308250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18689500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8618750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 27308250 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993651 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993651 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995575 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993651 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995575 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59710.862620 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63571.839080 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60550.625000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61760 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61760 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59710.862620 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62910.583942 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60685 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59710.862620 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62910.583942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60685 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 402 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 402 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 630 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 904 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20160 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 28928 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 532000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 224750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) -system.membus.trans_dist::ReadReq 400 # Transaction distribution -system.membus.trans_dist::ReadResp 400 # Transaction distribution -system.membus.trans_dist::ReadExReq 50 # Transaction distribution -system.membus.trans_dist::ReadExResp 50 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 900 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 900 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28800 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 28800 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 450 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 450 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 450 # Request fanout histogram -system.membus.reqLayer0.occupancy 545500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.2 # Layer utilization (%) -system.membus.respLayer1.occupancy 4210250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 17.3 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini deleted file mode 100644 index a3c44273d..000000000 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini +++ /dev/null @@ -1,381 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=InOrderCPU -children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -activity=0 -branchPred=system.cpu.branchPred -cachePorts=2 -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -div16Latency=1 -div16RepeatRate=1 -div24Latency=1 -div24RepeatRate=1 -div32Latency=1 -div32RepeatRate=1 -div8Latency=1 -div8RepeatRate=1 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBuffSize=4 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -memBlockSize=64 -multLatency=1 -multRepeatRate=1 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -stageTracing=false -stageWidth=4 -switched_out=false -system=system -threadModel=SMT -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -predType=tournament - -[system.cpu.dcache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=SparcInterrupts -eventq_index=0 - -[system.cpu.isa] -type=SparcISA -eventq_index=0 - -[system.cpu.itb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.l2cache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=20 -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -clk_domain=system.cpu_clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=hello -cwd= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/sparc/linux/hello -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaChCo -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -page_policy=open_adaptive -range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=0 -tXPDLL=0 -tXS=0 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr deleted file mode 100755 index 1a4f96712..000000000 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simerr +++ /dev/null @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout deleted file mode 100755 index bce99f509..000000000 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout +++ /dev/null @@ -1,10 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 17:04:27 -gem5 started Jan 22 2014 17:29:22 -gem5 executing on u200540-lin -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Hello World!Exiting @ tick 20892500 because target called exit() diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt deleted file mode 100644 index 33e0e9c43..000000000 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ /dev/null @@ -1,710 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000021 # Number of seconds simulated -sim_ticks 20927500 # Number of ticks simulated -final_tick 20927500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 82286 # Simulator instruction rate (inst/s) -host_op_rate 82268 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 323129777 # Simulator tick rate (ticks/s) -host_mem_usage 289972 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host -sim_insts 5327 # Number of instructions simulated -sim_ops 5327 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18496 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8576 # Number of bytes read from this memory -system.physmem.bytes_read::total 27072 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18496 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18496 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory -system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 883813164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 409795723 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1293608888 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 883813164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 883813164 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 883813164 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 409795723 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1293608888 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 423 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 423 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27072 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27072 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 24 # Per bank write bursts -system.physmem.perBankRdBursts::1 7 # Per bank write bursts -system.physmem.perBankRdBursts::2 1 # Per bank write bursts -system.physmem.perBankRdBursts::3 8 # Per bank write bursts -system.physmem.perBankRdBursts::4 0 # Per bank write bursts -system.physmem.perBankRdBursts::5 78 # Per bank write bursts -system.physmem.perBankRdBursts::6 80 # Per bank write bursts -system.physmem.perBankRdBursts::7 62 # Per bank write bursts -system.physmem.perBankRdBursts::8 35 # Per bank write bursts -system.physmem.perBankRdBursts::9 18 # Per bank write bursts -system.physmem.perBankRdBursts::10 10 # Per bank write bursts -system.physmem.perBankRdBursts::11 52 # Per bank write bursts -system.physmem.perBankRdBursts::12 12 # Per bank write bursts -system.physmem.perBankRdBursts::13 21 # Per bank write bursts -system.physmem.perBankRdBursts::14 7 # Per bank write bursts -system.physmem.perBankRdBursts::15 8 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 20858000 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 423 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 250 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 74 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 323.459459 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 226.188766 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 265.234411 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 17 22.97% 22.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 21.62% 44.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 11 14.86% 59.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 13 17.57% 77.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 8 10.81% 87.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 4 5.41% 93.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 5 6.76% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 74 # Bytes accessed per row activation -system.physmem.totQLat 3885750 # Total ticks spent queuing -system.physmem.totMemAccLat 11817000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2115000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9186.17 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27936.17 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1293.61 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1293.61 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 10.11 # Data bus utilization in percentage -system.physmem.busUtilRead 10.11 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.66 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 339 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 80.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 49309.69 # Average gap between requests -system.physmem.pageHitRate 80.14 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1497600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10702035 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 111750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 13784220 # Total energy per rank (pJ) -system.physmem_0.averagePower 870.628138 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 116500 # Time in different power states -system.physmem_0.memoryStateTime::REF 520000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15209750 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 196560 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 107250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1107600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10576350 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 222000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 13226880 # Total energy per rank (pJ) -system.physmem_1.averagePower 835.425865 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 328000 # Time in different power states -system.physmem_1.memoryStateTime::REF 520000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14998250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1636 # Number of BP lookups -system.cpu.branchPred.condPredicted 1090 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 897 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1343 # Number of BTB lookups -system.cpu.branchPred.BTBHits 584 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 43.484736 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 67 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 41856 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 651 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 985 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5611 # Number of Reads from Int. Register File -system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9599 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File -system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1718 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 1472 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 376 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 458 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 834 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 281 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 74.798206 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 3957 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9651 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 424 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 35611 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6245 # Number of cycles cpu stages are processed. -system.cpu.activity 14.920203 # Percentage of cycles cpu is active -system.cpu.comLoads 715 # Number of Load instructions committed -system.cpu.comStores 673 # Number of Store instructions committed -system.cpu.comBranches 1115 # Number of Branches instructions committed -system.cpu.comNops 173 # Number of Nop instructions committed -system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed -system.cpu.comInts 2526 # Number of Integer instructions committed -system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 5327 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 7.857331 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 7.857331 # CPI: Total CPI of All Threads -system.cpu.ipc 0.127270 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.127270 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 37216 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4640 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 11.085627 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 38661 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3195 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.633314 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 38823 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3033 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.246273 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 40881 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.329415 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38699 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3157 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.542527 # Percentage of cycles stage was utilized (processing insts). -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 85.369863 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 914 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 6.770370 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 85.369863 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.020842 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.020842 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 97 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.032959 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 2911 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 2911 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits -system.cpu.dcache.overall_hits::total 914 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses -system.cpu.dcache.overall_misses::total 474 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4588750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4588750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 28972250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 28972250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 33561000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 33561000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 33561000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 33561000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 1388 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 1388 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 1388 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 75225.409836 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 75225.409836 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70150.726392 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 70150.726392 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 70803.797468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 70803.797468 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 70803.797468 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 818 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 31 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.387097 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 81 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4091500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4091500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6091750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6091750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10183250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10183250 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10183250 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10183250 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.120357 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 75768.518519 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 75768.518519 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75206.790123 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75206.790123 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75431.481481 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 75431.481481 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 142.708262 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 892 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 3.065292 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 142.708262 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.069682 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.069682 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 291 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.142090 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 2807 # Number of tag accesses -system.cpu.icache.tags.data_accesses 2807 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 892 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 892 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 892 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 892 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 892 # number of overall hits -system.cpu.icache.overall_hits::total 892 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses -system.cpu.icache.overall_misses::total 366 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25412000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25412000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25412000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25412000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25412000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25412000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1258 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1258 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1258 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1258 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1258 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1258 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.290938 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.290938 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.290938 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.290938 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.290938 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.290938 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69431.693989 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 69431.693989 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 69431.693989 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 69431.693989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 69431.693989 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 69431.693989 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20639500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20639500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20639500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20639500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20639500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20639500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.231320 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.231320 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.231320 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70926.116838 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70926.116838 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70926.116838 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 70926.116838 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70926.116838 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 70926.116838 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 169.161112 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.008772 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.138007 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 27.023105 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004338 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000825 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005162 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 342 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 171 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010437 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3831 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3831 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits -system.cpu.l2cache.overall_hits::total 3 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 289 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 342 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 81 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 81 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 289 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 134 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 423 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses -system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20321000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4025000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24346000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6008250 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6008250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20321000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 10033250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 30354250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20321000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 10033250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 30354250 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 81 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 291 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 426 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 291 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 426 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993127 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981481 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.991304 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993127 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.992593 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.992958 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70314.878893 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75943.396226 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 71187.134503 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74175.925926 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74175.925926 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70314.878893 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 74875 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 71759.456265 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70314.878893 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 74875 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 71759.456265 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 289 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 81 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 289 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 423 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16706500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3370000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20076500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5013250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5013250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16706500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8383250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25089750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16706500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8383250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25089750 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57807.958478 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63584.905660 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58703.216374 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61891.975309 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61891.975309 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57807.958478 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62561.567164 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59313.829787 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57807.958478 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62561.567164 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59313.829787 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 345 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 81 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 81 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 582 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 852 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18624 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 27264 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 426 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 426 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 426 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 213000 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 486500 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 216750 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) -system.membus.trans_dist::ReadReq 342 # Transaction distribution -system.membus.trans_dist::ReadResp 342 # Transaction distribution -system.membus.trans_dist::ReadExReq 81 # Transaction distribution -system.membus.trans_dist::ReadExResp 81 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 846 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 846 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 27072 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 423 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 423 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 423 # Request fanout histogram -system.membus.reqLayer0.occupancy 501500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) -system.membus.respLayer1.occupancy 3931250 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 18.8 # Layer utilization (%) - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini deleted file mode 100644 index c6b990bda..000000000 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini +++ /dev/null @@ -1,381 +0,0 @@ -[root] -type=Root -children=system -eventq_index=0 -full_system=false -sim_quantum=0 -time_sync_enable=false -time_sync_period=100000000000 -time_sync_spin_threshold=100000000 - -[system] -type=System -children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain -boot_osflags=a -cache_line_size=64 -clk_domain=system.clk_domain -eventq_index=0 -init_param=0 -kernel= -kernel_addr_check=true -load_addr_mask=1099511627775 -load_offset=0 -mem_mode=timing -mem_ranges= -memories=system.physmem -num_work_ids=16 -readfile= -symbolfile= -work_begin_ckpt_count=0 -work_begin_cpu_id_exit=-1 -work_begin_exit_count=0 -work_cpus_ckpt_count=0 -work_end_ckpt_count=0 -work_end_exit_count=0 -work_item_id=-1 -system_port=system.membus.slave[0] - -[system.clk_domain] -type=SrcClockDomain -clock=1000 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.cpu] -type=InOrderCPU -children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload -activity=0 -branchPred=system.cpu.branchPred -cachePorts=2 -checker=Null -clk_domain=system.cpu_clk_domain -cpu_id=0 -div16Latency=1 -div16RepeatRate=1 -div24Latency=1 -div24RepeatRate=1 -div32Latency=1 -div32RepeatRate=1 -div8Latency=1 -div8RepeatRate=1 -do_checkpoint_insts=true -do_quiesce=true -do_statistics_insts=true -dtb=system.cpu.dtb -eventq_index=0 -fetchBuffSize=4 -function_trace=false -function_trace_start=0 -interrupts=system.cpu.interrupts -isa=system.cpu.isa -itb=system.cpu.itb -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -memBlockSize=64 -multLatency=1 -multRepeatRate=1 -numThreads=1 -profile=0 -progress_interval=0 -simpoint_start_insts= -socket_id=0 -stageTracing=false -stageWidth=4 -switched_out=false -system=system -threadModel=SMT -tracer=system.cpu.tracer -workload=system.cpu.workload -dcache_port=system.cpu.dcache.cpu_side -icache_port=system.cpu.icache.cpu_side - -[system.cpu.branchPred] -type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 -RASSize=16 -choiceCtrBits=2 -choicePredictorSize=8192 -eventq_index=0 -globalCtrBits=2 -globalPredictorSize=8192 -instShiftAmt=2 -localCtrBits=2 -localHistoryTableSize=2048 -localPredictorSize=2048 -numThreads=1 -predType=tournament - -[system.cpu.dcache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=262144 -system=system -tags=system.cpu.dcache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.dcache_port -mem_side=system.cpu.toL2Bus.slave[1] - -[system.cpu.dcache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=262144 - -[system.cpu.dtb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.icache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=2 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=2 -is_top_level=true -max_miss_count=0 -mshrs=4 -prefetch_on_access=false -prefetcher=Null -response_latency=2 -sequential_access=false -size=131072 -system=system -tags=system.cpu.icache.tags -tgts_per_mshr=20 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.icache_port -mem_side=system.cpu.toL2Bus.slave[0] - -[system.cpu.icache.tags] -type=LRU -assoc=2 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=2 -sequential_access=false -size=131072 - -[system.cpu.interrupts] -type=SparcInterrupts -eventq_index=0 - -[system.cpu.isa] -type=SparcISA -eventq_index=0 - -[system.cpu.itb] -type=SparcTLB -eventq_index=0 -size=64 - -[system.cpu.l2cache] -type=BaseCache -children=tags -addr_ranges=0:18446744073709551615 -assoc=8 -clk_domain=system.cpu_clk_domain -eventq_index=0 -forward_snoops=true -hit_latency=20 -is_top_level=false -max_miss_count=0 -mshrs=20 -prefetch_on_access=false -prefetcher=Null -response_latency=20 -sequential_access=false -size=2097152 -system=system -tags=system.cpu.l2cache.tags -tgts_per_mshr=12 -two_queue=false -write_buffers=8 -cpu_side=system.cpu.toL2Bus.master[0] -mem_side=system.membus.slave[1] - -[system.cpu.l2cache.tags] -type=LRU -assoc=8 -block_size=64 -clk_domain=system.cpu_clk_domain -eventq_index=0 -hit_latency=20 -sequential_access=false -size=2097152 - -[system.cpu.toL2Bus] -type=CoherentXBar -clk_domain=system.cpu_clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=32 -master=system.cpu.l2cache.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side - -[system.cpu.tracer] -type=ExeTracer -eventq_index=0 - -[system.cpu.workload] -type=LiveProcess -cmd=insttest -cwd= -egid=100 -env= -errout=cerr -euid=100 -eventq_index=0 -executable=/scratch/nilay/GEM5/gem5/tests/test-progs/insttest/bin/sparc/linux/insttest -gid=100 -input=cin -max_stack_size=67108864 -output=cout -pid=100 -ppid=99 -simpoint=0 -system=system -uid=100 -useArchPT=false - -[system.cpu_clk_domain] -type=SrcClockDomain -clock=500 -domain_id=-1 -eventq_index=0 -init_perf_level=0 -voltage_domain=system.voltage_domain - -[system.dvfs_handler] -type=DVFSHandler -domains= -enable=false -eventq_index=0 -sys_clk_domain=system.clk_domain -transition_latency=100000000 - -[system.membus] -type=CoherentXBar -clk_domain=system.clk_domain -eventq_index=0 -header_cycles=1 -snoop_filter=Null -system=system -use_default_range=false -width=8 -master=system.physmem.port -slave=system.system_port system.cpu.l2cache.mem_side - -[system.physmem] -type=DRAMCtrl -IDD0=0.075000 -IDD02=0.000000 -IDD2N=0.050000 -IDD2N2=0.000000 -IDD2P0=0.000000 -IDD2P02=0.000000 -IDD2P1=0.000000 -IDD2P12=0.000000 -IDD3N=0.057000 -IDD3N2=0.000000 -IDD3P0=0.000000 -IDD3P02=0.000000 -IDD3P1=0.000000 -IDD3P12=0.000000 -IDD4R=0.187000 -IDD4R2=0.000000 -IDD4W=0.165000 -IDD4W2=0.000000 -IDD5=0.220000 -IDD52=0.000000 -IDD6=0.000000 -IDD62=0.000000 -VDD=1.500000 -VDD2=0.000000 -activation_limit=4 -addr_mapping=RoRaBaChCo -bank_groups_per_rank=0 -banks_per_rank=8 -burst_length=8 -channels=1 -clk_domain=system.clk_domain -conf_table_reported=true -device_bus_width=8 -device_rowbuffer_size=1024 -devices_per_rank=8 -dll=true -eventq_index=0 -in_addr_map=true -max_accesses_per_row=16 -mem_sched_policy=frfcfs -min_writes_per_switch=16 -null=false -page_policy=open_adaptive -range=0:134217727 -ranks_per_channel=2 -read_buffer_size=32 -static_backend_latency=10000 -static_frontend_latency=10000 -tBURST=5000 -tCCD_L=0 -tCK=1250 -tCL=13750 -tCS=2500 -tRAS=35000 -tRCD=13750 -tREFI=7800000 -tRFC=260000 -tRP=13750 -tRRD=6000 -tRRD_L=0 -tRTP=7500 -tRTW=2500 -tWR=15000 -tWTR=7500 -tXAW=30000 -tXP=0 -tXPDLL=0 -tXS=0 -tXSDLL=0 -write_buffer_size=64 -write_high_thresh_perc=85 -write_low_thresh_perc=50 -port=system.membus.master[0] - -[system.voltage_domain] -type=VoltageDomain -eventq_index=0 -voltage=1.000000 - diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr deleted file mode 100755 index 1a4f96712..000000000 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simerr +++ /dev/null @@ -1 +0,0 @@ -warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout deleted file mode 100755 index 8b0aca80b..000000000 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout +++ /dev/null @@ -1,21 +0,0 @@ -gem5 Simulator System. http://gem5.org -gem5 is copyrighted software; use the --copyright option for details. - -gem5 compiled Jan 22 2014 17:04:27 -gem5 started Jan 22 2014 17:29:33 -gem5 executing on u200540-lin -command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -Global frequency set at 1000000000000 ticks per second -info: Entering event queue @ 0. Starting simulation... -Begining test of difficult SPARC instructions... -LDSTUB: Passed -SWAP: Passed -CAS FAIL: Passed -CAS WORK: Passed -CASX FAIL: Passed -CASX WORK: Passed -LDTX: Passed -LDTW: Passed -STTW: Passed -Done -Exiting @ tick 27705000 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt deleted file mode 100644 index 766e4c6e5..000000000 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ /dev/null @@ -1,712 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000028 # Number of seconds simulated -sim_ticks 27671000 # Number of ticks simulated -final_tick 27671000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95145 # Simulator instruction rate (inst/s) -host_op_rate 95137 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 173614335 # Simulator tick rate (ticks/s) -host_mem_usage 289900 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host -sim_insts 15162 # Number of instructions simulated -sim_ops 15162 # Number of ops (including micro ops) simulated -system.voltage_domain.voltage 1 # Voltage in Volts -system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 19008 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory -system.physmem.bytes_read::total 27840 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 19008 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 19008 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 297 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory -system.physmem.num_reads::total 435 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 686928553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 319178924 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1006107477 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 686928553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 686928553 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 686928553 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 319178924 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1006107477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 436 # Number of read requests accepted -system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 436 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 27904 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 27904 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 97 # Per bank write bursts -system.physmem.perBankRdBursts::1 28 # Per bank write bursts -system.physmem.perBankRdBursts::2 38 # Per bank write bursts -system.physmem.perBankRdBursts::3 20 # Per bank write bursts -system.physmem.perBankRdBursts::4 16 # Per bank write bursts -system.physmem.perBankRdBursts::5 0 # Per bank write bursts -system.physmem.perBankRdBursts::6 29 # Per bank write bursts -system.physmem.perBankRdBursts::7 32 # Per bank write bursts -system.physmem.perBankRdBursts::8 4 # Per bank write bursts -system.physmem.perBankRdBursts::9 1 # Per bank write bursts -system.physmem.perBankRdBursts::10 1 # Per bank write bursts -system.physmem.perBankRdBursts::11 0 # Per bank write bursts -system.physmem.perBankRdBursts::12 48 # Per bank write bursts -system.physmem.perBankRdBursts::13 31 # Per bank write bursts -system.physmem.perBankRdBursts::14 58 # Per bank write bursts -system.physmem.perBankRdBursts::15 33 # Per bank write bursts -system.physmem.perBankWrBursts::0 0 # Per bank write bursts -system.physmem.perBankWrBursts::1 0 # Per bank write bursts -system.physmem.perBankWrBursts::2 0 # Per bank write bursts -system.physmem.perBankWrBursts::3 0 # Per bank write bursts -system.physmem.perBankWrBursts::4 0 # Per bank write bursts -system.physmem.perBankWrBursts::5 0 # Per bank write bursts -system.physmem.perBankWrBursts::6 0 # Per bank write bursts -system.physmem.perBankWrBursts::7 0 # Per bank write bursts -system.physmem.perBankWrBursts::8 0 # Per bank write bursts -system.physmem.perBankWrBursts::9 0 # Per bank write bursts -system.physmem.perBankWrBursts::10 0 # Per bank write bursts -system.physmem.perBankWrBursts::11 0 # Per bank write bursts -system.physmem.perBankWrBursts::12 0 # Per bank write bursts -system.physmem.perBankWrBursts::13 0 # Per bank write bursts -system.physmem.perBankWrBursts::14 0 # Per bank write bursts -system.physmem.perBankWrBursts::15 0 # Per bank write bursts -system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 27637500 # Total gap between requests -system.physmem.readPktSize::0 0 # Read request sizes (log2) -system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 0 # Read request sizes (log2) -system.physmem.readPktSize::4 0 # Read request sizes (log2) -system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 436 # Read request sizes (log2) -system.physmem.writePktSize::0 0 # Write request sizes (log2) -system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 0 # Write request sizes (log2) -system.physmem.writePktSize::3 0 # Write request sizes (log2) -system.physmem.writePktSize::4 0 # Write request sizes (log2) -system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 390.787879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 254.304435 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.314954 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 12 18.18% 18.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 28.79% 46.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 10 15.15% 62.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 6.06% 68.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 4 6.06% 74.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 3 4.55% 78.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 3 4.55% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 11 16.67% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66 # Bytes accessed per row activation -system.physmem.totQLat 2648750 # Total ticks spent queuing -system.physmem.totMemAccLat 10823750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 2180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6075.11 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24825.11 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1008.42 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1008.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 7.88 # Data bus utilization in percentage -system.physmem.busUtilRead 7.88 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.50 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 362 # Number of row buffer hits during reads -system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.03 # Row buffer hit rate for reads -system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 63388.76 # Average gap between requests -system.physmem.pageHitRate 83.03 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1786200 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 15269445 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 797250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 19822605 # Total energy per rank (pJ) -system.physmem_0.averagePower 838.076525 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 1258750 # Time in different power states -system.physmem_0.memoryStateTime::REF 780000 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 21626500 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 204120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 111375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 1232400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 14625630 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1341750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 19040955 # Total energy per rank (pJ) -system.physmem_1.averagePower 806.179624 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 4247250 # Time in different power states -system.physmem_1.memoryStateTime::REF 780000 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 20686250 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 5146 # Number of BP lookups -system.cpu.branchPred.condPredicted 3529 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2366 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 4100 # Number of BTB lookups -system.cpu.branchPred.BTBHits 2719 # Number of BTB hits -system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 66.317073 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 174 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 5 # Number of incorrect RAS predictions. -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 55343 # number of cpu cycles simulated -system.cpu.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.predictedTaken 2893 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 2253 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 14397 # Number of Reads from Int. Register File -system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 25496 # Total Accesses (Read+Write) to the Int. Register File -system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File -system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File -system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 5052 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 3844 # Number of Address Generations -system.cpu.execution_unit.predictedTakenIncorrect 1541 # Number of Branches Incorrectly Predicted As Taken. -system.cpu.execution_unit.predictedNotTakenIncorrect 762 # Number of Branches Incorrectly Predicted As Not Taken). -system.cpu.execution_unit.mispredicted 2303 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.predicted 1055 # Number of Branches Incorrectly Predicted -system.cpu.execution_unit.mispredictPct 68.582490 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 11045 # Number of Instructions Executed. -system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed -system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed -system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 21863 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) -system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 440 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 37775 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17568 # Number of cycles cpu stages are processed. -system.cpu.activity 31.743852 # Percentage of cycles cpu is active -system.cpu.comLoads 2225 # Number of Load instructions committed -system.cpu.comStores 1448 # Number of Store instructions committed -system.cpu.comBranches 3358 # Number of Branches instructions committed -system.cpu.comNops 726 # Number of Nop instructions committed -system.cpu.comNonSpec 222 # Number of Non-Speculative instructions committed -system.cpu.comInts 7166 # Number of Integer instructions committed -system.cpu.comFloats 0 # Number of Floating Point instructions committed -system.cpu.committedInsts 15162 # Number of Instructions committed (Per-Thread) -system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) -system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) -system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.650112 # CPI: Cycles Per Instruction (Per-Thread) -system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.650112 # CPI: Total CPI of All Threads -system.cpu.ipc 0.273964 # IPC: Instructions Per Cycle (Per-Thread) -system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.273964 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 41917 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 13426 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 24.259617 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 45990 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9353 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 16.900060 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 46540 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8803 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 15.906257 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 52465 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.200296 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 46034 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9309 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 16.820555 # Percentage of cycles stage was utilized (processing insts). -system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 98.529834 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 3193 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 23.137681 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 98.529834 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.024055 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.024055 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 16 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 7484 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 7484 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3187 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3187 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3187 # number of overall hits -system.cpu.dcache.overall_hits::total 3187 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 422 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 422 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses -system.cpu.dcache.overall_misses::total 480 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 4268250 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 4268250 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 25898250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 25898250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30166500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30166500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30166500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30166500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 3667 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 3667 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 3667 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026067 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.026067 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292649 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.292649 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73590.517241 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 73590.517241 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61370.260664 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 61370.260664 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 62846.875000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 62846.875000 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 62846.875000 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 1102 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 33 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 33.393939 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 337 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 337 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 342 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 342 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 342 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3749750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3749750 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6087750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6087750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9837500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9837500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9837500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9837500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 70750 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 70750 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 71620.588235 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 71620.588235 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71286.231884 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 71286.231884 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 168.877638 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3004 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 10.046823 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 168.877638 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.082460 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.082460 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 299 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 79 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 220 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.145996 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7069 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7069 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3004 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3004 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3004 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3004 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3004 # number of overall hits -system.cpu.icache.overall_hits::total 3004 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 381 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 381 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 381 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 381 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 381 # number of overall misses -system.cpu.icache.overall_misses::total 381 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 25899500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 25899500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 25899500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 25899500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 25899500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 25899500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3385 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3385 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3385 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3385 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3385 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3385 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.112555 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.112555 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.112555 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.112555 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.112555 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.112555 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 67977.690289 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 67977.690289 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 67977.690289 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 67977.690289 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 67977.690289 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 67977.690289 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.icache.fast_writes 0 # number of fast writes performed -system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 80 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 80 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 80 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 80 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 80 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 20459500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 20459500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 20459500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 20459500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 20459500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 20459500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.088922 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.088922 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.088922 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 67971.760797 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 67971.760797 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 67971.760797 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 67971.760797 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 67971.760797 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 67971.760797 # average overall mshr miss latency -system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 199.907137 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.005714 # Average number of references to valid blocks. -system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 168.211200 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 31.695937 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005133 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.000967 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.006101 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 350 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 91 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 259 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010681 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3947 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3947 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits -system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 299 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 352 # number of ReadReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 85 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 299 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses -system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20136000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3695250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 23831250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5999750 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 5999750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 20136000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9695000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 29831000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 20136000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9695000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 29831000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 301 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 301 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993355 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.994350 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993355 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995444 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67344.481605 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69721.698113 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67702.414773 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70585.294118 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70585.294118 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67344.481605 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70253.623188 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68263.157895 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67344.481605 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70253.623188 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68263.157895 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 437 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16419500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3036250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 19455750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4955250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4955250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16419500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7991500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 24411000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16419500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7991500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24411000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 54914.715719 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 57287.735849 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55272.017045 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58297.058824 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58297.058824 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 54914.715719 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57909.420290 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 55860.411899 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 54914.715719 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57909.420290 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 55860.411899 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 354 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 352 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 85 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 85 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 600 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 876 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19136 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 27968 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 439 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 439 100.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 439 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) -system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 500000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 222000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) -system.membus.trans_dist::ReadReq 351 # Transaction distribution -system.membus.trans_dist::ReadResp 350 # Transaction distribution -system.membus.trans_dist::ReadExReq 85 # Transaction distribution -system.membus.trans_dist::ReadExResp 85 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 871 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 871 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27840 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 27840 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 436 # Request fanout histogram -system.membus.snoop_fanout::mean 0 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 436 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 0 # Request fanout histogram -system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 436 # Request fanout histogram -system.membus.reqLayer0.occupancy 519500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 1.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 4048500 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 14.6 # Layer utilization (%) - ----------- End Simulation Statistics ---------- |